coreboot-gerrit May 2021

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Change in coreboot[master]: soc/amd/common/block/pci: Introduce struct pci_routing_info
by Raul Rangel (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/53922 to look at the new patch set (#3). Change subject: soc/amd/common/block/pci: Introduce struct pci_routing_info ...................................................................... soc/amd/common/block/pci: Introduce struct pci_routing_info This struct is similar to `struct pci_routing` defined in picasso/pcie_gpp.c. It additionally contains the irq used for the bridge and is structured in a way that the FSP can provide via HOB. The next set of CLs will migrate the pci routing functions used by picasso into common and enable pci routing table generation for cezanne. BUG=b:184766519 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1a8d988d125f407f0aa7bc1722d432446aa9aff8 --- M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h M src/soc/amd/common/block/pci/Makefile.inc A src/soc/amd/common/block/pci/pci_routing_info.c 3 files changed, 85 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/53922/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/53922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a8d988d125f407f0aa7bc1722d432446aa9aff8 Gerrit-Change-Number: 53922 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: Generate PCI GPP ACPI names
by Felix Held (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52870 ) Change subject: soc/amd/cezanne: Generate PCI GPP ACPI names ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5134d1dba4fcb9ce8cc4bfad1c619331a95f3b11 Gerrit-Change-Number: 52870 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Fri, 07 May 2021 23:02:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: herobrine: Enable macronix SPI config
by Shelley Chen (Code Review) 08 May '21

08 May '21

Attention is currently required from: Ravi kumar, Sajida Bhanu, mturney mturney, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50583 ) Change subject: herobrine: Enable macronix SPI config ...................................................................... Patch Set 33: (1 comment) Patchset: PS32: > Ok that's fair. […] Reopening this comment so that it's obvious that Julius' comment hasn't been resolved yet. -- To view, visit https://review.coreboot.org/c/coreboot/+/50583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I505ee95d9f2ca16baf244135b3e2e8fe72f93491 Gerrit-Change-Number: 50583 Gerrit-PatchSet: 33 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 22:55:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/sn65dsi86: Switch EDID reading to use "indirect mode"
by Douglas Anderson (Code Review) 08 May '21

08 May '21

Attention is currently required from: Vinod Polimera, Julius Werner. Douglas Anderson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52959 ) Change subject: drivers/sn65dsi86: Switch EDID reading to use "indirect mode" ...................................................................... Patch Set 5: (1 comment) File src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c: https://review.coreboot.org/c/coreboot/+/52959/comment/f4341904_3f7758fd PS5, Line 253: if (i2c_writeb(bus, chip, SN_AUX_CMD_REG, AUX_CMD_SEND | (cmd << 4)) || : !wait_ms(100, !i2c_readb(bus, chip, SN_AUX_CMD_REG, &buf) && : !(buf & AUX_CMD_SEND)) || : i2c_readb(bus, chip, SN_AUX_CMD_STATUS_REG, &buf) || : (buf & (NAT_I2C_FAIL | AUX_SHORT | AUX_DFER | AUX_RPLY_TOUT))) { : printk(BIOS_ERR, "ERROR: aux command send failed\n"); : return CB_ERR; : } If it were me, I wouldn't have written separate commands. The way this is written makes me think too hard, and no good has ever come of thinking too hard. Splitting it up into separate calls would also potentially allow you to give better error message (like saying _which_ of the error bits was set). I won't insist on it, but it'd be nice. One other note: the way you have things setup right now if you ever get a single error then you'll fail forevermore. If you want to avoid that, you need to manually "ack" the error bits at the beginning of the function. It also might not hurt to have a comment saying that, in theory, we think SHORT might come up with some panels and need to be handled but we haven't seen a panel like that yet. If anyone ever does see SHORT come up in the future it would maybe be a little quicker for them to realize that the problem was... -- To view, visit https://review.coreboot.org/c/coreboot/+/52959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65f80193380d3c3841f9f5c26897ed672f45e15a Gerrit-Change-Number: 52959 Gerrit-PatchSet: 5 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 22:50:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Disable CBFS MCACHE again
by Julius Werner (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53933 ) Change subject: soc/amd/picasso: Disable CBFS MCACHE again ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Did this ever work and break again or was it just broken the whole time? The error message looks like the mcache just wasn't transferred correctly from PSP memory to DRAM. Please check the transfer logic (e.g. hexdump _cbfs_mcache at the end of the PSP execution and right before this assertion, they should be the same but they probably aren't). Or maybe you're trying to make a CBFS access before the code copying the transfer buffer into DRAM runs? (Interestingly, the FMAP access before that runs fine. Are you using FMAP_CACHE? If so, that would suggest that the FMAP cache was transferred correctly already...) -- To view, visit https://review.coreboot.org/c/coreboot/+/53933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68b4b73670e750207414f0d85ff96f21481be8ce Gerrit-Change-Number: 53933 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Fri, 07 May 2021 22:48:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/n130wu: Use device alias names in devicetree
by Felix Singer (Code Review) 08 May '21

08 May '21

Attention is currently required from: Michael Niewöhner. Hello Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/53939 to look at the new patch set (#2). Change subject: mb/clevo/n130wu: Use device alias names in devicetree ...................................................................... mb/clevo/n130wu: Use device alias names in devicetree Switch to device alias names in devicetree. Remove unnecessary comments since the names are self-explanatory. Change-Id: Id486d9bd44bd7ba6a93a5f757af487b211e58efa Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb 1 file changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/53939/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id486d9bd44bd7ba6a93a5f757af487b211e58efa Gerrit-Change-Number: 53939 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/clevo/n130wu: Use device alias names in devicetree
by Felix Singer (Code Review) 08 May '21

08 May '21

Attention is currently required from: Michael Niewöhner. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53939 ) Change subject: mb/clevo/n130wu: Use device alias names in devicetree ...................................................................... mb/clevo/n130wu: Use device alias names in devicetree Switch to device alias names in devicetree. Remove unnecessary comments since the names are self explanatory. Change-Id: Id486d9bd44bd7ba6a93a5f757af487b211e58efa Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb 1 file changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/53939/1 diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index 788b233..2ad6853 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -44,9 +44,9 @@ end device domain 0 on subsystemid 0x1558 0x1313 inherit - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem - device pci 14.0 on # USB xHCI + device ref igpu on end + device ref sa_thermal on end + device ref south_xhci on register "SsicPortEnable" = "0" # USB2 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, right @@ -62,19 +62,19 @@ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C, right register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left end - device pci 14.2 on end # Thermal Subsystem - device pci 16.0 on # Management Engine Interface 1 + device ref thermal on end + device ref heci1 on register "HeciEnabled" = "1" end - device pci 17.0 on # SATA + device ref sata on register "SataSalpSupport" = "0" # Ports register "SataPortsEnable[0]" = "1" register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[2]" = "1" end - device pci 19.0 on end # UART 2 - device pci 1c.0 on # PCI Express Port 1 + device ref uart2 on end + device ref pcie_rp1 on device pci 00.0 on end # x4 TBT register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" @@ -84,7 +84,7 @@ register "PcieRpLtrEnable[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X" end - device pci 1c.4 on # PCI Express Port 5 + device ref pcie_rp5 on device pci 00.0 on end # x1 LAN register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" @@ -92,7 +92,7 @@ register "PcieRpClkSrcNumber[4]" = "3" register "PcieRpLtrEnable[4]" = "1" end - device pci 1c.5 on # PCI Express Port 6 + device ref pcie_rp6 on device pci 00.0 on end # x1 WLAN register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" @@ -101,7 +101,7 @@ register "PcieRpLtrEnable[5]" = "1" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" end - device pci 1d.0 on # PCI Express Port 9 + device ref pcie_rp9 on device pci 00.0 on end # x4 M.2/M (J_SSD1) register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" @@ -110,7 +110,7 @@ register "PcieRpLtrEnable[8]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" end - device pci 1f.0 on # LPC Interface + device ref lpc_espi on register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641" register "gen3_dec" = "0x00040069" @@ -119,14 +119,14 @@ device pnp 0c31.0 on end end end - device pci 1f.1 on end # P2SB - device pci 1f.2 on # Power Management Controller + device ref p2sb on end + device ref pmc on register "gpe0_dw0" = "GPP_C" register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" end - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI + device ref hda on end + device ref smbus on end + device ref fast_spi on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/53939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id486d9bd44bd7ba6a93a5f757af487b211e58efa Gerrit-Change-Number: 53939 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/clevo/n130wu: Unhide P2SB device
by Felix Singer (Code Review) 08 May '21

08 May '21

Attention is currently required from: Michael Niewöhner. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53938 ) Change subject: mb/clevo/n130wu: Unhide P2SB device ...................................................................... mb/clevo/n130wu: Unhide P2SB device There is no need to make P2SB hidden. Thus, unhide it. Change-Id: I2e6b2e2c8dc9d08b4260fc7bc9d7795e2747de75 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/53938/1 diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index 1102f4e..788b233 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -119,7 +119,7 @@ device pnp 0c31.0 on end end end - device pci 1f.1 hidden end # P2SB + device pci 1f.1 on end # P2SB device pci 1f.2 on # Power Management Controller register "gpe0_dw0" = "GPP_C" register "gpe0_dw1" = "GPP_D" -- To view, visit https://review.coreboot.org/c/coreboot/+/53938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e6b2e2c8dc9d08b4260fc7bc9d7795e2747de75 Gerrit-Change-Number: 53938 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/clevo/n130wu: Remove host bridge from devicetree
by Felix Singer (Code Review) 08 May '21

08 May '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53937 ) Change subject: mb/clevo/n130wu: Remove host bridge from devicetree ...................................................................... mb/clevo/n130wu: Remove host bridge from devicetree Remove host bridge from devicetree since it is enabled by chipset devicetree. Change-Id: I44d5ee82ce8b8d5c092feca2562f763a3fbb3cae Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/53937/1 diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index 0a0cdf4..1102f4e 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -44,7 +44,6 @@ end device domain 0 on subsystemid 0x1558 0x1313 inherit - device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on end # SA thermal subsystem device pci 14.0 on # USB xHCI -- To view, visit https://review.coreboot.org/c/coreboot/+/53937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44d5ee82ce8b8d5c092feca2562f763a3fbb3cae Gerrit-Change-Number: 53937 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data
by Raul Rangel (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52913 to look at the new patch set (#6). Change subject: soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data ...................................................................... soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data The method now dynamically allocates the pirq structure and uses the get_pci_routing_table method. BUG=b:184766519 TEST=Build guybrush and verify picasso SSDT has not changed. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I297fc3ca7227fb4794ac70bd046ce2f93da8b869 --- M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h M src/soc/amd/common/block/pci/pci_routing_info.c M src/soc/amd/picasso/pcie_gpp.c 3 files changed, 35 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/52913/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/52913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I297fc3ca7227fb4794ac70bd046ce2f93da8b869 Gerrit-Change-Number: 52913 Gerrit-PatchSet: 6 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021