coreboot-gerrit May 2021

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Change in gerrit-avatars[master]: Add profile picture
by Patrik Tesarik (Code Review) 08 May '21

08 May '21

Patrik Tesarik has uploaded this change for review. ( https://review.coreboot.org/c/gerrit-avatars/+/53941 ) Change subject: Add profile picture ...................................................................... Add profile picture Signed-off-by: Patrik Tesarik <patrik.tesarik(a)rub.de> Change-Id: I79b716ff7eeb2c5e677d749767fe7898210e9a9e --- A 1002397.jpg 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/gerrit-avatars refs/changes/41/53941/1 diff --git a/1002397.jpg b/1002397.jpg new file mode 100644 index 0000000..d986762 --- /dev/null +++ b/1002397.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/gerrit-avatars/+/53941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: gerrit-avatars Gerrit-Branch: master Gerrit-Change-Id: I79b716ff7eeb2c5e677d749767fe7898210e9a9e Gerrit-Change-Number: 53941 Gerrit-PatchSet: 1 Gerrit-Owner: Patrik Tesarik Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC] device: Introduce new method for setting device states
by build bot (Jenkins) (Code Review) 08 May '21

08 May '21

Attention is currently required from: Felix Singer, Raul Rangel, Furquan Shaikh, Matt DeVillier, Angel Pons, Michael Niewöhner, Patrick Rudolph, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52493 ) Change subject: [RFC] device: Introduce new method for setting device states ...................................................................... Patch Set 21: (1 comment) File src/device/devenmap.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118786): https://review.coreboot.org/c/coreboot/+/52493/comment/052c6861_bfcc8576 PS21, Line 17: if (devmap[i].hook) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/52493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70fde306c65a8881f565c5f923be20f380ea64d3 Gerrit-Change-Number: 52493 Gerrit-PatchSet: 21 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 08 May 2021 00:39:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] device: Introduce new method for setting device states
by Felix Singer (Code Review) 08 May '21

08 May '21

Attention is currently required from: Felix Singer, Raul Rangel, Furquan Shaikh, Matt DeVillier, Angel Pons, Michael Niewöhner, Patrick Rudolph, Felix Held. Hello build bot (Jenkins), Raul Rangel, Nico Huber, Furquan Shaikh, Matt DeVillier, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, Patrick Rudolph, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52493 to look at the new patch set (#21). Change subject: [RFC] device: Introduce new method for setting device states ...................................................................... [RFC] device: Introduce new method for setting device states We mostly use the same mechanism for setting the state of internal devices, but we copy it over again and again. Thus, introduce a new method trying to reduce redundant code. Basically, this uses an array of structs containing the DEVFN number, its corresponding FSP option and an indicator if the FSP option is inverted. The struct maps the device to its related FSP option and `set_dev_state_by_devicetree()` iterates over the array using the usual mechanism. Unresolved issues: - Where should fspdevmap{.c,.h} be implemented? Tested in combination with CB:52835 and roda/rw14. Works. Change-Id: I70fde306c65a8881f565c5f923be20f380ea64d3 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/device/Makefile.inc A src/device/devenmap.c A src/include/device/devenmap.h 3 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/52493/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/52493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70fde306c65a8881f565c5f923be20f380ea64d3 Gerrit-Change-Number: 52493 Gerrit-PatchSet: 21 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: trogdor: Add backlight support for sn65dsi86bridge for Homestar
by Julius Werner (Code Review) 08 May '21

08 May '21

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52663 ) Change subject: trogdor: Add backlight support for sn65dsi86bridge for Homestar ...................................................................... trogdor: Add backlight support for sn65dsi86bridge for Homestar Add backlight support in sn65dsi86bridge through the AUX channel using eDP DPCD registers, which is needed on the GOOGLE_HOMESTAR board. Change-Id: Ie700080f1feabe2d3397c38088a64cff27bfbe55 Signed-off-by: Vinod Polimera <vpolimer(a)codeaurora.org> Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52663 Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h M src/mainboard/google/trogdor/Kconfig M src/mainboard/google/trogdor/mainboard.c 4 files changed, 31 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Douglas Anderson: Looks good to me, approved diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c index 1cbf6fd..2ba0977 100644 --- a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c @@ -31,6 +31,14 @@ #define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ #define DP_LANE_COUNT_MASK 0xf +/* Backlight configuration */ +#define DP_BACKLIGHT_MODE_SET 0x721 +#define DP_BACKLIGHT_CONTROL_MODE_MASK 0x3 +#define DP_BACKLIGHT_CONTROL_MODE_DPCD 0x2 +#define DP_DISPLAY_CONTROL_REGISTER 0x720 +#define DP_BACKLIGHT_ENABLE 0x1 +#define DP_BACKLIGHT_BRIGHTNESS_MSB 0x722 + /* link configuration */ #define DP_LINK_BW_SET 0x100 #define DP_LINK_BW_1_62 0x06 @@ -497,6 +505,20 @@ printk(BIOS_ERR, "ERROR: Link training failed 10 times\n"); } +void sn65dsi86_backlight_enable(uint8_t bus, uint8_t chip) +{ + uint8_t val = DP_BACKLIGHT_CONTROL_MODE_DPCD; + sn65dsi86_bridge_aux_request(bus, chip, DP_BACKLIGHT_MODE_SET, 1, DPCD_WRITE, &val); + + val = 0xff; + sn65dsi86_bridge_aux_request(bus, chip, DP_BACKLIGHT_BRIGHTNESS_MSB, 1, + DPCD_WRITE, &val); + + val = DP_BACKLIGHT_ENABLE; + sn65dsi86_bridge_aux_request(bus, chip, DP_DISPLAY_CONTROL_REGISTER, 1, + DPCD_WRITE, &val); +} + static void sn65dsi86_bridge_assr_config(uint8_t bus, uint8_t chip, int enable) { if (enable) diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h index 83b940b..0f03080 100644 --- a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h @@ -18,5 +18,6 @@ struct edid *edid, uint32_t num_of_lines, uint32_t dsi_bpp); enum cb_err sn65dsi86_bridge_read_edid(uint8_t bus, uint8_t chip, struct edid *out); +void sn65dsi86_backlight_enable(uint8_t bus, uint8_t chip); #endif diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig index 5538205..4a2630d 100644 --- a/src/mainboard/google/trogdor/Kconfig +++ b/src/mainboard/google/trogdor/Kconfig @@ -7,6 +7,11 @@ config TROGDOR_REV0 def_bool n +config TROGDOR_HAS_BRIDGE_BACKLIGHT + bool + default y if BOARD_GOOGLE_HOMESTAR + default n + config TROGDOR_HAS_FINGERPRINT bool default y if BOARD_GOOGLE_COACHZ diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index 61a64f8..864bd6d 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -83,6 +83,9 @@ return; sn65dsi86_bridge_configure(BRIDGE_BUS, BRIDGE_CHIP, edid, lanes, dsi_bpp); + if (CONFIG(TROGDOR_HAS_BRIDGE_BACKLIGHT)) + sn65dsi86_backlight_enable(BRIDGE_BUS, BRIDGE_CHIP); + mdp_dsi_video_config(edid); mdss_dsi_video_mode_config(edid, dsi_bpp); mdp_dsi_video_on(); -- To view, visit https://review.coreboot.org/c/coreboot/+/52663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie700080f1feabe2d3397c38088a64cff27bfbe55 Gerrit-Change-Number: 52663 Gerrit-PatchSet: 6 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/sn65dsi86: Switch EDID reading to use "indirect mode"
by Julius Werner (Code Review) 08 May '21

08 May '21

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52959 ) Change subject: drivers/sn65dsi86: Switch EDID reading to use "indirect mode" ...................................................................... drivers/sn65dsi86: Switch EDID reading to use "indirect mode" The SN65DSI86 eDP bridge supports two ways to read the EDID: for now we've been using "direct mode", which works by basically making the bridge I2C device listen to another chip address besides its own and proxy all requests received there directly to the eDP AUX channel. The great part about that mode is that it is super easy and hassle-free to use. The not so great part about it is that it doesn't work: for EDID extensions, the last byte (which happens to contain the checksum) is somehow always read as zero. We presume this is a hardware bug in the bridge part. The other, much more annoying way is "indirect mode", where each byte transmitted over the AUX channel has to be manually set up in the I2C registers of the bridge, just like we're already doing with DPCD transactions. Thankfully, we can reuse most of the DPCD code for this so it's not a lot of extra code. It's a bit slower but not as much as you'd expect (26ms instead of 18ms on my board), and the difference is not very relevant compared to common total times for display init. Also, some of the (previously unused) enum definitions for the AUX_CMD mode field of the bridge had just been plain wrong for some reason, and needed to be fixed to make this work. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I65f80193380d3c3841f9f5c26897ed672f45e15a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52959 Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c 1 file changed, 143 insertions(+), 75 deletions(-) Approvals: build bot (Jenkins): Verified Douglas Anderson: Looks good to me, approved diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c index ca41cdb..1cbf6fd 100644 --- a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c @@ -127,14 +127,22 @@ enum i2c_over_aux { I2C_OVER_AUX_WRITE_MOT_0 = 0x0, I2C_OVER_AUX_READ_MOT_0 = 0x1, - I2C_OVER_AUX_WRITE_STATUS_UPDATE_0 = 0x4, - I2C_OVER_AUX_WRITE_MOT_1 = 0x5, - I2C_OVER_AUX_READ_MOT_1 = 0x6, - I2C_OVER_AUX_WRITE_STATUS_UPDATE_1 = 0x7, + I2C_OVER_AUX_WRITE_STATUS_UPDATE_0 = 0x2, + I2C_OVER_AUX_WRITE_MOT_1 = 0x4, + I2C_OVER_AUX_READ_MOT_1 = 0x5, + I2C_OVER_AUX_WRITE_STATUS_UPDATE_1 = 0x6, NATIVE_AUX_WRITE = 0x8, NATIVE_AUX_READ = 0x9, }; +enum aux_cmd_status { + NAT_I2C_FAIL = 1 << 6, + AUX_SHORT = 1 << 5, + AUX_DFER = 1 << 4, + AUX_RPLY_TOUT = 1 << 3, + SEND_INT = 1 << 0, +}; + enum ml_tx_mode { MAIN_LINK_OFF = 0x0, NORMAL_MODE = 0x1, @@ -150,9 +158,13 @@ REDRIVER_SEMI_AUTO_LINK_TRAINING = 0xb, }; -enum dpcd_request { - DPCD_READ = 0x0, - DPCD_WRITE = 0x1, +enum aux_request { + DPCD_READ, + DPCD_WRITE, + I2C_RAW_READ, + I2C_RAW_WRITE, + I2C_RAW_READ_AND_STOP, + I2C_RAW_WRITE_AND_STOP, }; enum { @@ -169,29 +181,131 @@ 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 }; -enum cb_err sn65dsi86_bridge_read_edid(uint8_t bus, uint8_t chip, struct edid *out) +static bool request_is_write(enum aux_request request) { - int ret; + switch (request) { + case I2C_RAW_WRITE_AND_STOP: + case I2C_RAW_WRITE: + case DPCD_WRITE: + return true; + default: + return false; + } +} + +static enum i2c_over_aux get_aux_cmd(enum aux_request request, uint32_t remaining_after_this) +{ + switch (request) { + case I2C_RAW_WRITE_AND_STOP: + if (!remaining_after_this) + return I2C_OVER_AUX_WRITE_MOT_0; + /* fallthrough */ + case I2C_RAW_WRITE: + return I2C_OVER_AUX_WRITE_MOT_1; + case I2C_RAW_READ_AND_STOP: + if (!remaining_after_this) + return I2C_OVER_AUX_READ_MOT_0; + /* fallthrough */ + case I2C_RAW_READ: + return I2C_OVER_AUX_READ_MOT_1; + case DPCD_WRITE: + return NATIVE_AUX_WRITE; + case DPCD_READ: + default: + return NATIVE_AUX_READ; + } +} + +static cb_err_t sn65dsi86_bridge_aux_request(uint8_t bus, + uint8_t chip, + unsigned int target_reg, + unsigned int total_size, + enum aux_request request, + uint8_t *data) +{ + int i; + uint32_t length; + uint8_t buf; + uint8_t reg; + + /* Clear old status flags just in case they're left over from a previous transfer. */ + i2c_writeb(bus, chip, SN_AUX_CMD_STATUS_REG, + NAT_I2C_FAIL | AUX_SHORT | AUX_DFER | AUX_RPLY_TOUT | SEND_INT); + + while (total_size) { + length = MIN(total_size, 16); + total_size -= length; + + enum i2c_over_aux cmd = get_aux_cmd(request, total_size); + if (i2c_writeb(bus, chip, SN_AUX_CMD_REG, (cmd << 4)) || + i2c_writeb(bus, chip, SN_AUX_ADDR_19_16_REG, (target_reg >> 16) & 0xF) || + i2c_writeb(bus, chip, SN_AUX_ADDR_15_8_REG, (target_reg >> 8) & 0xFF) || + i2c_writeb(bus, chip, SN_AUX_ADDR_7_0_REG, (target_reg) & 0xFF) || + i2c_writeb(bus, chip, SN_AUX_LENGTH_REG, length)) + return CB_ERR; + + if (request_is_write(request)) { + reg = SN_AUX_WDATA_REG_0; + for (i = 0; i < length; i++) + if (i2c_writeb(bus, chip, reg++, *data++)) + return CB_ERR; + } + + if (i2c_writeb(bus, chip, SN_AUX_CMD_REG, AUX_CMD_SEND | (cmd << 4))) + return CB_ERR; + if (!wait_ms(100, !i2c_readb(bus, chip, SN_AUX_CMD_REG, &buf) && + !(buf & AUX_CMD_SEND))) { + printk(BIOS_ERR, "ERROR: AUX_CMD_SEND not acknowledged\n"); + return CB_ERR; + } + if (i2c_readb(bus, chip, SN_AUX_CMD_STATUS_REG, &buf)) + return CB_ERR; + if (buf & (NAT_I2C_FAIL | AUX_SHORT | AUX_DFER | AUX_RPLY_TOUT)) { + printk(BIOS_ERR, "ERROR: AUX command failed, status = %#x\n", buf); + return CB_ERR; + } + + if (!request_is_write(request)) { + reg = SN_AUX_RDATA_REG_0; + for (i = 0; i < length; i++) { + if (i2c_readb(bus, chip, reg++, &buf)) + return CB_ERR; + *data++ = buf; + } + } + } + + return CB_SUCCESS; +} + +cb_err_t sn65dsi86_bridge_read_edid(uint8_t bus, uint8_t chip, struct edid *out) +{ + cb_err_t err; u8 edid[EDID_LENGTH * 2]; int edid_size = EDID_LENGTH; - /* Send I2C command to claim EDID I2c slave */ - i2c_writeb(bus, chip, SN_I2C_CLAIM_ADDR_EN1, (EDID_I2C_ADDR << 1) | 0x1); - - /* read EDID */ - ret = i2c_read_bytes(bus, EDID_I2C_ADDR, 0x0, edid, EDID_LENGTH); - if (ret != 0) { + uint8_t reg_addr = 0; + err = sn65dsi86_bridge_aux_request(bus, chip, EDID_I2C_ADDR, 1, + I2C_RAW_WRITE, &reg_addr); + if (!err) + err = sn65dsi86_bridge_aux_request(bus, chip, EDID_I2C_ADDR, EDID_LENGTH, + I2C_RAW_READ_AND_STOP, edid); + if (err) { printk(BIOS_ERR, "ERROR: Failed to read EDID.\n"); - return CB_ERR; + return err; } if (edid[EDID_EXTENSION_FLAG]) { edid_size += EDID_LENGTH; - ret = i2c_read_bytes(bus, EDID_I2C_ADDR, EDID_LENGTH, - &edid[EDID_LENGTH], EDID_LENGTH); - if (ret != 0) { + reg_addr = EDID_LENGTH; + err = sn65dsi86_bridge_aux_request(bus, chip, EDID_I2C_ADDR, 1, + I2C_RAW_WRITE, &reg_addr); + if (!err) + err = sn65dsi86_bridge_aux_request(bus, chip, EDID_I2C_ADDR, + EDID_LENGTH, I2C_RAW_READ_AND_STOP, &edid[EDID_LENGTH]); + if (err) { printk(BIOS_ERR, "Failed to read EDID ext block.\n"); - return CB_ERR; + return err; } } @@ -203,67 +317,21 @@ return CB_SUCCESS; } -static void sn65dsi86_bridge_dpcd_request(uint8_t bus, - uint8_t chip, - unsigned int dpcd_reg, - unsigned int len, - enum dpcd_request request, - uint8_t *data) -{ - int i; - uint32_t length; - uint8_t buf; - uint8_t reg; - - while (len) { - length = MIN(len, 16); - - i2c_writeb(bus, chip, SN_AUX_ADDR_19_16_REG, (dpcd_reg >> 16) & 0xF); - i2c_writeb(bus, chip, SN_AUX_ADDR_15_8_REG, (dpcd_reg >> 8) & 0xFF); - i2c_writeb(bus, chip, SN_AUX_ADDR_7_0_REG, (dpcd_reg) & 0xFF); - i2c_writeb(bus, chip, SN_AUX_LENGTH_REG, length); /* size of 1 Byte data */ - if (request == DPCD_WRITE) { - reg = SN_AUX_WDATA_REG_0; - for (i = 0; i < length; i++) - i2c_writeb(bus, chip, reg++, *data++); - - i2c_writeb(bus, chip, - SN_AUX_CMD_REG, AUX_CMD_SEND | (NATIVE_AUX_WRITE << 4)); - } else { - i2c_writeb(bus, chip, - SN_AUX_CMD_REG, AUX_CMD_SEND | (NATIVE_AUX_READ << 4)); - if (!wait_ms(100, - !i2c_readb(bus, chip, SN_AUX_CMD_REG, - &buf) && !(buf & AUX_CMD_SEND))) { - printk(BIOS_ERR, "ERROR: aux command send failed\n"); - } - - reg = SN_AUX_RDATA_REG_0; - for (i = 0; i < length; i++) { - i2c_readb(bus, chip, reg++, &buf); - *data++ = buf; - } - } - - len -= length; - } -} - static void sn65dsi86_bridge_valid_dp_rates(uint8_t bus, uint8_t chip, bool rate_valid[]) { unsigned int rate_per_200khz; uint8_t dpcd_val; int i, j; - sn65dsi86_bridge_dpcd_request(bus, chip, - DP_BRIDGE_DPCD_REV, 1, DPCD_READ, &dpcd_val); + sn65dsi86_bridge_aux_request(bus, chip, + DP_BRIDGE_DPCD_REV, 1, DPCD_READ, &dpcd_val); if (dpcd_val >= DP_BRIDGE_14) { /* eDP 1.4 devices must provide a custom table */ uint16_t sink_rates[DP_MAX_SUPPORTED_RATES] = {0}; - sn65dsi86_bridge_dpcd_request(bus, chip, DP_SUPPORTED_LINK_RATES, - sizeof(sink_rates), - DPCD_READ, (void *)sink_rates); + sn65dsi86_bridge_aux_request(bus, chip, DP_SUPPORTED_LINK_RATES, + sizeof(sink_rates), + DPCD_READ, (void *)sink_rates); for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { rate_per_200khz = le16_to_cpu(sink_rates[i]); @@ -288,7 +356,7 @@ } /* On older versions best we can do is use DP_MAX_LINK_RATE */ - sn65dsi86_bridge_dpcd_request(bus, chip, DP_MAX_LINK_RATE, 1, DPCD_READ, &dpcd_val); + sn65dsi86_bridge_aux_request(bus, chip, DP_MAX_LINK_RATE, 1, DPCD_READ, &dpcd_val); switch (dpcd_val) { default: @@ -410,8 +478,8 @@ * at DisplayPort address 0x0010A prior to link training. */ buf = 0x1; - sn65dsi86_bridge_dpcd_request(bus, chip, - DP_BRIDGE_CONFIGURATION_SET, 1, DPCD_WRITE, &buf); + sn65dsi86_bridge_aux_request(bus, chip, + DP_BRIDGE_CONFIGURATION_SET, 1, DPCD_WRITE, &buf); int i; /* Kernel driver suggests to retry this up to 10 times if it fails. */ for (i = 0; i < 10; i++) { @@ -441,7 +509,7 @@ { uint8_t lane_count; - sn65dsi86_bridge_dpcd_request(bus, chip, DP_MAX_LANE_COUNT, 1, DPCD_READ, &lane_count); + sn65dsi86_bridge_aux_request(bus, chip, DP_MAX_LANE_COUNT, 1, DPCD_READ, &lane_count); lane_count &= DP_LANE_COUNT_MASK; i2c_write_field(bus, chip, SN_SSC_CONFIG_REG, MIN(lane_count, 3), 3, 4); -- To view, visit https://review.coreboot.org/c/coreboot/+/52959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65f80193380d3c3841f9f5c26897ed672f45e15a Gerrit-Change-Number: 52959 Gerrit-PatchSet: 8 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso: move acpigen_dptc_call_alib to new common alib
by build bot (Jenkins) (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53940 ) Change subject: soc/amd/picasso: move acpigen_dptc_call_alib to new common alib ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/picasso/root_complex.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118782): https://review.coreboot.org/c/coreboot/+/53940/comment/e7ba16fb_75eb317d PS1, Line 211: acpigen_dptc_call_alib("DEFB", (uint8_t *)(void *)&default_input, sizeof(default_input)); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/53940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0f7da12429b6278d1e4bc5d6650c7ee0f3b5209 Gerrit-Change-Number: 53940 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Sat, 08 May 2021 00:11:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: adjust the size for RO/RW mcache
by Julius Werner (Code Review) 08 May '21

08 May '21

Attention is currently required from: Furquan Shaikh, Nick Vaccaro, Zhuohao Lee. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53908 ) Change subject: mb/google/volteer: adjust the size for RO/RW mcache ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Agree with you about the RW_PERCENTAGE. […] In that case, I would just set the size for those specific chipsets to 8K and the default for everything else to 16K. I think defaults should always be set so they'll do the right thing for new stuff that will be added in the future, and I assume the available CAR size should only get bigger on future chipsets. Might as well make sure less people will run into trouble with this in the future. -- To view, visit https://review.coreboot.org/c/coreboot/+/53908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9552bc9fa5d36b1ca662c9da030ae7b137b60a8 Gerrit-Change-Number: 53908 Gerrit-PatchSet: 2 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 23:56:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: trogdor: Add backlight support for sn65dsi86bridge for Homestar
by Douglas Anderson (Code Review) 08 May '21

08 May '21

Attention is currently required from: Shelley Chen, Ravi kumar, Julius Werner, mturney mturney. Douglas Anderson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52663 ) Change subject: trogdor: Add backlight support for sn65dsi86bridge for Homestar ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Patchset: PS5: As far as I can tell this looks fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/52663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie700080f1feabe2d3397c38088a64cff27bfbe55 Gerrit-Change-Number: 52663 Gerrit-PatchSet: 5 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Fri, 07 May 2021 23:49:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: trogdor: Add backlight support for sn65dsi86bridge for Homestar
by Julius Werner (Code Review) 08 May '21

08 May '21

Attention is currently required from: Shelley Chen, Ravi kumar, Douglas Anderson, mturney mturney. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52663 ) Change subject: trogdor: Add backlight support for sn65dsi86bridge for Homestar ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: This suddenly became somewhat urgent so let me take over the last few bits of polish needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/52663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie700080f1feabe2d3397c38088a64cff27bfbe55 Gerrit-Change-Number: 52663 Gerrit-PatchSet: 5 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Douglas Anderson <dianders(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Fri, 07 May 2021 23:38:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: trogdor: Add backlight support for sn65dsi86bridge for Homestar
by Julius Werner (Code Review) 08 May '21

08 May '21

Attention is currently required from: Shelley Chen, Ravi kumar, Douglas Anderson, Julius Werner, mturney mturney. Julius Werner has uploaded a new patch set (#5) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/52663 ) Change subject: trogdor: Add backlight support for sn65dsi86bridge for Homestar ...................................................................... trogdor: Add backlight support for sn65dsi86bridge for Homestar Add backlight support in sn65dsi86bridge through the AUX channel using eDP DPCD registers, which is needed on the GOOGLE_HOMESTAR board. Change-Id: Ie700080f1feabe2d3397c38088a64cff27bfbe55 Signed-off-by: Vinod Polimera <vpolimer(a)codeaurora.org> Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h M src/mainboard/google/trogdor/Kconfig M src/mainboard/google/trogdor/mainboard.c 4 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/52663/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie700080f1feabe2d3397c38088a64cff27bfbe55 Gerrit-Change-Number: 52663 Gerrit-PatchSet: 5 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Douglas Anderson <dianders(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021