coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/amd/common/block/pci: Introduce struct pci_routing_info
by Raul Rangel (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53922 ) Change subject: soc/amd/common/block/pci: Introduce struct pci_routing_info ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/block/include/amdblocks/amd_pci_util.h: https://review.coreboot.org/c/coreboot/+/53922/comment/33279e3f_2f08f667 PS3, Line 47: struct pci_routing_info { > should this be marked as packed, since this is what we get from fsp via hob? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/53922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a8d988d125f407f0aa7bc1722d432446aa9aff8 Gerrit-Change-Number: 53922 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 08 May 2021 01:43:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRT
by Raul Rangel (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52917 ) Change subject: soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRT ...................................................................... Patch Set 7: (2 comments) File src/soc/amd/common/block/pci/acpi_prt.c: https://review.coreboot.org/c/coreboot/+/52917/comment/b2767ace_592d9818 PS6, Line 98: LNKA > is this correct? from the code above, i'd assume to rather be \\_SB. […] Done https://review.coreboot.org/c/coreboot/+/52917/comment/ca982d81_55665960 PS6, Line 167: LNKA > same here Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76 Gerrit-Change-Number: 52917 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 08 May 2021 01:43:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/pci: Introduce struct pci_routing_info
by Raul Rangel (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/53922 to look at the new patch set (#4). Change subject: soc/amd/common/block/pci: Introduce struct pci_routing_info ...................................................................... soc/amd/common/block/pci: Introduce struct pci_routing_info This struct is similar to `struct pci_routing` defined in picasso/pcie_gpp.c. It additionally contains the irq used for the bridge and is structured in a way that the FSP can provide via HOB. The next set of CLs will migrate the pci routing functions used by picasso into common and enable pci routing table generation for cezanne. BUG=b:184766519 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1a8d988d125f407f0aa7bc1722d432446aa9aff8 --- M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h M src/soc/amd/common/block/pci/Makefile.inc A src/soc/amd/common/block/pci/pci_routing_info.c 3 files changed, 85 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/53922/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/53922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a8d988d125f407f0aa7bc1722d432446aa9aff8 Gerrit-Change-Number: 53922 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data
by Raul Rangel (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52913 ) Change subject: soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data ...................................................................... Patch Set 8: (2 comments) File src/soc/amd/common/fsp/pci/pirq.c: https://review.coreboot.org/c/coreboot/+/52913/comment/07f70270_eb74f3dd PS3, Line 19: > might be a good idea to check if entries is != 0 before calling calloc Done https://review.coreboot.org/c/coreboot/+/52913/comment/34f91f3f_51b67d4c PS3, Line 23: return; > add some BIOS_ERR printk here? for a valid routing table calloc isn't supposed to return NULL Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I297fc3ca7227fb4794ac70bd046ce2f93da8b869 Gerrit-Change-Number: 52913 Gerrit-PatchSet: 8 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 08 May 2021 01:43:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Merge soc_memory_init_params() into its caller
by Felix Singer (Code Review) 08 May '21

08 May '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Paul Menzel, Angel Pons, Arthur Heymans, Michael Niewöhner, Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52491 ) Change subject: soc/intel/cannonlake: Merge soc_memory_init_params() into its caller ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52491/comment/1a7280b2_b12891b1 PS7, Line 13: > Have you tested if this affects the binary? Just tested. Binary remains the same. -- To view, visit https://review.coreboot.org/c/coreboot/+/52491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3b6395ea5d5cb714a412c856d66d4a9bcbd9c12 Gerrit-Change-Number: 52491 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 08 May 2021 01:38:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Merge soc_memory_init_params() into its caller
by Felix Singer (Code Review) 08 May '21

08 May '21

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Angel Pons, Arthur Heymans, Michael Niewöhner, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Tim Wawrzynczak, Paul Menzel, Angel Pons, Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52491 to look at the new patch set (#10). Change subject: soc/intel/cannonlake: Merge soc_memory_init_params() into its caller ...................................................................... soc/intel/cannonlake: Merge soc_memory_init_params() into its caller soc_memory_init_params() does not only configure memory init parameters. Despite its name, it also configures many other things. Therefore, merge it into its caller function platform_fsp_memory_init_params_cb() to prevent confusions. Built clevo/l140cu with BUILD_TIMELESS=1. coreboot.rom remains the same. Change-Id: Id3b6395ea5d5cb714a412c856d66d4a9bcbd9c12 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/cannonlake/romstage/fsp_params.c 1 file changed, 5 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/52491/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/52491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3b6395ea5d5cb714a412c856d66d4a9bcbd9c12 Gerrit-Change-Number: 52491 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation: Add suggestion to document flag days
by Julius Werner (Code Review) 08 May '21

08 May '21

Attention is currently required from: Martin Roth, Piotr Król, Felix Held. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52576 ) Change subject: Documentation: Add suggestion to document flag days ...................................................................... Patch Set 1: (1 comment) File Documentation/getting_started/gerrit_guidelines.md: https://review.coreboot.org/c/coreboot/+/52576/comment/38883a32_a2a5f6a6 PS1, Line 332: requires a change in all mainboards using it) needs to be documented. > 1. Sign of life - certain string showing as early as possible on platform boot Open to discussion but I think this might be reasonable as a Kconfig (depending on how complicated it looks). > 2. sortbootorder as payload - would payload supporting only one vendor will be merged to coreboot? > 3. Custom SeaBIOS features which SeaBIOS upstream won't accept - this is general pattern related to other payloads (memtest, ipxe), including customization and configuration of those payloads Payload stuff I'd consider separate -- I think for payloads we already have an existing assumption that payloads don't need to be in-tree and that the payload interface is somewhat stable (of course, sometimes changes are unavoidable, but we could discuss more rules about how those should be communicated). So I think it should be okay if you uprev coreboot but keep your payload code untouched and expect them to continue working together most of the time. > 4. Experimental uCode inclusion Is this more than just setting the microcode file Kconfig to some file you maintain out-of-tree? (I think that's considered supported.) > 5. ACPI difference, mentioned in email thread, required for OS compatibility I haven't fully understood that problem, but generally, I think OS compatibility stuff is something that can be included upstream (depends on whether we're talking about a publicly available OS or something custom used only by your customer, maybe). Again, I think coreboot itself gets developed as a sort of monolithic blob with no stable boundaries on its inside, but the boundary between coreboot and the payload or the OS is different and we spend more effort trying to keep that as stable and widely compatible as possible. > Maybe we should be clear about saying that coreboot is too expensive for small OEM/ODM, they should go to IBVs. I don't think anyone is trying to build any intentional barriers here to keep someone out. We're all interested in making all the things that people want to do with coreboot as cheap and easy as possible. I just don't think there are any easy answers to your problems here. "Everyone stop making big API changes" isn't something we can do, then we can't really develop big new features at all anymore. Then the project would basically become irrelevant and die out. "Spend a ton of extra effort on every global change you make" also becomes prohibitive and will effectively cause the same problems as forbidding big changes completely. I think we can discuss smaller effort process changes (e.g. writing spatches where it makes sense), but it needs to balance out the effort saved on one side and the extra effort caused on the other. -- To view, visit https://review.coreboot.org/c/coreboot/+/52576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7c01a0f1008821ebbda43a426ba1e3d6410e861 Gerrit-Change-Number: 52576 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 08 May 2021 01:26:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Enable GNB IO-APIC _PRT
by Felix Held (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53936 ) Change subject: soc/amd/cezanne: Enable GNB IO-APIC _PRT ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4df5a4583f14044d2efcde3a9de9dd85e898a11d Gerrit-Change-Number: 53936 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Sat, 08 May 2021 01:18:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: add GNB IOAPIC support
by Felix Held (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52905 ) Change subject: soc/amd/cezanne: add GNB IOAPIC support ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: can't +2 this one, since i was the initial author -- To view, visit https://review.coreboot.org/c/coreboot/+/52905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e127ce500d052783f0a6e13fb2ad16a8e408b0e Gerrit-Change-Number: 52905 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Sat, 08 May 2021 01:17:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Generate PCI routing table
by Felix Held (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51556 ) Change subject: soc/amd/cezanne: Generate PCI routing table ...................................................................... Patch Set 9: Code-Review+2 (1 comment) File src/soc/amd/cezanne/pcie_gpp.c: https://review.coreboot.org/c/coreboot/+/51556/comment/b65b43ee_ba22f574 PS6, Line 68: 0 > false would be the correct type here this is solved differently now, so the comment doesn't apply any more -- To view, visit https://review.coreboot.org/c/coreboot/+/51556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb559335435a95e73640e6d7fb224e16e0592326 Gerrit-Change-Number: 51556 Gerrit-PatchSet: 9 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-CC: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Sat, 08 May 2021 01:16:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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coreboot-gerrit May 2021