coreboot-gerrit May 2021

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Change in coreboot[master]: [RFC] device: Introduce new method for setting device states
by Nico Huber (Code Review) 08 May '21

08 May '21

Attention is currently required from: Felix Singer, Raul Rangel, Furquan Shaikh, Matt DeVillier, Angel Pons, Michael Niewöhner, Patrick Rudolph, Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52493 ) Change subject: [RFC] device: Introduce new method for setting device states ...................................................................... Patch Set 21: (1 comment) File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/52493/comment/4678949f_407d3846 PS13, Line 461: if (!xdci_can_enable()) : params->XdciEnable = 0; > I had the idea that we could set related UPDs in that function, too, like UPDs that depend on the enabled state of the device e.g. PchHdaEnable, PchHdaVcType etc. or ScsEmmcHs400Enabled, PchScsEmmcHs400DllDataValid, PchScsEmmcHs400RxStrobeDll1. > > This way, these UPDs would be grouped together in these functions (on function per device). However, we would have to pass that FSP*_UPD pointer around, which is pretty ugly. For everything there is a pattern. Usually one would pass a void pointer through the generic API. However, I have to say that this might be going in the wrong direction. At some point, we'd have to ask: why a table? It seems to make sense if it's about one thing common to all entries, e.g. the enable state. If we allow just everything, we can as well call the functions directly (with some alignment maybe?). pch_enable_dev (&params->PchHdaEnable, PCH_DEVFN_HDA); pch_enable_dev (&params->ShowSpiController, PCH_DEVFN_SPI); pch_enable_emmc(params, PCH_DEVFN_EMMC); pch_enable_dci (... That's a table too of sorts. -- To view, visit https://review.coreboot.org/c/coreboot/+/52493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70fde306c65a8881f565c5f923be20f380ea64d3 Gerrit-Change-Number: 52493 Gerrit-PatchSet: 21 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 08 May 2021 12:25:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] device: Introduce new method for setting device states
by Felix Singer (Code Review) 08 May '21

08 May '21

Attention is currently required from: Nico Huber, Raul Rangel, Furquan Shaikh, Matt DeVillier, Angel Pons, Michael Niewöhner, Patrick Rudolph, Felix Held. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52493 ) Change subject: [RFC] device: Introduce new method for setting device states ...................................................................... Patch Set 21: (1 comment) File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/52493/comment/604d2be0_eb236e8c PS13, Line 461: if (!xdci_can_enable()) : params->XdciEnable = 0; > I had the idea that we could set related UPDs in that function, too, like UPDs that depend on the enabled state of the device e.g. PchHdaEnable, PchHdaVcType etc. or ScsEmmcHs400Enabled, PchScsEmmcHs400DllDataValid, PchScsEmmcHs400RxStrobeDll1. > > This way, these UPDs would be grouped together in these functions (on function per device). However, we would have to pass that FSP*_UPD pointer around, which is pretty ugly. More ugly FSP hacks because why not? :) -- To view, visit https://review.coreboot.org/c/coreboot/+/52493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70fde306c65a8881f565c5f923be20f380ea64d3 Gerrit-Change-Number: 52493 Gerrit-PatchSet: 21 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 08 May 2021 12:02:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: payload/external/tianocore/Kconfig: Toggle default payload
by Patrik Tesarik (Code Review) 08 May '21

08 May '21

Attention is currently required from: Martin Roth, Matt DeVillier, Stefan Reinauer, Angel Pons, Andrey Petrov, Patrick Rudolph. Patrik Tesarik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53934 ) Change subject: payload/external/tianocore/Kconfig: Toggle default payload ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/apollolake/Kconfig: https://review.coreboot.org/c/coreboot/+/53934/comment/e74a0d16_9f640e2c PS4, Line 113: select TIANOCORE_PREFER_UEFIPAYLOAD > Hrm, try to append `if PAYLOAD_TIANOCORE` to make Kconfig happy Already done. Let's see if that fixes this. -- To view, visit https://review.coreboot.org/c/coreboot/+/53934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib50fdaf2cd5c599e497ef8ca06e5692a9e69b813 Gerrit-Change-Number: 53934 Gerrit-PatchSet: 5 Gerrit-Owner: Patrik Tesarik Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 08 May 2021 11:41:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: payload/external/tianocore/Kconfig: Toggle default payload
by Patrik Tesarik (Code Review) 08 May '21

08 May '21

Attention is currently required from: Martin Roth, Matt DeVillier, Stefan Reinauer, Andrey Petrov, Patrick Rudolph, Patrik Tesarik. Hello build bot (Jenkins), Martin Roth, Matt DeVillier, Stefan Reinauer, Angel Pons, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/53934 to look at the new patch set (#5). Change subject: payload/external/tianocore/Kconfig: Toggle default payload ...................................................................... payload/external/tianocore/Kconfig: Toggle default payload Since the UP2 board features a Apollo Lake SoC, the default Kconfig value of the Tianocore payload (CorebootPayload build from MrChromebox's source tree) is not working on the actual hardware. This patch enables a board/SoC specific toggle for the payload choice prompt by introducing a boolean option and selecting it at the SoC level for Apollo Lake. Signed-off-by: Patrik Tesarik <patrik.tesarik(a)rub.de> Change-Id: Ib50fdaf2cd5c599e497ef8ca06e5692a9e69b813 --- M payloads/external/tianocore/Kconfig M src/soc/intel/apollolake/Kconfig 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/53934/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/53934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib50fdaf2cd5c599e497ef8ca06e5692a9e69b813 Gerrit-Change-Number: 53934 Gerrit-PatchSet: 5 Gerrit-Owner: Patrik Tesarik Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrik Tesarik Gerrit-MessageType: newpatchset

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Change in coreboot[master]: payload/external/tianocore/Kconfig: Toggle default payload
by Patrik Tesarik (Code Review) 08 May '21

08 May '21

Attention is currently required from: Martin Roth, Stefan Reinauer, Angel Pons, Andrey Petrov, Patrick Rudolph. Patrik Tesarik has removed Angel Pons from this change. ( https://review.coreboot.org/c/coreboot/+/53934 ) Change subject: payload/external/tianocore/Kconfig: Toggle default payload ...................................................................... Removed reviewer Angel Pons. -- To view, visit https://review.coreboot.org/c/coreboot/+/53934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib50fdaf2cd5c599e497ef8ca06e5692a9e69b813 Gerrit-Change-Number: 53934 Gerrit-PatchSet: 4 Gerrit-Owner: Patrik Tesarik Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/intel/skylake: Set proper defaults in chipset devicetree
by Nico Huber (Code Review) 08 May '21

08 May '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53925 ) Change subject: soc/intel/skylake: Set proper defaults in chipset devicetree ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/skylake/chipset.cb: https://review.coreboot.org/c/coreboot/+/53925/comment/e1cb7b77_0730c4f6 PS1, Line 63: n end # P2SB : device pci 1f.2 alias pmc on > Thanks for clarification! There's something about children, I guess a "hidden" bridge wouldn't be followed down. But the reason to not use `hidden` for skylake/ is simple: FSP is not as broken as for the newer platforms. -- To view, visit https://review.coreboot.org/c/coreboot/+/53925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20b8cbe536da70fccc3d11e1eedf4a5e14bfc862 Gerrit-Change-Number: 53925 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 08 May 2021 11:03:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Set proper defaults in chipset devicetree
by Michael Niewöhner (Code Review) 08 May '21

08 May '21

Attention is currently required from: Felix Singer, Nico Huber, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53925 ) Change subject: soc/intel/skylake: Set proper defaults in chipset devicetree ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/soc/intel/skylake/chipset.cb: https://review.coreboot.org/c/coreboot/+/53925/comment/cf1bb238_c9537b84 PS1, Line 63: n end # P2SB : device pci 1f.2 alias pmc on > If P2SB is enabled in the devicetree but FSP hides the P2SB device before coreboot sees it, then cor […] Thanks for clarification! -- To view, visit https://review.coreboot.org/c/coreboot/+/53925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20b8cbe536da70fccc3d11e1eedf4a5e14bfc862 Gerrit-Change-Number: 53925 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 08 May 2021 10:43:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Set proper defaults in chipset devicetree
by Angel Pons (Code Review) 08 May '21

08 May '21

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Change in coreboot[master]: soc/intel/skylake: Set proper defaults in chipset devicetree
by Angel Pons (Code Review) 08 May '21

08 May '21

Attention is currently required from: Felix Singer, Nico Huber, Michael Niewöhner, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53925 ) Change subject: soc/intel/skylake: Set proper defaults in chipset devicetree ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/skylake/chipset.cb: https://review.coreboot.org/c/coreboot/+/53925/comment/2602a110_b4a259d0 PS1, Line 63: n end # P2SB : device pci 1f.2 alias pmc on If P2SB is enabled in the devicetree but FSP hides the P2SB device before coreboot sees it, then coreboot will just report something about `static device not found, disabling it` and move on. > Yes I mean that hidden keyword. It does not hide things, but AFAICS it controls if a pci device that was hidden by the FSP before gets probed or not. That comment on pci_scan_hidden_device says: "This is useful when devices would like to be described in the devicetree.cb file [...] but the platform firmware hides the device (makes the device invisible to PCI enumeration) before PCI enumeration takes place." I'm unsure what exactly that means for the P2SB device, which does not have any children. The `hidden` keyword is a kludge. It means "This PCI device exists but is not discoverable (cannot be found using the standard PCI enumeration procedure); assume it is present and otherwise behaves as a regular PCI device". It kind of tells coreboot to have faith in cursed hardware behaving properly. > > we shouldn't use `device pci` in such a case. > > Mhh, you mean because it's not about the device actually, but the children (bus scanned or not)? The device is not discoverable using standard PCI enumeration; therefore, it can't be a PCI device. -- To view, visit https://review.coreboot.org/c/coreboot/+/53925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20b8cbe536da70fccc3d11e1eedf4a5e14bfc862 Gerrit-Change-Number: 53925 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 08 May 2021 10:42:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Set proper defaults in chipset devicetree
by Michael Niewöhner (Code Review) 08 May '21

08 May '21

Attention is currently required from: Felix Singer, Nico Huber, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53925 ) Change subject: soc/intel/skylake: Set proper defaults in chipset devicetree ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/skylake/chipset.cb: https://review.coreboot.org/c/coreboot/+/53925/comment/47d24f5b_97d8a3d2 PS1, Line 63: n end # P2SB : device pci 1f.2 alias pmc on Yes I mean that hidden keyword. It does not hide things, but AFAICS it controls if a pci device that was hidden by the FSP before gets probed or not. That comment on pci_scan_hidden_device says: "This is useful when devices would like to be described in the devicetree.cb file [...] but the platform firmware hides the device (makes the device invisible to PCI enumeration) before PCI enumeration takes place." I'm unsure what exactly that means for the P2SB device, which does not have any children. > we shouldn't use `device pci` in such a case. Mhh, you mean because it's not about the device actually, but the children (bus scanned or not)? -- To view, visit https://review.coreboot.org/c/coreboot/+/53925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20b8cbe536da70fccc3d11e1eedf4a5e14bfc862 Gerrit-Change-Number: 53925 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 08 May 2021 10:33:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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coreboot-gerrit May 2021