coreboot-gerrit May 2021

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Change in coreboot[master]: soc/amd/cezanne/acpi/soc: call WAL1 for AC/DC state ALIB call
by Felix Held (Code Review) 08 May '21

08 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53921 ) Change subject: soc/amd/cezanne/acpi/soc: call WAL1 for AC/DC state ALIB call ...................................................................... soc/amd/cezanne/acpi/soc: call WAL1 for AC/DC state ALIB call BUG=b:187212773, b:185481298 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2cf50257d767525d682602cdcc5547bf001fe2ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/53921 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/acpi/soc.asl 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl index f7781da..5039ca1 100644 --- a/src/soc/amd/cezanne/acpi/soc.asl +++ b/src/soc/amd/cezanne/acpi/soc.asl @@ -17,6 +17,8 @@ #include "pci0.asl" } /* End \_SB scope */ +#include <soc/amd/common/acpi/alib.asl> + #include <soc/amd/common/acpi/platform.asl> #include <soc/amd/common/acpi/sleepstates.asl> @@ -30,4 +32,6 @@ */ Method (PNOT) { + /* Report AC/DC state to ALIB using WAL1() */ + \WAL1 () } -- To view, visit https://review.coreboot.org/c/coreboot/+/53921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cf50257d767525d682602cdcc5547bf001fe2ac Gerrit-Change-Number: 53921 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso/acpi/cpu: move WAL1 method that calls ALIB to common
by Felix Held (Code Review) 08 May '21

08 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53920 ) Change subject: soc/amd/picasso/acpi/cpu: move WAL1 method that calls ALIB to common ...................................................................... soc/amd/picasso/acpi/cpu: move WAL1 method that calls ALIB to common TEST=Mandolin still boots into Linux and there's no ACPI warning in dmesg. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7e6d38ebeae5e55a4a65930b989838532ab9c446 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53920 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/soc/amd/common/acpi/alib.asl M src/soc/amd/picasso/acpi/cpu.asl M src/soc/amd/picasso/acpi/sb_pci0_fch.asl 3 files changed, 31 insertions(+), 29 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/acpi/alib.asl b/src/soc/amd/common/acpi/alib.asl new file mode 100644 index 0000000..bf4a137 --- /dev/null +++ b/src/soc/amd/common/acpi/alib.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/alib.h> + +/* The ALIB method object is defined in an SSDT */ +External(\_SB.ALIB, MethodObj) + +/* Wrapper method that calls ALIB function 1 to report current AC/DC state. */ +Method (WAL1) +{ + /* Send ALIB Function 1 the AC/DC state */ + Local0 = Buffer (0x03) {} + CreateWordField (Local0, 0, F1SZ) + CreateByteField (Local0, 2, F1DA) + + /* First argument is size i.e. 3 bytes */ + F1SZ = 3 + + /* + * Second argument is power state i.e. AC or DC. + * ALIB expects AC = 0, DC = 1. + * PWRS reports AC = 1, DC = 0. + * + * Hence, need to invert the state of PWRS. + */ + F1DA = \PWRS ^ 1 + + Printf ("ALIB call: func 1 params %o", Local0) + \_SB.ALIB (ALIB_FUNCTION_REPORT_AC_DC_STATE, Local0) +} diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl index 869602c..b7395fc 100644 --- a/src/soc/amd/picasso/acpi/cpu.asl +++ b/src/soc/amd/picasso/acpi/cpu.asl @@ -1,32 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <amdblocks/alib.h> - -/* - * Wrapper method that calls ALIB function 1 to report current AC/DC state. - */ -Method (WAL1) -{ - /* Send ALIB Function 1 the AC/DC state */ - Local0 = Buffer (0x03) {} - CreateWordField (Local0, 0, F1SZ) - CreateByteField (Local0, 2, F1DA) - - /* First argument is size i.e. 3 bytes */ - F1SZ = 3 - - /* - * Second argument is power state i.e. AC or DC. - * ALIB expects AC = 0, DC = 1. - * PWRS reports AC = 1, DC = 0. - * - * Hence, need to invert the state of PWRS. - */ - F1DA = \PWRS ^ 1 - - Printf ("ALIB call: func 1 params %o", Local0) - \_SB.ALIB (ALIB_FUNCTION_REPORT_AC_DC_STATE, Local0) -} +#include <soc/amd/common/acpi/alib.asl> Method (PNOT) { diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 0b253c9..e948bca 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -2,8 +2,6 @@ #include <arch/ioapic.h> -External(\_SB.ALIB, MethodObj) - /* System Bus */ /* _SB.PCI0 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/53920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e6d38ebeae5e55a4a65930b989838532ab9c446 Gerrit-Change-Number: 53920 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso,common: move ALIB DPTC parameter struct to common code
by Felix Held (Code Review) 08 May '21

08 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53918 ) Change subject: soc/amd/picasso,common: move ALIB DPTC parameter struct to common code ...................................................................... soc/amd/picasso,common: move ALIB DPTC parameter struct to common code Also add an alib_ prefix to avoid possible name collisions. TEST=Timeless build for Mandolin results in identical binary. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib0f220a4cde6da764bb8bc589b5f44ae16496bd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53918 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/include/amdblocks/alib.h M src/soc/amd/picasso/root_complex.c 2 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/alib.h b/src/soc/amd/common/block/include/amdblocks/alib.h index e11b1ae..5e92924 100644 --- a/src/soc/amd/common/block/include/amdblocks/alib.h +++ b/src/soc/amd/common/block/include/amdblocks/alib.h @@ -16,6 +16,11 @@ ALIB_DPTC_SLOW_PPT_LIMIT_ID = 0x7, }; +struct alib_dptc_param { + uint8_t id; + uint32_t value; +} __packed; + #endif /* !__ACPI__ */ #endif /* AMD_COMMON_ALIB_H */ diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index c0b444f..979da3e 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -20,14 +20,9 @@ #define DPTC_TOTAL_UPDATE_PARAMS 4 -struct dptc_param { - uint8_t id; - uint32_t value; -} __packed; - struct dptc_input { uint16_t size; - struct dptc_param params[DPTC_TOTAL_UPDATE_PARAMS]; + struct alib_dptc_param params[DPTC_TOTAL_UPDATE_PARAMS]; } __packed; #define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/53918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0f220a4cde6da764bb8bc589b5f44ae16496bd7 Gerrit-Change-Number: 53918 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso,common: move ALIB DPTC IDs to common code
by Felix Held (Code Review) 08 May '21

08 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53917 ) Change subject: soc/amd/picasso,common: move ALIB DPTC IDs to common code ...................................................................... soc/amd/picasso,common: move ALIB DPTC IDs to common code These parameter IDs are defined in the AGESA Interface specification #55483. This patch also adds a ALIB_DPTC_ prefix to the IDs and makes the names more consistent. TEST=Timeless build for Mandolin results in identical binary. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I75e0504f6274ad50c53faa8fcbde4d6821d85a04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53917 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/include/amdblocks/alib.h M src/soc/amd/picasso/root_complex.c 2 files changed, 32 insertions(+), 27 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/alib.h b/src/soc/amd/common/block/include/amdblocks/alib.h index a59ba8b..e11b1ae 100644 --- a/src/soc/amd/common/block/include/amdblocks/alib.h +++ b/src/soc/amd/common/block/include/amdblocks/alib.h @@ -6,4 +6,16 @@ #define ALIB_FUNCTION_REPORT_AC_DC_STATE 0x1 #define ALIB_FUNCTION_DYNAMIC_POWER_THERMAL_CONFIG 0xc +#ifndef __ACPI__ + +/* parameter IDs for the ALIB_FUNCTION_DYNAMIC_POWER_THERMAL_CONFIG function */ +enum alib_dptc_parameter_ids { + ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID = 0x3, + ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID = 0x5, + ALIB_DPTC_FAST_PPT_LIMIT_ID = 0x6, + ALIB_DPTC_SLOW_PPT_LIMIT_ID = 0x7, +}; + +#endif /* !__ACPI__ */ + #endif /* AMD_COMMON_ALIB_H */ diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 932ca76..c0b444f 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -18,13 +18,6 @@ #include <soc/iomap.h> #include "chip.h" -enum { - THERMAL_CONTROL_LIMIT_ID = 0x3, - SUSTAINED_POWER_LIMIT_PARAM_ID = 0x5, - FAST_PPT_LIMIT_PARAM_ID = 0x6, - SLOW_PPT_LIMIT_PARAM_ID = 0x7, -}; - #define DPTC_TOTAL_UPDATE_PARAMS 4 struct dptc_param { @@ -38,27 +31,27 @@ } __packed; #define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow) \ - { \ - .size = sizeof(struct dptc_input), \ - .params = { \ - { \ - .id = THERMAL_CONTROL_LIMIT_ID, \ - .value = _thermctllmit, \ - }, \ - { \ - .id = SUSTAINED_POWER_LIMIT_PARAM_ID, \ - .value = _sustained, \ - }, \ - { \ - .id = FAST_PPT_LIMIT_PARAM_ID, \ - .value = _fast, \ - }, \ - { \ - .id = SLOW_PPT_LIMIT_PARAM_ID, \ - .value = _slow, \ - }, \ + { \ + .size = sizeof(struct dptc_input), \ + .params = { \ + { \ + .id = ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID, \ + .value = _thermctllmit, \ }, \ - } + { \ + .id = ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID, \ + .value = _sustained, \ + }, \ + { \ + .id = ALIB_DPTC_FAST_PPT_LIMIT_ID, \ + .value = _fast, \ + }, \ + { \ + .id = ALIB_DPTC_SLOW_PPT_LIMIT_ID, \ + .value = _slow, \ + }, \ + }, \ + } /* * * +--------------------------------+ -- To view, visit https://review.coreboot.org/c/coreboot/+/53917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75e0504f6274ad50c53faa8fcbde4d6821d85a04 Gerrit-Change-Number: 53917 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso/root_complex: move DPTC_TOTAL_UPDATE_PARAMS out of enum
by Felix Held (Code Review) 08 May '21

08 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53916 ) Change subject: soc/amd/picasso/root_complex: move DPTC_TOTAL_UPDATE_PARAMS out of enum ...................................................................... soc/amd/picasso/root_complex: move DPTC_TOTAL_UPDATE_PARAMS out of enum The other enum entries are control IDs for the ALIB_FUNCTION_DYNAMIC_POWER_THERMAL_CONFIG ALIB function while DPTC_TOTAL_UPDATE_PARAMS is the total number of configuration settings that will get passed as parameter in the ALIB call, so it shouldn't be part of that enum. TEST=Timeless build for Mandolin results in identical binary. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0cb9e9d2ba579a74d916011b4ead71cc86d69a24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53916 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/root_complex.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 47b3a43..932ca76 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -23,9 +23,10 @@ SUSTAINED_POWER_LIMIT_PARAM_ID = 0x5, FAST_PPT_LIMIT_PARAM_ID = 0x6, SLOW_PPT_LIMIT_PARAM_ID = 0x7, - DPTC_TOTAL_UPDATE_PARAMS = 4, }; +#define DPTC_TOTAL_UPDATE_PARAMS 4 + struct dptc_param { uint8_t id; uint32_t value; -- To view, visit https://review.coreboot.org/c/coreboot/+/53916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cb9e9d2ba579a74d916011b4ead71cc86d69a24 Gerrit-Change-Number: 53916 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd: factor out ACPI ALIB function numbers to common code
by Felix Held (Code Review) 08 May '21

08 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53915 ) Change subject: soc/amd: factor out ACPI ALIB function numbers to common code ...................................................................... soc/amd: factor out ACPI ALIB function numbers to common code The ACPI ALIB function numbers are defined in the AMD Generic Encapsulated Software Architecture (AGESA™) Interface Specification (document #55483). TEST=Timeless build stays the same for Mandolin (Picasso) and Gardenia (Stoneyridge). Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I290ef0db32c65ebb2bbbe4f65db4df772b884161 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53915 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/soc/amd/common/block/include/amdblocks/alib.h M src/soc/amd/picasso/acpi/cpu.asl M src/soc/amd/picasso/root_complex.c M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 4 files changed, 17 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/alib.h b/src/soc/amd/common/block/include/amdblocks/alib.h new file mode 100644 index 0000000..a59ba8b --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/alib.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_COMMON_ALIB_H +#define AMD_COMMON_ALIB_H + +#define ALIB_FUNCTION_REPORT_AC_DC_STATE 0x1 +#define ALIB_FUNCTION_DYNAMIC_POWER_THERMAL_CONFIG 0xc + +#endif /* AMD_COMMON_ALIB_H */ diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl index 294d89f..869602c 100644 --- a/src/soc/amd/picasso/acpi/cpu.asl +++ b/src/soc/amd/picasso/acpi/cpu.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/alib.h> + /* * Wrapper method that calls ALIB function 1 to report current AC/DC state. */ @@ -23,7 +25,7 @@ F1DA = \PWRS ^ 1 Printf ("ALIB call: func 1 params %o", Local0) - \_SB.ALIB (1, Local0) + \_SB.ALIB (ALIB_FUNCTION_REPORT_AC_DC_STATE, Local0) } Method (PNOT) diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 292ee20..47b3a43 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -2,6 +2,7 @@ #include <acpi/acpigen.h> #include <amdblocks/acpi.h> +#include <amdblocks/alib.h> #include <amdblocks/memmap.h> #include <amdblocks/ioapic.h> #include <arch/ioapic.h> @@ -18,7 +19,6 @@ #include "chip.h" enum { - ALIB_DPTCI_FUNCTION_ID = 0xc, THERMAL_CONTROL_LIMIT_ID = 0x3, SUSTAINED_POWER_LIMIT_PARAM_ID = 0x5, FAST_PPT_LIMIT_PARAM_ID = 0x6, @@ -196,7 +196,7 @@ /* \_SB.ALIB(0xc, buf_name) */ acpigen_emit_namestring("\\_SB.ALIB"); - acpigen_write_integer(ALIB_DPTCI_FUNCTION_ID); + acpigen_write_integer(ALIB_FUNCTION_DYNAMIC_POWER_THERMAL_CONFIG); acpigen_emit_namestring(buf_name); } diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 4580b77..78ce889 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/alib.h> + External(\_SB.ALIB, MethodObj) /* System Bus */ @@ -142,7 +144,7 @@ F1SZ = 3 F1DA= \PWRS - \_SB.ALIB(1, F1BF) + \_SB.ALIB(ALIB_FUNCTION_REPORT_AC_DC_STATE, F1BF) } /* End Method(_SB._INI) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/53915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I290ef0db32c65ebb2bbbe4f65db4df772b884161 Gerrit-Change-Number: 53915 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Generate PCI routing table
by Felix Held (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51556 ) Change subject: soc/amd/cezanne: Generate PCI routing table ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51556/comment/33a2f6d7_ae67f994 PS10, Line 10: > It says in the comment `Enable GNB IO-APIC`. yep, that's the gnb ioapic enablement bug. see CB:52905 -- To view, visit https://review.coreboot.org/c/coreboot/+/51556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb559335435a95e73640e6d7fb224e16e0592326 Gerrit-Change-Number: 51556 Gerrit-PatchSet: 10 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 08 May 2021 17:54:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/pci: Introduce struct pci_routing_info
by Felix Held (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53922 ) Change subject: soc/amd/common/block/pci: Introduce struct pci_routing_info ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File src/soc/amd/common/block/include/amdblocks/amd_pci_util.h: https://review.coreboot.org/c/coreboot/+/53922/comment/512c9c9b_09834e0a PS3, Line 47: struct pci_routing_info { > does the __packed go before or after the struct definition? i always put it before the definition an […] ok, both are valid, so let's keep it like it is now -- To view, visit https://review.coreboot.org/c/coreboot/+/53922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a8d988d125f407f0aa7bc1722d432446aa9aff8 Gerrit-Change-Number: 53922 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Sat, 08 May 2021 17:49:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRT
by Felix Held (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52917 ) Change subject: soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRT ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76 Gerrit-Change-Number: 52917 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Sat, 08 May 2021 16:51:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data
by Felix Held (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52913 ) Change subject: soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I297fc3ca7227fb4794ac70bd046ce2f93da8b869 Gerrit-Change-Number: 52913 Gerrit-PatchSet: 8 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Sat, 08 May 2021 16:50:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2021