coreboot-gerrit May 2021

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Change in coreboot[master]: arch/riscv: Fix interrupt_handler to adapt to machine length
by Xiang W (Code Review) 08 May '21

08 May '21

Xiang W has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53945 ) Change subject: arch/riscv: Fix interrupt_handler to adapt to machine length ...................................................................... arch/riscv: Fix interrupt_handler to adapt to machine length The length of mcause is related to the word length of the machine. Using a constant to remove the most significant bit is not an ideal method. This patch uses the gcc built-in macro __riscv_xlen to remove the highest bit of mcause Change-Id: I516fbec1dba11ce6efd3523555c48e972d2cf418 Signed-off-by: Xiang W <wxjstz(a)126.com> --- M src/arch/riscv/trap_handler.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/53945/1 diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 32b2c40..bebed23 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -69,7 +69,7 @@ static void interrupt_handler(trapframe *tf) { - uint64_t cause = tf->cause & ~0x8000000000000000ULL; + uint64_t cause = tf->cause & ~(1ULL << (__riscv_xlen - 1)); switch (cause) { case IRQ_M_TIMER: -- To view, visit https://review.coreboot.org/c/coreboot/+/53945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I516fbec1dba11ce6efd3523555c48e972d2cf418 Gerrit-Change-Number: 53945 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang W <wxjstz(a)126.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/riscv: Fixed exception handling when CONFIG_RISCV_WORKING_HARTID...
by Xiang Wang (Code Review) 08 May '21

08 May '21

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37461 ) Change subject: arch/riscv: Fixed exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0 ...................................................................... arch/riscv: Fixed exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0 Change-Id: Ic45560b4bfbf9366425ef4006ac2765113457349 Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M src/arch/riscv/trap_util.S 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/37461/1 diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 8aba48b..8c1f6cc 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -118,6 +118,7 @@ # someday this gets fixed. //csrr sp, mhartid csrr sp, 0xf14 + addi sp, sp, -CONFIG_RISCV_WORKING_HARTID .Lsmp_hang: bnez sp, .Lsmp_hang -- To view, visit https://review.coreboot.org/c/coreboot/+/37461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic45560b4bfbf9366425ef4006ac2765113457349 Gerrit-Change-Number: 37461 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/riscv: Add SMP support for exception handling
by Xiang W (Code Review) 08 May '21

08 May '21

Attention is currently required from: Philipp Hug, ron minnich. Hello build bot (Jenkins), Philipp Hug, ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/53944 to look at the new patch set (#3). Change subject: arch/riscv: Add SMP support for exception handling ...................................................................... arch/riscv: Add SMP support for exception handling The previous exception handling code does not support SMP. If start Linux directly through coreboot, it will be a big problem. Change-Id: Id8d3085bcd6f8883b08384f6bbf14052fd81fc2b Signed-off-by: Xiang W <wxjstz(a)126.com> --- M src/arch/riscv/bootblock.S M src/arch/riscv/ramstage.S M src/arch/riscv/trap_util.S 3 files changed, 17 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/53944/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/53944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8d3085bcd6f8883b08384f6bbf14052fd81fc2b Gerrit-Change-Number: 53944 Gerrit-PatchSet: 3 Gerrit-Owner: Xiang W <wxjstz(a)126.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/riscv: Add SMP support for exception handling
by Xiang W (Code Review) 08 May '21

08 May '21

Attention is currently required from: Philipp Hug, ron minnich. Hello build bot (Jenkins), Philipp Hug, ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/53944 to look at the new patch set (#2). Change subject: arch/riscv: Add SMP support for exception handling ...................................................................... arch/riscv: Add SMP support for exception handling The previous exception handling code does not support SMP. If start Linux directly through coreboot, it will be a big problem. Change-Id: Id8d3085bcd6f8883b08384f6bbf14052fd81fc2b Signed-off-by: Xiang W <wxjstz(a)126.com> --- M src/arch/riscv/bootblock.S M src/arch/riscv/ramstage.S M src/arch/riscv/trap_util.S 3 files changed, 17 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/53944/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8d3085bcd6f8883b08384f6bbf14052fd81fc2b Gerrit-Change-Number: 53944 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang W <wxjstz(a)126.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/riscv: Add SMP support for exception handling
by Xiang W (Code Review) 08 May '21

08 May '21

Xiang W has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53944 ) Change subject: arch/riscv: Add SMP support for exception handling ...................................................................... arch/riscv: Add SMP support for exception handling The previous exception handling code does not support SMP. If start Linux directly through coreboot, it will be a big problem. Change-Id: Id8d3085bcd6f8883b08384f6bbf14052fd81fc2b Signed-off-by: Xiang W <wxjstz(a)12.com> --- M src/arch/riscv/bootblock.S M src/arch/riscv/ramstage.S M src/arch/riscv/trap_util.S 3 files changed, 17 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/53944/1 diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 12fda32..e21047c 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -36,15 +36,16 @@ STORE t1, 0(t0) li t1, RISCV_PGSIZE - HLS_SIZE add sp, t0, t1 + # mscratch points to the entry of the exception stack + li t1, RISCV_PGSIZE / 2 - MENTRY_FRAME_SIZE + add t1, t1, t0 + csrw mscratch, t1 # initialize hart-local storage csrr a0, mhartid csrrw a1, mscratch, zero call hls_init - li a0, CONFIG_RISCV_WORKING_HARTID - call smp_pause - # initialize entry of interrupt/exception la t0, trap_entry csrw mtvec, t0 @@ -54,6 +55,10 @@ # set up the mstatus register call mstatus_init + + li a0, CONFIG_RISCV_WORKING_HARTID + call smp_pause + tail main // These codes need to be implemented on a specific SoC. diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S index 921c46d..df5ce68 100644 --- a/src/arch/riscv/ramstage.S +++ b/src/arch/riscv/ramstage.S @@ -25,14 +25,15 @@ STORE t1, 0(t0) li t1, RISCV_PGSIZE - HLS_SIZE add sp, t0, t1 + # mscratch points to the entry of the exception stack + li t1, RISCV_PGSIZE / 2 - MENTRY_FRAME_SIZE + add t1, t1, t0 + csrw mscratch, t1 # initialize hart-local storage csrr a0, mhartid call hls_init - li a0, CONFIG_RISCV_WORKING_HARTID - call smp_pause - # initialize entry of interrupt/exception la t0, trap_entry csrw mtvec, t0 @@ -43,6 +44,10 @@ call exit_car # set up the mstatus register call mstatus_init + + li a0, CONFIG_RISCV_WORKING_HARTID + call smp_pause + tail main # These codes need to be implemented on a specific SoC diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index f1c4c4d..88ad6d5 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -100,25 +100,7 @@ .global trap_entry .align 2 # four byte alignment, as required by mtvec trap_entry: - csrw mscratch, sp - - # SMP isn't supported yet, to avoid overwriting the same stack with different - # harts that handle traps at the same time. - # someday this gets fixed. - //csrr sp, mhartid - csrr sp, 0xf14 -.Lsmp_hang: - bnez sp, .Lsmp_hang - - # Use a different stack than in the main context, to to avoid overwriting - # stack data. - # TODO: Maybe use the old stack pointer (plus an offset) instead. But only if - # the previous mode was M, because it would be a very bad idea to use a stack - # pointer provided by unprivileged code! - la sp, _estack - addi sp, sp, -2048 # 2 KiB is half of the stack space - addi sp, sp, -MENTRY_FRAME_SIZE - + csrrw sp, mscratch, sp save_tf move a0,sp jal trap_handler -- To view, visit https://review.coreboot.org/c/coreboot/+/53944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8d3085bcd6f8883b08384f6bbf14052fd81fc2b Gerrit-Change-Number: 53944 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang W <wxjstz(a)126.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: adjust the size for RO/RW mcache
by Tim Wawrzynczak (Code Review) 08 May '21

08 May '21

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53908 ) Change subject: mb/google/volteer: adjust the size for RO/RW mcache ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > In that case, I would just set the size for those specific chipsets to 8K and the default for everyt […] b/187561710 -- To view, visit https://review.coreboot.org/c/coreboot/+/53908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9552bc9fa5d36b1ca662c9da030ae7b137b60a8 Gerrit-Change-Number: 53908 Gerrit-PatchSet: 3 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Sat, 08 May 2021 02:52:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: adjust the size for RO/RW mcache
by Tim Wawrzynczak (Code Review) 08 May '21

08 May '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53908 ) Change subject: mb/google/volteer: adjust the size for RO/RW mcache ...................................................................... mb/google/volteer: adjust the size for RO/RW mcache The mcache is overflowed in the latest build. In order to fix the mcache overflow, we increase the mcache size to 0x4000 and adjust the percentage to 50% for the ro/rw mcache. This change is for all of the volteer variants as we see many of the volteer variants which use the latest bios having the mcache overflow issue. BUG=b:187095474, b:187095765, b:187234881, b:162052593 TEST=no mcache overflow in the bios log Change-Id: If9552bc9fa5d36b1ca662c9da030ae7b137b60a8 Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53908 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/Kconfig 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index bdfb6da..291ffb8 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -159,4 +159,12 @@ bool default n +config CBFS_MCACHE_RW_PERCENTAGE + int + default 50 + +config CBFS_MCACHE_SIZE + hex + default 0x4000 + endif # BOARD_GOOGLE_BASEBOARD_VOLTEER -- To view, visit https://review.coreboot.org/c/coreboot/+/53908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9552bc9fa5d36b1ca662c9da030ae7b137b60a8 Gerrit-Change-Number: 53908 Gerrit-PatchSet: 3 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Enable PP5000_PEN
by Eric Peers (Code Review) 08 May '21

08 May '21

Eric Peers has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53943 ) Change subject: mb/google/guybrush: Enable PP5000_PEN ...................................................................... mb/google/guybrush: Enable PP5000_PEN Everybody wants a stylish stylus. Enable the power system to it. BUG=b:186267293 TEST=connect multimeter to PP5000_PEN and see it go from 0 to 1. MAGIC! Signed-off-by: Eric Peers <epeers(a)google.com> Change-Id: I11d05c118ec9451d26136c320f3650c489e02c59 --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/53943/1 diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index e386658..6b2013c 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -18,7 +18,7 @@ /* SOC_PEN_DETECT_ODL */ PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S0i3), /* EN_PP5000_PEN */ - PAD_GPO(GPIO_5, LOW), + PAD_GPO(GPIO_5, HIGH), /* EN_PP3300_WLAN */ PAD_GPO(GPIO_6, LOW), /* EN_PP3300_TCHPAD */ -- To view, visit https://review.coreboot.org/c/coreboot/+/53943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11d05c118ec9451d26136c320f3650c489e02c59 Gerrit-Change-Number: 53943 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Peers <epeers(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data
by Raul Rangel (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52913 to look at the new patch set (#8). Change subject: soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data ...................................................................... soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data The method now dynamically allocates the pirq structure and uses the get_pci_routing_table method. BUG=b:184766519 TEST=Build guybrush and verify picasso SSDT has not changed. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I297fc3ca7227fb4794ac70bd046ce2f93da8b869 --- M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h M src/soc/amd/common/block/pci/pci_routing_info.c M src/soc/amd/picasso/pcie_gpp.c 3 files changed, 35 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/52913/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/52913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I297fc3ca7227fb4794ac70bd046ce2f93da8b869 Gerrit-Change-Number: 52913 Gerrit-PatchSet: 8 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRT
by Raul Rangel (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52917 to look at the new patch set (#7). Change subject: soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRT ...................................................................... soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRT This is loosely based off of picasso/pcie_gpp.c. This version uses the acpigen_write_PRT_X methods to write the actual records. There are also two functions, 1 for using the GNB, and one for using the FCH. The FCH one is useful when the GNB IO-APIC has not been initialized. BUG=b:184766519 TEST=Dump guybrush ACPI and verify it looks correct Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76 --- M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h M src/soc/amd/common/block/pci/Makefile.inc A src/soc/amd/common/block/pci/acpi_prt.c 3 files changed, 217 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/52917/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/52917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76 Gerrit-Change-Number: 52917 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021