coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/amd/agesa/family14/northbridge.c: Report missing resources
by Angel Pons (Code Review) 07 May '21

07 May '21

Attention is currently required from: Nico Huber, Michał Żygowski, Kyösti Mälkki, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52935 ) Change subject: nb/amd/agesa/family14/northbridge.c: Report missing resources ...................................................................... Patch Set 2: (2 comments) File src/northbridge/amd/agesa/family14/northbridge.c: https://review.coreboot.org/c/coreboot/+/52935/comment/78ad6301_284730c5 PS2, Line 289: resource_t > why not resource_t? mmio_resource() is a wrapper macro for fixed_mem_resource(), which takes arguments of `unsigned long` type for basek and sizek. These functions don't use resource_t because they take values in KiB for some reason (space savings?) https://review.coreboot.org/c/coreboot/+/52935/comment/2f49b41f_5ee6968f PS2, Line 382: resource_t > Why? What is the policy behind using resource_t anyway? Same as above: mmio_resource() is a wrapper macro for fixed_mem_resource(), which takes arguments of `unsigned long` type for basek and sizek. -- To view, visit https://review.coreboot.org/c/coreboot/+/52935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b1b5f585ff6e0c7aecad250a75600e0c76331e1 Gerrit-Change-Number: 52935 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 07 May 2021 18:44:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common: Add Kconfig/Makefile support for common/fsp/*
by Felix Held (Code Review) 07 May '21

07 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52910 ) Change subject: soc/amd/common: Add Kconfig/Makefile support for common/fsp/* ...................................................................... soc/amd/common: Add Kconfig/Makefile support for common/fsp/* This will allow us to have subdirectories in common/fsp. BUG=b:184766519 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ib3497791e1963867c8fe06a42c111e5d0503ade1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52910 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/Kconfig.common M src/soc/amd/common/fsp/Makefile.inc 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/common/Kconfig.common b/src/soc/amd/common/Kconfig.common index fa1d14a..8050881 100644 --- a/src/soc/amd/common/Kconfig.common +++ b/src/soc/amd/common/Kconfig.common @@ -10,4 +10,10 @@ source "src/soc/amd/common/block/*/Kconfig" +if PLATFORM_USES_FSP2_0 + +source "src/soc/amd/common/fsp/*/Kconfig" + +endif # PLATFORM_USES_FSP2_0 + endif # SOC_AMD_COMMON diff --git a/src/soc/amd/common/fsp/Makefile.inc b/src/soc/amd/common/fsp/Makefile.inc index 3ba6ea5..ff25eba 100644 --- a/src/soc/amd/common/fsp/Makefile.inc +++ b/src/soc/amd/common/fsp/Makefile.inc @@ -2,4 +2,7 @@ romstage-y += fsp_reset.c ramstage-y += fsp_reset.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fsp-acpi.c + +subdirs-y += ./* + endif # CONFIG_PLATFORM_USES_FSP2_0 -- To view, visit https://review.coreboot.org/c/coreboot/+/52910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3497791e1963867c8fe06a42c111e5d0503ade1 Gerrit-Change-Number: 52910 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer: increase CBFS_MCACHE_SIZE
by Nick Vaccaro (Code Review) 07 May '21

07 May '21

Nick Vaccaro has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/53919 ) Change subject: mb/google/volteer: increase CBFS_MCACHE_SIZE ...................................................................... Abandoned Already covered by https://review.coreboot.org/c/coreboot/+/53908 -- To view, visit https://review.coreboot.org/c/coreboot/+/53919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04604395d41b878e7ef53aadcb27140c203a579e Gerrit-Change-Number: 53919 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/volteer: adjust the size for RO/RW mcache
by Nick Vaccaro (Code Review) 07 May '21

07 May '21

Attention is currently required from: Furquan Shaikh, Nick Vaccaro, Julius Werner, Zhuohao Lee. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53908 ) Change subject: mb/google/volteer: adjust the size for RO/RW mcache ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9552bc9fa5d36b1ca662c9da030ae7b137b60a8 Gerrit-Change-Number: 53908 Gerrit-PatchSet: 2 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 18:41:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: northbridge/amd/pi/00730F01: Create DRTM ACPI table
by Michał Żygowski (Code Review) 07 May '21

07 May '21

Attention is currently required from: Lance Zhao. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51581 ) Change subject: northbridge/amd/pi/00730F01: Create DRTM ACPI table ...................................................................... Patch Set 4: (1 comment) File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/c/coreboot/+/51581/comment/6d98d64b_ddfaefd9 PS4, Line 848: 16 > 8 Hmm. The tables here are 8-byte aligned, but in src/acpi/acpi.c the alignment is 16-byte for all tables. -- To view, visit https://review.coreboot.org/c/coreboot/+/51581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccb64578153d993075cae524cdef87e74cf9f34c Gerrit-Change-Number: 51581 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Comment-Date: Fri, 07 May 2021 18:36:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Migrate to struct pci_routing_info
by Raul Rangel (Code Review) 07 May '21

07 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53923 ) Change subject: soc/amd/picasso: Migrate to struct pci_routing_info ...................................................................... soc/amd/picasso: Migrate to struct pci_routing_info This allows us to use the common get_pci_routing_info and pci_calculate_irq. The IRQ field in the struct was also filled in from the PPR. BUG=b:184766519 TEST=Boot ezkinil and verify SSDT table is identical. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I16d90d8c89bfcf48878c0741154290ebc52a4120 --- M src/soc/amd/picasso/pcie_gpp.c 1 file changed, 21 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/53923/1 diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index 29dfe68..f609875 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -12,30 +12,24 @@ #include <soc/pci_devs.h> #include <stdio.h> -/** - * Each PCI bridge has its INTx lines routed to one of the 8 GNB IOAPIC PCI - * groups. Each group has 4 interrupts. The INTx lines can be swizzled before - * being routed to the IOAPIC. If the IOAPIC redirection entry is masked, the - * interrupt is reduced modulo 8 onto INT[A-H] and forwarded to the FCH IOAPIC. - **/ -struct pci_routing { - unsigned int devfn; - unsigned int group; - uint8_t pin[4]; +/* See AMD PPR 55570 - IOAPIC Initialization for the table that AGESA sets up */ +const struct pci_routing_info pci_routing_table[] = { + {PCIE_GPP_0_DEVFN, 0, PCI_SWIZZLE_ABCD, 0x10}, + {PCIE_GPP_1_DEVFN, 1, PCI_SWIZZLE_ABCD, 0x11}, + {PCIE_GPP_2_DEVFN, 2, PCI_SWIZZLE_ABCD, 0x12}, + {PCIE_GPP_3_DEVFN, 3, PCI_SWIZZLE_ABCD, 0x13}, + {PCIE_GPP_4_DEVFN, 4, PCI_SWIZZLE_ABCD, 0x10}, + {PCIE_GPP_5_DEVFN, 5, PCI_SWIZZLE_ABCD, 0x11}, + {PCIE_GPP_6_DEVFN, 6, PCI_SWIZZLE_ABCD, 0x12}, + {PCIE_GPP_A_DEVFN, 7, PCI_SWIZZLE_ABCD, 0x13}, + {PCIE_GPP_B_DEVFN, 7, PCI_SWIZZLE_CDAB, 0x0C}, }; -/* See AMD PPR 55570 - IOAPIC Initialization for the table that AGESA sets up */ -static const struct pci_routing pci_routing_table[] = { - {PCIE_GPP_0_DEVFN, 0, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, - {PCIE_GPP_1_DEVFN, 1, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, - {PCIE_GPP_2_DEVFN, 2, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, - {PCIE_GPP_3_DEVFN, 3, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, - {PCIE_GPP_4_DEVFN, 4, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, - {PCIE_GPP_5_DEVFN, 5, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, - {PCIE_GPP_6_DEVFN, 6, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, - {PCIE_GPP_A_DEVFN, 7, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, - {PCIE_GPP_B_DEVFN, 7, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B} }, -}; +const struct pci_routing_info *get_pci_routing_table(size_t *entries) +{ + *entries = ARRAY_SIZE(pci_routing_table); + return pci_routing_table; +} /* * This data structure is populated from the raw data above. It is used @@ -44,28 +38,9 @@ */ static struct pirq_struct pirq_data[ARRAY_SIZE(pci_routing_table)]; -static const struct pci_routing *get_pci_routing(unsigned int devfn) -{ - for (size_t i = 0; i < ARRAY_SIZE(pci_routing_table); ++i) { - if (devfn == pci_routing_table[i].devfn) - return &pci_routing_table[i]; - } - - return NULL; -} - -static unsigned int calculate_irq(const struct pci_routing *pci_routing, unsigned int i) -{ - unsigned int irq_index; - irq_index = pci_routing->group * 4; - irq_index += pci_routing->pin[i]; - - return irq_index; -} - void populate_pirq_data(void) { - const struct pci_routing *pci_routing; + const struct pci_routing_info *pci_routing; struct pirq_struct *pirq; unsigned int irq_index; @@ -75,7 +50,7 @@ pirq->devfn = pci_routing->devfn; for (size_t j = 0; j < 4; ++j) { - irq_index = calculate_irq(pci_routing, j); + irq_index = pci_calculate_irq(pci_routing, j); pirq->PIN[j] = irq_index % 8; } @@ -119,7 +94,7 @@ char link_template[] = "\\_SB.INTX"; unsigned int irq_index; - const struct pci_routing *pci_routing = get_pci_routing(dev->path.pci.devfn); + const struct pci_routing_info *pci_routing = get_pci_routing_info(dev->path.pci.devfn); if (!pci_routing) { printk(BIOS_ERR, "PCI routing table not found for %s\n", dev_path(dev)); return; @@ -136,7 +111,7 @@ acpigen_write_package(4); /* Package - APIC Routing */ for (unsigned int i = 0; i < 4; ++i) { - irq_index = calculate_irq(pci_routing, i); + irq_index = pci_calculate_irq(pci_routing, i); acpigen_write_package(4); /* There is only one device attached to the bridge */ @@ -157,7 +132,7 @@ acpigen_write_package(4); /* Package - PIC Routing */ for (unsigned int i = 0; i < 4; ++i) { - irq_index = calculate_irq(pci_routing, i); + irq_index = pci_calculate_irq(pci_routing, i); link_template[8] = 'A' + (irq_index % 8); -- To view, visit https://review.coreboot.org/c/coreboot/+/53923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16d90d8c89bfcf48878c0741154290ebc52a4120 Gerrit-Change-Number: 53923 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/pci: Introduce struct pci_routing_info
by Raul Rangel (Code Review) 07 May '21

07 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53922 ) Change subject: soc/amd/common/block/pci: Introduce struct pci_routing_info ...................................................................... soc/amd/common/block/pci: Introduce struct pci_routing_info This struct is similar to `struct pci_routing` defined in picasso/pcie_gpp.c. It additionally contains the irq used for the bridge and is structured in a way that the FSP can provide via HOB. The next set of CLs will migrate the pci routing functions used by picasso into common and enable pci routing table generation for cezanne. BUG=b:184766519 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1a8d988d125f407f0aa7bc1722d432446aa9aff8 --- M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h M src/soc/amd/common/block/pci/Makefile.inc A src/soc/amd/common/block/pci/pci_routing_info.c 3 files changed, 85 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/53922/1 diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h index 081741a..bc8eefb 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h @@ -31,7 +31,34 @@ void write_pci_int_table(void); const struct irq_idx_name *sb_get_apic_reg_association(size_t *size); +enum pci_routing_swizzle { + PCI_SWIZZLE_ABCD, + PCI_SWIZZLE_BCDA, + PCI_SWIZZLE_CDAB, + PCI_SWIZZLE_DABC, +}; + +/** + * Each PCI bridge has its INTx lines routed to one of the GNB IO-APIC PCI + * groups. Each group has 4 interrupts. The INTx lines can be swizzled before + * being routed to the IO-APIC. If the IO-APIC redirection entry is masked, the + * interrupt is reduced modulo 8 onto INT[A-H] and forwarded to the FCH IO-APIC. + **/ +struct pci_routing_info { + uint8_t devfn; + uint8_t group; + uint8_t swizzle; + uint8_t irq; +}; + /* Implemented by the SoC */ void populate_pirq_data(void); +/* Implemented by the SoC */ +const struct pci_routing_info *get_pci_routing_table(size_t *entries); + +const struct pci_routing_info *get_pci_routing_info(unsigned int devfn); + +unsigned int pci_calculate_irq(const struct pci_routing_info *routing_info, unsigned int pin); + #endif /* AMD_BLOCK_PCI_UTIL_H */ diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index 78453d4..5df641b 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -1,4 +1,5 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += amd_pci_util.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += pci_routing_info.c ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF),y) diff --git a/src/soc/amd/common/block/pci/pci_routing_info.c b/src/soc/amd/common/block/pci/pci_routing_info.c new file mode 100644 index 0000000..e0a6964 --- /dev/null +++ b/src/soc/amd/common/block/pci/pci_routing_info.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/amd_pci_util.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <types.h> + +enum pcie_swizzle_pin { + PIN_A, + PIN_B, + PIN_C, + PIN_D, +}; + +static const uint8_t pcie_swizzle_table[][4] = { + {PIN_A, PIN_B, PIN_C, PIN_D}, + {PIN_B, PIN_C, PIN_D, PIN_A}, + {PIN_C, PIN_D, PIN_A, PIN_B}, + {PIN_D, PIN_A, PIN_B, PIN_C}, +}; + +const struct pci_routing_info *get_pci_routing_info(unsigned int devfn) +{ + const struct pci_routing_info *routing_info; + size_t entries = 0; + + routing_info = get_pci_routing_table(&entries); + + if (!routing_info || !entries) + return NULL; + + for (size_t i = 0; i < entries; ++i, ++routing_info) + if (routing_info->devfn == devfn) + return routing_info; + + printk(BIOS_ERR, "Failed to find PCIe routing info for dev: %#x, fn: %#x\n", + PCI_SLOT(devfn), PCI_FUNC(devfn)); + + return NULL; +} + +unsigned int pci_calculate_irq(const struct pci_routing_info *routing_info, + unsigned int pin) +{ + unsigned int irq; + + if (routing_info->swizzle >= ARRAY_SIZE(pcie_swizzle_table)) + die("%s: swizzle %u out of bounds\n", __func__, routing_info->swizzle); + + if (pin >= ARRAY_SIZE(pcie_swizzle_table[routing_info->swizzle])) + die("%s: pin %u out of bounds\n", __func__, pin); + + irq = routing_info->group * 4; + irq += pcie_swizzle_table[routing_info->swizzle][pin]; + + return irq; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/53922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a8d988d125f407f0aa7bc1722d432446aa9aff8 Gerrit-Change-Number: 53922 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data
by Raul Rangel (Code Review) 07 May '21

07 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52913 to look at the new patch set (#4). Change subject: soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data ...................................................................... soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data The method now dynamically allocates the pirq structure and uses the get_pci_routing_table method. BUG=b:184766519 TEST=Build guybrush and verify picasso SSDT has not changed. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I297fc3ca7227fb4794ac70bd046ce2f93da8b869 --- M src/soc/amd/common/block/pci/pci_routing_info.c M src/soc/amd/picasso/pcie_gpp.c 2 files changed, 35 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/52913/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I297fc3ca7227fb4794ac70bd046ce2f93da8b869 Gerrit-Change-Number: 52913 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer: increase CBFS_MCACHE_SIZE
by Tim Wawrzynczak (Code Review) 07 May '21

07 May '21

Attention is currently required from: Furquan Shaikh, Nick Vaccaro, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53919 ) Change subject: mb/google/volteer: increase CBFS_MCACHE_SIZE ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: see CB:53908 -- To view, visit https://review.coreboot.org/c/coreboot/+/53919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04604395d41b878e7ef53aadcb27140c203a579e Gerrit-Change-Number: 53919 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Fri, 07 May 2021 18:29:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/amd/pi/00730F01/northbridge.c: Report missing resources
by Michał Żygowski (Code Review) 07 May '21

07 May '21

Attention is currently required from: Nico Huber, Kyösti Mälkki, Felix Held. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52927 ) Change subject: nb/amd/pi/00730F01/northbridge.c: Report missing resources ...................................................................... Patch Set 3: (1 comment) File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/c/coreboot/+/52927/comment/6c0d5ed5_bc5c7b6a PS3, Line 256: * 0xc0000 - 0xcffff: VGA OPROM > is it intended that the d segment isn't listed here? Rather not. It should be included in the SeaBIOS range, as D segment is mainly used by oproms -- To view, visit https://review.coreboot.org/c/coreboot/+/52927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia57ab026218f4aae0a98c2081412c4a9ebb7f57a Gerrit-Change-Number: 52927 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 07 May 2021 18:28:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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coreboot-gerrit May 2021