coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: src/intel: Add LOCKDIS to mark SPI as writable in SKL
by Patrick Rudolph (Code Review) 07 May '21

07 May '21

Attention is currently required from: Star Labs. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52796 ) Change subject: src/intel: Add LOCKDIS to mark SPI as writable in SKL ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > To clarify, it's just the BIOS Control register - the SPI is indeed writable. […] that's indeed strange, but all platforms use the same code to lock the BC register. I guess there's simply no code that sets sane defaults in BC register prior to locking it. -- To view, visit https://review.coreboot.org/c/coreboot/+/52796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I712972428dd22373d8655ce72d36c0957ee9a900 Gerrit-Change-Number: 52796 Gerrit-PatchSet: 4 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Star Labs <admin(a)starlabs.systems> Gerrit-Comment-Date: Fri, 07 May 2021 16:41:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Star Labs <admin(a)starlabs.systems> Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: adjust the size for RO/RW mcache
by Tim Wawrzynczak (Code Review) 07 May '21

07 May '21

Attention is currently required from: Furquan Shaikh, Nick Vaccaro, Julius Werner, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53908 ) Change subject: mb/google/volteer: adjust the size for RO/RW mcache ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: Seems fine to me. Considering the minidiag changes, we may want to revisit the default value for MCACHE_RW_PERCENTAGE for CHROMEOS (maybe just remove it now and leave the default of 50?), but I think the MCACHE_SIZE probably should be adjusted on a per-program basis like this. -- To view, visit https://review.coreboot.org/c/coreboot/+/53908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9552bc9fa5d36b1ca662c9da030ae7b137b60a8 Gerrit-Change-Number: 53908 Gerrit-PatchSet: 2 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 16:29:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/sn65dsi86: Switch EDID reading to use "indirect mode"
by Douglas Anderson (Code Review) 07 May '21

07 May '21

Attention is currently required from: Vinod Polimera, Julius Werner. Douglas Anderson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52959 ) Change subject: drivers/sn65dsi86: Switch EDID reading to use "indirect mode" ...................................................................... Patch Set 4: Code-Review-1 (4 comments) Patchset: PS4: I think there are still problems. Please yell if you think I got any of my analysis wrong. File src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c: https://review.coreboot.org/c/coreboot/+/52959/comment/ab176843_cc7e282b PS4, Line 189: [I2C_RAW_WRITE] = I2C_OVER_AUX_WRITE_MOT_1, : [I2C_RAW_READ] = I2C_OVER_AUX_READ_MOT_1, I haven't fully analyzed the side effects, but I _think_ that always using MOT=1 here isn't quite right. MOT=Middle-of-Transaction and I believe it says not to send the "stop" bit. I think you're essentially always leaving the panel hanging at the end of your i2c transac... For the kernel this is all abstracted out by the generic I2C-over-aux framework which presumably handles it. For the "Example of Indirect I2C Read of the EDID." in the TI datasheet, they seem to handle it by adding an extra zero-byte command (with MOT=0) at the end. For read that's: ``` 18. Program the AUX_CMD = 0x1, AUX_ADDR[7:0] = 0x50, and AUX_LENGTH = 0x00. ``` For write, that's: ``` 9. Program the AUX_CMD = 0x0, AUX_ADDR[7:0] = 0x30, and AUX_LENGTH = 0x00. ``` Maybe you're handling this in some other way and I just missed it. https://review.coreboot.org/c/coreboot/+/52959/comment/1cb68a7f_f8491612 PS4, Line 200: i2c_writeb(bus, chip, SN_AUX_CMD_REG, (cmd[request] << 4)) I don't know if it maters, but kernel driver and datasheet show doing this _first_, before the setting of the address and length. Maybe move it first just to be consistent? https://review.coreboot.org/c/coreboot/+/52959/comment/998550d4_d8f0f050 PS4, Line 220: In the kernel driver, we check a whole bunch of extra status things here (timeout, short, and failed). I don't think we've ever actually seen them in practice but I think they're important. Specifically your code is assuming that the 100 ms timeout above will handle everything but I don't think it will. Specifically see this bit: > Once the requested Read or Write completes, the SN65DSI86 will clear the SEND bit and if an error occurred, the SN65DSI86 will set the NAT_I2C_FAILED flag. The NAT_I2C_FAILED flag will get set if for some reason the slave NACK the I2C Address. If the Slave NACK without completing the entire request AUX_LENGTH, the SN65DSI86 will set the AUX_SHORT flag and update the AUX_LENGTH register with the amount of data completed and then clear the SEND bit So the SEND bit could be cleared but then we might have a problem. Presumably for most of this you just want to treat it as an error. The bridge chip does a whole lot of retries on its own for you so pretty much anything it reports back to you means we've already tried a bunch and failed. In theory you could _try_ to handle the SHORT case but I think treating it as an error is likely fine too. Since I don't think we've ever seen this in practice, the current kernel code is just our best guess about how to handle it (the kernel driver leverages the generic kernel framework for most of this). -- To view, visit https://review.coreboot.org/c/coreboot/+/52959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65f80193380d3c3841f9f5c26897ed672f45e15a Gerrit-Change-Number: 52959 Gerrit-PatchSet: 4 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 16:25:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/gigabyte/ga-d510ud: Fix HDA codec configuration
by Angel Pons (Code Review) 07 May '21

07 May '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53914 ) Change subject: mb/gigabyte/ga-d510ud: Fix HDA codec configuration ...................................................................... mb/gigabyte/ga-d510ud: Fix HDA codec configuration The values were copied from Foxconn D41S, which uses a different codec. Adjust the codec config as per the settings dumped from vendor firmware. Change-Id: If6a4c41b5d424adb23ebef402d2d2ad21269fe25 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/gigabyte/ga-d510ud/hda_verb.c 1 file changed, 18 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/53914/1 diff --git a/src/mainboard/gigabyte/ga-d510ud/hda_verb.c b/src/mainboard/gigabyte/ga-d510ud/hda_verb.c index f36d48c..a19839f 100644 --- a/src/mainboard/gigabyte/ga-d510ud/hda_verb.c +++ b/src/mainboard/gigabyte/ga-d510ud/hda_verb.c @@ -3,22 +3,24 @@ #include <device/azalia_device.h> const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0662, - 0x105b0d55, /* Subsystem ID */ - 10, /* Number of entries */ - - /* Pin Widget Verb Table */ - AZALIA_PIN_CFG(0, 0x14, 0x01014c10), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x01a19c30), - AZALIA_PIN_CFG(0, 0x19, 0x02a19c31), - AZALIA_PIN_CFG(0, 0x1a, 0x0181343f), - AZALIA_PIN_CFG(0, 0x1b, 0x02214c1f), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x4005c603), - AZALIA_PIN_CFG(0, 0x1e, 0x99430120), + 0x10ec0887, /* Realtek ALC887 */ + 0x1458a002, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x1458a002), + AZALIA_PIN_CFG(2, 0x11, 0x411111f0), + AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x14, 0x01014410), + AZALIA_PIN_CFG(2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(2, 0x18, 0x01a19c30), + AZALIA_PIN_CFG(2, 0x19, 0x02a19c50), + AZALIA_PIN_CFG(2, 0x1a, 0x0181344f), + AZALIA_PIN_CFG(2, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(2, 0x1c, 0x593301f0), + AZALIA_PIN_CFG(2, 0x1d, 0x4005c603), + AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1f, 0x411111f0), }; const u32 pc_beep_verbs[] = {}; -- To view, visit https://review.coreboot.org/c/coreboot/+/53914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6a4c41b5d424adb23ebef402d2d2ad21269fe25 Gerrit-Change-Number: 53914 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/intel/cbnt: Allow to use an externally provided bg-prov bin
by Angel Pons (Code Review) 07 May '21

07 May '21

Attention is currently required from: Martin Roth, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51982 ) Change subject: security/intel/cbnt: Allow to use an externally provided bg-prov bin ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06ff4ee01bf58cae45648ddb8a30a30b9a7e027a Gerrit-Change-Number: 51982 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 07 May 2021 16:01:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/amd/agesa/family14/northbridge.c: Report missing resources
by Angel Pons (Code Review) 07 May '21

07 May '21

Attention is currently required from: Nico Huber, Michał Żygowski, Kyösti Mälkki. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52935 ) Change subject: nb/amd/agesa/family14/northbridge.c: Report missing resources ...................................................................... Patch Set 2: (6 comments) Patchset: PS2: a File src/northbridge/amd/agesa/family14/northbridge.c: https://review.coreboot.org/c/coreboot/+/52935/comment/c9ff2939_44031a4d PS2, Line 285: Ff typo? If https://review.coreboot.org/c/coreboot/+/52935/comment/73c2d05f_5b5c62f9 PS2, Line 288: __f4_dev These fX dev pointers are signs that the code could use more PCI drivers https://review.coreboot.org/c/coreboot/+/52935/comment/a90f937d_98b25f3c PS2, Line 289: resource_t unsigned long https://review.coreboot.org/c/coreboot/+/52935/comment/b415d636_ee341232 PS2, Line 382: resource_t unsigned long https://review.coreboot.org/c/coreboot/+/52935/comment/2c377c29_89b06a4f PS2, Line 382: // 4 1T What does this comment mean? -- To view, visit https://review.coreboot.org/c/coreboot/+/52935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b1b5f585ff6e0c7aecad250a75600e0c76331e1 Gerrit-Change-Number: 52935 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 07 May 2021 15:59:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/cbnt/Makefile.inc: Use variables for hash alg
by Angel Pons (Code Review) 07 May '21

07 May '21

Attention is currently required from: Martin Roth, Christian Walter, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51975 ) Change subject: security/intel/cbnt/Makefile.inc: Use variables for hash alg ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4113b1496e99c10017fc1d85a4acbbc16d32ea41 Gerrit-Change-Number: 51975 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 07 May 2021 15:56:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE
by Angel Pons (Code Review) 07 May '21

07 May '21

Attention is currently required from: Arthur Heymans, Alexander Couzens, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52942 ) Change subject: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE ...................................................................... Patch Set 1: (1 comment) File src/cpu/intel/socket_p/Kconfig: https://review.coreboot.org/c/coreboot/+/52942/comment/5b3557f0_96c74cee PS1, Line 16: default 0x10000 > > CPU_INTEL_SOCKET_BGA956 and CPU_INTEL_SOCKET_M use 0x8000 here, and are never used with NO_CBFS_MCACHE. I'd simply drop `select NO_CBFS_MCACHE` from t400. > > config.lenovo_t400_vboot_and_debug fails to build then :-/ Why is this not mentioned in the commit message? I would expect that the same settings would not build on X200 either. And IIRC you have an X200, so you could test if doubling DCACHE_RAM_SIZE works on it. > I'm pretty sure cache won't be an issue but I can also strip down that config. Any thoughts? Obviously t400 should not miss out on cbfs_mcache because of a probably not booting debug buildtest. I agree that it should be safe to increase this, but I'm somewhat worried because the coreboot 4.14 release is scheduled for the 10th (in three days). The lowest bound for L2 cache size on Socket P is 512 KiB: https://www.cpu-world.com/CPUs/Celeron_Dual-Core/Intel-Mobile%20Celeron%20D… -- To view, visit https://review.coreboot.org/c/coreboot/+/52942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772 Gerrit-Change-Number: 52942 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 07 May 2021 15:56:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/amd/agesa/family14/northbridge.c: Use generic allocation functions
by Felix Held (Code Review) 07 May '21

07 May '21

Attention is currently required from: Nico Huber, Michał Żygowski, Kyösti Mälkki. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52934 ) Change subject: nb/amd/agesa/family14/northbridge.c: Use generic allocation functions ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74a0ed1fcbbc9e066c42c4d51d30ab1d7138134a Gerrit-Change-Number: 52934 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 07 May 2021 15:43:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/amd/agesa/family14/northbridge.c: Report missing resources
by Felix Held (Code Review) 07 May '21

07 May '21

Attention is currently required from: Nico Huber, Michał Żygowski, Angel Pons, Kyösti Mälkki. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52935 ) Change subject: nb/amd/agesa/family14/northbridge.c: Report missing resources ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/northbridge/amd/agesa/family14/northbridge.c: https://review.coreboot.org/c/coreboot/+/52935/comment/41de2129_c83cb365 PS2, Line 275: * 0xc0000 - 0xcffff: VGA OPROM same comment about the d segment here -- To view, visit https://review.coreboot.org/c/coreboot/+/52935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b1b5f585ff6e0c7aecad250a75600e0c76331e1 Gerrit-Change-Number: 52935 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 07 May 2021 15:43:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2021