coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

1 participants
6048 discussions

Change in coreboot[master]: sc7280: aop loading changes
by build bot (Jenkins) (Code Review) 07 May '21

07 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Martin Roth, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49767 ) Change subject: sc7280: aop loading changes ...................................................................... Patch Set 33: (26 comments) File src/soc/qualcomm/sc7280/aop_load_reset.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/05076cb7_5a0690d9 PS33, Line 11: bool aop_fw_entry; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/94d84cbc_d0b8632a PS33, Line 11: bool aop_fw_entry; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/8e080467_fc86dace PS33, Line 13: struct prog aop_fw_prog = code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/bf42544c_cfeb804a PS33, Line 13: struct prog aop_fw_prog = please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/eb95fc9e_bc2e6d79 PS33, Line 14: PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/aop"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/eefc9aae_a34858cd PS33, Line 14: PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/aop"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/5b74ddfc_b8cea067 PS33, Line 16: if (prog_locate(&aop_fw_prog)) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/f46bef29_9568d376 PS33, Line 16: if (prog_locate(&aop_fw_prog)) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/2d5c08f5_7939206a PS33, Line 17: die("SOC image: AOP_FW not found"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/984cee08_fa47b669 PS33, Line 17: die("SOC image: AOP_FW not found"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/0e19eebc_3c62ecd3 PS33, Line 19: aop_fw_entry = selfload(&aop_fw_prog); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/d3c8ff98_22c74e8d PS33, Line 19: aop_fw_entry = selfload(&aop_fw_prog); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/4e2905a6_cdbea112 PS33, Line 20: if (!aop_fw_entry) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/e219fd55_aea85e73 PS33, Line 20: if (!aop_fw_entry) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/2625271c_ad7c1dd1 PS33, Line 21: die("SOC image: AOP load failed"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/3243da1c_98901804 PS33, Line 21: die("SOC image: AOP load failed"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/a3b247e2_e93fd75d PS33, Line 23: clock_reset_aop(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/d964b1ca_4cd42dc1 PS33, Line 23: clock_reset_aop(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/f2d931d4_a6059cb5 PS33, Line 25: printk(BIOS_DEBUG, "\nSOC:AOP brought out of reset.\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/e8a3fe4e_96d6cb73 PS33, Line 25: printk(BIOS_DEBUG, "\nSOC:AOP brought out of reset.\n"); please, no spaces at the start of a line File src/soc/qualcomm/sc7280/mmu.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/0f216f78_58e18732 PS33, Line 25: mmu_config_range((void *)_aop_code_ram, REGION_SIZE(aop_code_ram), CACHED_RAM); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/0f5a4452_037010a0 PS33, Line 25: mmu_config_range((void *)_aop_code_ram, REGION_SIZE(aop_code_ram), CACHED_RAM); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/47c2b8d0_d9c6fc6e PS33, Line 26: mmu_config_range((void *)_aop_data_ram, REGION_SIZE(aop_data_ram), CACHED_RAM); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/9202e54c_0b2bc661 PS33, Line 26: mmu_config_range((void *)_aop_data_ram, REGION_SIZE(aop_data_ram), CACHED_RAM); please, no spaces at the start of a line File src/soc/qualcomm/sc7280/soc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/9f144f52_1364bf1a PS33, Line 15: REGION_SIZE(dram_aop) / KiB); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118670): https://review.coreboot.org/c/coreboot/+/49767/comment/ff49964c_58d161dd PS33, Line 15: REGION_SIZE(dram_aop) / KiB); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/49767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90b0f48e15df390970e027bff2065b7a89b14cec Gerrit-Change-Number: 49767 Gerrit-PatchSet: 33 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 07:27:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sc7280: shrm.elf loading changes
by build bot (Jenkins) (Code Review) 07 May '21

07 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Martin Roth, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49392 ) Change subject: sc7280: shrm.elf loading changes ...................................................................... Patch Set 34: (1 comment) File src/soc/qualcomm/sc7280/shrm_load_reset.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118669): https://review.coreboot.org/c/coreboot/+/49392/comment/eb66becc_7617e773 PS34, Line 9: void shrm_fw_load_reset() Bad function definition - void shrm_fw_load_reset() should probably be void shrm_fw_load_reset(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/49392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Gerrit-Change-Number: 49392 Gerrit-PatchSet: 34 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 07:26:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: psp_verstage: remove not-implemented files for cezanne
by Kangheui Won (Code Review) 07 May '21

07 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53905 ) Change subject: psp_verstage: remove not-implemented files for cezanne ...................................................................... psp_verstage: remove not-implemented files for cezanne Cezanne PSP is missing implementations for some svc apis. Do not include files related to missing svc apis. Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Ibaab4e8435624d403ef18e980146ebfd1598b61b --- M src/soc/amd/common/psp_verstage/Makefile.inc 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/53905/1 diff --git a/src/soc/amd/common/psp_verstage/Makefile.inc b/src/soc/amd/common/psp_verstage/Makefile.inc index a913a5b..487698e 100644 --- a/src/soc/amd/common/psp_verstage/Makefile.inc +++ b/src/soc/amd/common/psp_verstage/Makefile.inc @@ -14,9 +14,12 @@ verstage-y += printk.c verstage-y += psp_verstage.c verstage-y += psp.c +ifneq ($(CONFIG_SOC_AMD_CEZANNE),y) +# cezanne PSP does not support these functions yet verstage-y += reset.c verstage-y += timer.c verstage-y += vboot_crypto.c +endif $(obj)/psp_verstage.bin: $(objcbfs)/verstage.elf $(OBJCOPY_verstage) -O binary $^ $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/53905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaab4e8435624d403ef18e980146ebfd1598b61b Gerrit-Change-Number: 53905 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: cezanne/psp_verstage: update SRAM address
by Kangheui Won (Code Review) 07 May '21

07 May '21

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53904 ) Change subject: cezanne/psp_verstage: update SRAM address ...................................................................... cezanne/psp_verstage: update SRAM address Loading address and size for the user app has been changed with recent PSP release. Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: If247cdf3413c6a10f4b3c92fb7e43dd1057865d9 --- M src/soc/amd/cezanne/include/soc/psp_verstage_addr.h 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/53904/1 diff --git a/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h b/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h index bdc46cb..569d6e1 100644 --- a/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h +++ b/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h @@ -8,8 +8,8 @@ * header for the user app (verstage) must be mapped. * Size is 0x14000 bytes */ -#define PSP_SRAM_START 0x36000 -#define PSP_SRAM_SIZE (80K) +#define PSP_SRAM_START 0x26000 +#define PSP_SRAM_SIZE (148K) #define VERSTAGE_START PSP_SRAM_START /* @@ -17,7 +17,7 @@ * and make the size a multiple of 4k */ -#define PSP_VERSTAGE_STACK_START 0x49000 -#define PSP_VERSTAGE_STACK_SIZE (4K) +#define PSP_VERSTAGE_STACK_START 0x41000 +#define PSP_VERSTAGE_STACK_SIZE (40K) #endif /* AMD_CEZANNE_PSP_VERSTAGE_ADDR_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/53904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If247cdf3413c6a10f4b3c92fb7e43dd1057865d9 Gerrit-Change-Number: 53904 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: sc7280: Reserve wlan & wpss dram memory regions
by build bot (Jenkins) (Code Review) 07 May '21

07 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50587 ) Change subject: sc7280: Reserve wlan & wpss dram memory regions ...................................................................... Patch Set 31: (4 comments) File src/soc/qualcomm/sc7280/soc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118657): https://review.coreboot.org/c/coreboot/+/50587/comment/3c0de8c6_39c2fee0 PS31, Line 16: REGION_SIZE(dram_wlan) / KiB); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118657): https://review.coreboot.org/c/coreboot/+/50587/comment/554fc6b6_2ffe6fa6 PS31, Line 16: REGION_SIZE(dram_wlan) / KiB); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118657): https://review.coreboot.org/c/coreboot/+/50587/comment/6cf1f1c5_32354401 PS31, Line 18: REGION_SIZE(dram_wpss) / KiB); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118657): https://review.coreboot.org/c/coreboot/+/50587/comment/66a443ab_9a15adf6 PS31, Line 18: REGION_SIZE(dram_wpss) / KiB); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/50587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic98b5d08a0a7b3f772582bf85d94f901a7c53010 Gerrit-Change-Number: 50587 Gerrit-PatchSet: 31 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 07:15:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: libpayload: Add MMIO support in PCI lib
by Ravi kumar (Code Review) 07 May '21

07 May '21

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53903 ) Change subject: libpayload: Add MMIO support in PCI lib ...................................................................... libpayload: Add MMIO support in PCI lib Added MMIO Support in libpayload pci driver to allow ep config space access using payload PCI functions. endpoint config space addres passed from coreboot to payload through coreboot tables if MMIO supports. Change-Id: I7cfb95e31b7ee984ee0c2e7586e6caeecd7deadd Signed-off-by: Prasad Malisetty <pmaliset(a)codeaurora.org> --- M payloads/libpayload/Kconfig M payloads/libpayload/configs/config.herobrine M payloads/libpayload/drivers/pci.c M payloads/libpayload/include/arm64/arch/io.h M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/coreboot_tables.h M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c M src/soc/qualcomm/sc7280/Kconfig 11 files changed, 120 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/53903/1 diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 7a502b5..8f67d2f 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -391,9 +391,13 @@ config PCI bool "Support for PCI devices" - depends on ARCH_X86 # for now default y +config MMCONF_SUPPORT + bool "Support MMIO method" + depends on PCI + default y + config NVRAM bool "Support for reading/writing NVRAM bytes" depends on ARCH_X86 # for now diff --git a/payloads/libpayload/configs/config.herobrine b/payloads/libpayload/configs/config.herobrine index 6309d2b..c47afba 100644 --- a/payloads/libpayload/configs/config.herobrine +++ b/payloads/libpayload/configs/config.herobrine @@ -6,3 +6,6 @@ CONFIG_LP_USB_XHCI=y CONFIG_LP_SERIAL_CONSOLE=y CONFIG_LP_QUALCOMM_QUPV3_SERIAL_CONSOLE=y +CONFIG_LP_MMCONF_SUPPORT=y +CONFIG_LP_PCI=y +CONFIG_LP_PCIE_NVME=y diff --git a/payloads/libpayload/drivers/pci.c b/payloads/libpayload/drivers/pci.c index 90e9220..326e0ed 100644 --- a/payloads/libpayload/drivers/pci.c +++ b/payloads/libpayload/drivers/pci.c @@ -32,38 +32,65 @@ u8 pci_read_config8(pcidev_t device, u16 reg) { +#if CONFIG(LP_MMCONF_SUPPORT) + void *cfg_addr = lib_sysinfo.pci_ep_cfg_base + reg; + return read8(cfg_addr); +#endif outl(device | (reg & ~3), 0xCF8); return inb(0xCFC + (reg & 3)); } u16 pci_read_config16(pcidev_t device, u16 reg) { +#if CONFIG(LP_MMCONF_SUPPORT) + void *cfg_addr = lib_sysinfo.pci_ep_cfg_base + (reg & ~1); + return read16(cfg_addr); +#endif outl(device | (reg & ~3), 0xCF8); return inw(0xCFC + (reg & 3)); } u32 pci_read_config32(pcidev_t device, u16 reg) { +#if CONFIG(LP_MMCONF_SUPPORT) + void *cfg_addr = lib_sysinfo.pci_ep_cfg_base + (reg & ~3); + return read32(cfg_addr); +#endif outl(device | (reg & ~3), 0xCF8); return inl(0xCFC + (reg & 3)); } void pci_write_config8(pcidev_t device, u16 reg, u8 val) { +#if CONFIG(LP_MMCONF_SUPPORT) + void *cfg_addr = lib_sysinfo.pci_ep_cfg_base + (reg); + write8(cfg_addr, val); +#endif outl(device | (reg & ~3), 0xCF8); outb(val, 0xCFC + (reg & 3)); + return; } void pci_write_config16(pcidev_t device, u16 reg, u16 val) { +#if CONFIG(LP_MMCONF_SUPPORT) + void *cfg_addr = lib_sysinfo.pci_ep_cfg_base + (reg & ~1); + write16(cfg_addr, val); +#endif outl(device | (reg & ~3), 0xCF8); outw(val, 0xCFC + (reg & 3)); + return; } void pci_write_config32(pcidev_t device, u16 reg, u32 val) { +#if CONFIG(LP_MMCONF_SUPPORT) + void *cfg_addr = lib_sysinfo.pci_ep_cfg_base + (reg & ~3); + write32(cfg_addr, val); +#endif outl(device | (reg & ~3), 0xCF8); outl(val, 0xCFC + (reg & 3)); + return; } static int find_on_bus(int bus, unsigned short vid, unsigned short did, diff --git a/payloads/libpayload/include/arm64/arch/io.h b/payloads/libpayload/include/arm64/arch/io.h index 9d67716..ae0bba1 100644 --- a/payloads/libpayload/include/arm64/arch/io.h +++ b/payloads/libpayload/include/arm64/arch/io.h @@ -133,4 +133,34 @@ dmb(); } +static inline unsigned int inl(int port) +{ + return 0; +} + +static inline unsigned short inw(int port) +{ + return 0; +} + +static inline unsigned char inb(int port) +{ + return 0; +} + +static inline void outl(unsigned int val, int port) +{ + return; +} + +static inline void outw(unsigned short val, int port) +{ + return; +} + +static inline void outb(unsigned char val, int port) +{ + return; + +} #endif diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index e042a90..4e67a2c 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -86,6 +86,7 @@ CB_TAG_OPTION_ENUM = 0x00ca, CB_TAG_OPTION_DEFAULTS = 0x00cb, CB_TAG_OPTION_CHECKSUM = 0x00cc, + CB_TAG_PCI_EP_CONFIG = 0x00cd, }; struct cbuint64 { @@ -238,6 +239,13 @@ struct cb_gpio gpios[0]; }; +/* PCI EP config window info */ +struct cb_pci_config_info { + uint32_t tag; + uint32_t size; + void *config_base; +}; + struct lb_range { uint32_t tag; uint32_t size; diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 5a24e14..b7e58fb 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -146,6 +146,7 @@ #if CONFIG(LP_PCI) struct pci_access pacc; + void *pci_ep_cfg_base; #endif }; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 7e23afe..d6f97f8 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -115,6 +115,13 @@ info->gpios[i] = gpios->gpios[i]; } +static void cb_parse_pci_ep_config_base(void *ptr, struct sysinfo_t *info) +{ + struct cb_pci_config_info *pci = (struct cb_pci_config_info *)ptr; + + info->pci_ep_cfg_base = pci->config_base; +} + static void cb_parse_mac_addresses(unsigned char *ptr, struct sysinfo_t *info) { @@ -412,6 +419,9 @@ case CB_TAG_FMAP: cb_parse_fmap_cache(ptr, info); break; + case CB_TAG_PCI_EP_CONFIG: + cb_parse_pci_ep_config_base(ptr, info); + break; default: cb_parse_arch_specific(rec, info); break; diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index be40c38..48e5ef5 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -89,6 +89,7 @@ LB_TAG_OPTION_ENUM = 0x00ca, LB_TAG_OPTION_DEFAULTS = 0x00cb, LB_TAG_OPTION_CHECKSUM = 0x00cc, + LB_TAG_PCI_EP_CONFIG = 0x00cd, }; /* Since coreboot is usually compiled 32bit, gcc will align 64bit @@ -326,6 +327,13 @@ struct lb_gpio gpios[0]; }; +/* PCI config info */ +struct lb_pci_config_info { + uint32_t tag; + uint32_t size; + void *config_base; +}; + struct lb_range { uint32_t tag; uint32_t size; diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index e77c60a..0240b87 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -21,6 +21,11 @@ void lb_add_serial(struct lb_serial *serial, void *data); void lb_add_console(uint16_t consoletype, void *data); +/*Fill PCIe endpoint config window base address*/ +void lb_fill_ep_config_window(struct lb_pci_config_info *pci); +void lb_add_pci(struct lb_header *header); +void lb_add_pci_config(struct lb_pci_config_info *info, struct lb_pci_config_info *data); + /* Define this in mainboard.c to add board-specific table entries. */ void lb_board(struct lb_header *header); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index cb85a18..7c89fc8 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -92,6 +92,21 @@ return mem; } +void lb_add_pci_config(struct lb_pci_config_info *info, struct lb_pci_config_info *data) +{ + data->config_base = info->config_base; +} + +void lb_add_pci(struct lb_header *header) +{ + struct lb_pci_config_info *pci = NULL; + + pci = (struct lb_pci_config_info *)lb_new_record(header); + pci->tag = LB_TAG_PCI_EP_CONFIG; + pci->size = sizeof(*pci); + lb_fill_ep_config_window(pci); +} + void lb_add_serial(struct lb_serial *new_serial, void *data) { struct lb_header *header = (struct lb_header *)data; @@ -485,6 +500,10 @@ if (CONFIG(CHROMEOS)) lb_gpios(head); + /* Store MMCONF_BASE Address for ep config access */ + if (CONFIG(SC7280_PCIE_NVME)) + lb_add_pci(head); + /* pass along VBNV offsets in CMOS */ if (CONFIG(VBOOT_VBNV_CMOS)) lb_table_add_vbnv_cmos(head); diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig index f182e9d..20d6289 100644 --- a/src/soc/qualcomm/sc7280/Kconfig +++ b/src/soc/qualcomm/sc7280/Kconfig @@ -45,4 +45,8 @@ help Select the QUP instance to be used for UART console output. +config SC7280_PCIE_NVME + bool + default y + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/53903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cfb95e31b7ee984ee0c2e7586e6caeecd7deadd Gerrit-Change-Number: 53903 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: sc7280: Add PCIe RC driver in Coreboot
by Ravi kumar (Code Review) 07 May '21

07 May '21

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53902 ) Change subject: sc7280: Add PCIe RC driver in Coreboot ...................................................................... sc7280: Add PCIe RC driver in Coreboot In coreboot ram stage, PCIe root complex driver initialize the PCIe core, QMP PHY and does the bus enumeration. Upon successful detection of EP(NVMe), PCIe RC driver allocates the resources and set the configuration parameters. Below are the changes added. (a) PCIe Core reset, init, link training. (b) Bus enumeration and resource allocation (c) QMP PHY 3x2 initialization Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631 Signed-off-by: Prasad Malisetty <pmaliset(a)codeaurora.org> --- M src/mainboard/google/herobrine/mainboard.c M src/soc/qualcomm/sc7280/Makefile.inc M src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/pcie.h A src/soc/qualcomm/sc7280/include/soc/qcom_qmp_phy.h A src/soc/qualcomm/sc7280/pcie_host.c 6 files changed, 1,701 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/53902/1 diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c index 351cb92..52e7b00 100644 --- a/src/mainboard/google/herobrine/mainboard.c +++ b/src/mainboard/google/herobrine/mainboard.c @@ -1,11 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <device/device.h> #include <bootblock_common.h> #include <soc/qupv3_config.h> #include <soc/clock.h> #include <soc/usb.h> #include <delay.h> +#include <soc/pcie.h> + +static void setup_pcie(void) +{ + /* Asseert NVMe External LDO's GPIO */ + gpio_output(GPIO(19), 1); + + setup_pcie_host(); +} static void setup_usb(void) { @@ -13,6 +23,7 @@ mdelay(2); setup_usb_host0(); } + static void mainboard_init(struct device *dev) { qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_I2C, GSI); /* APPS I2C */ @@ -32,6 +43,9 @@ clock_configure_sdcc(2, 50 * MHz); setup_usb(); + + /* Set up PCIe in RC mode */ + setup_pcie(); } static void mainboard_enable(struct device *dev) diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index 9929a45..74a6826 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -38,7 +38,8 @@ ramstage-y += qcom_qup_se.c ramstage-y += aop_load_reset.c ramstage-y += cpucp_load_reset.c - +ramstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c +ramstage-y += pcie_host.c ################################################################################ CPPFLAGS_common += -Isrc/soc/qualcomm/sc7280/include diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h index 04cb595..e58873e 100644 --- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -51,4 +51,36 @@ #define QMP_PHY_PCS_REG_BASE 0x088e9c00 #define USB_HOST_DWC3_BASE 0x0a60c100 +/* PCIE_1 */ +#define PCIE1_PCIE_PARF 0x01C08000 +#define PCIE1_GEN3X2_PCIE_DBI 0x40000000 +#define PCIE1_GEN3X2_PCIE_ELBI 0x40000F20 +#define PCIE1_GEN3X2_DWC_PCIE_DM_IATU 0x40001000 +#define PCIE1_CM_PCIE_BCM_PCIE_B 0x01C0E000 +#define PCIE1_GEN3x2_CONF 0x40100000 +#define PCIE1_GEN3x2_CONF_SIZE 0x100000 +#define PCIE1_BCR 0x18D000 + +/* MEMORY RANGES */ +#define PCIE1_IO_ADDR 0x40200000 +#define PCIE1_IO_SIZE 0x100000 +#define PCIE1_MEM_ADDR 0x40300000 +#define PCIE1_MEM_SIZE 0x1fd00000 +#define PCIE_MEM_END 0x404fffff + +/* QMP PCIE_1 PHY */ +#define PCIE_1_QMP_PHY 0x01C0E000 + +/* QMP PHY, Serdes,Tx, Rx and PCS register definitions */ +#define PCIE1_QMP_PHY_PCS_COM 0x01C0EA00 +#define PCE1_QPHY_SERDES 0x01C0E000 +#define PCE1_QPHY_TX0 0x01C0E200 +#define PCE1_QPHY_RX0 0x01C0E400 +#define PCE1_QPHY_TX1 0x01C0E600 +#define PCE1_QPHY_RX1 0x01C0E800 +#define PCE1_QPHY_PCS_MISC 0x01C0EE00 + +/*PHY BCR */ +#define GCC_PCIE_1_PHY_BCR 0x18E01C + #endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/pcie.h b/src/soc/qualcomm/sc7280/include/soc/pcie.h new file mode 100644 index 0000000..cc57105 --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/pcie.h @@ -0,0 +1,223 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <types.h> + +#ifndef _SC7280_PCIE_H_ +#define _SC7280_PCIE_H_ + +#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ +#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ +#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ +#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ +#define PCI_COMMAND_SERR 0x100 /* Enable SERR */ +#define PERST 2 +#define PCIE1_CAP 0x70 + +#define DEVICE_TYPE_RC 0x4 +#define PCIE1_PARF_DEVICE_TYPE 0x1000 +#define PCI_CLASS_DEVICE 0x0a /* Device class */ +#define DEV_ID_SZ 16 +#define CLASS_SZ 16 +#define HEADER_SZ 8 +#define VEND_ID_SZ 16 +#define PCIE_HDR_TYP 0x0e /* 8 bits */ +#define PCIE_VEND_ID 0x00 /* 16 bits */ +#define PCIE_DEV_ID 0x02 /* 16 bits */ +#define PCIE_CLASS 0x0a +#define PCI_MAX_DEV_FN 0x100 + +/* Parameters for the waiting for link up routine */ +#define LINK_WAIT_MAX_RETRIES 10 +#define PCIE1_PARF_LTSSM 0x1B0 +#define PCIE_LINK_CAPABILITY 0x7c +#define PCIE_LINK_CTL_2 0xa0 +#define TARGET_LINK_SPEED_MASK 0xf +#define LINK_SPEED_GEN_1 0x1 +#define LINK_SPEED_GEN_2 0x2 +#define LINK_SPEED_GEN_3 0x3 +#define PCIE_LINK_UP_MS 100 +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_USLEEP_MIN 90000 +#define LINK_WAIT_USLEEP_MAX 100000 +#define PCIE1_3x2_NUM_LANES 2 +#define XMLH_LINK_UP 0x400 +#define PCIE3X2_ELBI_SYS_STTS 0x08 +#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C +#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) +#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) +#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) +#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) +#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) +#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8) + +/* Parameters for the waiting for iATU enabled routine */ +#define LINK_WAIT_MAX_IATU_RETRIES 5 +#define LINK_WAIT_IATU 10000 + +#define PCIE_MISC_CONTROL_1_OFF 0x8BC +#define PERST_DELAY_US 1000 +#define PCIE_MAX_BARS 6 +#define MAX_CAPABILITY_CACHE 16 +#define PCIBIOS_BAD_REGISTER_NUMBER 0x87 +#define HEADER_TYPE_BRIDGE 1 + +/* Synopsys-specific PCIe configuration registers */ +#define PCIE_PORT_LINK_CONTROL 0x710 +#define PORT_LINK_MODE_MASK (0x3f << 16) +#define PORT_LINK_MODE_1_LANES (0x1 << 16) +#define PORT_LINK_MODE_2_LANES (0x3 << 16) +#define PORT_LINK_MODE_4_LANES (0x7 << 16) +#define PORT_LINK_MODE_8_LANES (0xf << 16) +#define PCIE_CFG_TYPE1_BUS (0x0018) /**< Bus config offset */ + + +#define ENABLE 1 +#define DISABLE 0 +#define ETIMEDOUT -10 +#define READ 0 +#define WRITE 1 +#define BYTE 8 +#define WORD 16 +#define DWORD 32 + +#define PCIE_ATU_VIEWPORT 0x900 +#define PCIE_ATU_REGION_INBOUND (0x1 << 31) +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE_ATU_REGION_INDEX2 (0x2 << 0) +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) +#define PCIE_ATU_CR1 0x904 +#define PCIE_ATU_TYPE_MEM (0x0 << 0) +#define PCIE_ATU_TYPE_IO (0x2 << 0) +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) +#define PCIE_ATU_CR2 0x908 +#define PCIE_ATU_ENABLE (0x1 << 31) +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) +#define PCIE_ATU_LOWER_BASE 0x90C +#define PCIE_ATU_UPPER_BASE 0x910 +#define PCIE_ATU_LIMIT 0x914 +#define PCIE_ATU_LOWER_TARGET 0x918 +#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) +#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) +#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) +#define PCIE_ATU_UPPER_TARGET 0x91C + +#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ +#define PCI_LATENCY_TIMER 0x0d /* 8 bits */ +#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ +#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ +#define PCI_INTERRUPT_LINE_DISABLE 0xff + +#define PCIE_MISC_CONTROL_1_OFF 0x8BC +#define PCIE_DBI_RO_WR_EN (0x1 << 0) + +/* + * iATU Unroll-specific register definitions + * From 4.80 core version the address translation will be made by unroll + */ +#define PCIE_ATU_UNR_REGION_CTRL1 0x00 +#define PCIE_ATU_UNR_REGION_CTRL2 0x04 +#define PCIE_ATU_UNR_LOWER_BASE 0x08 +#define PCIE_ATU_UNR_UPPER_BASE 0x0C +#define PCIE_ATU_UNR_LIMIT 0x10 +#define PCIE_ATU_UNR_LOWER_TARGET 0x14 +#define PCIE_ATU_UNR_UPPER_TARGET 0x18 + +#define PCI_BASE_ADDRESS_0 0x10 +#define PCI_BASE_ADDRESS_1 0x14 +#define PCI_BASE_ADDRESS_2 0x18 +#define PCI_BASE_ADDRESS_3 0x1c +#define PCI_BASE_ADDRESS_4 0x20 +#define PCI_BASE_ADDRESS_5 0x24 +#define PCI_BASE_ADDRESS_SPACE 1 // mask +#define PCI_BASE_ADDRESS_SPACE_IO 1 +#define PCI_BASE_ADDRESS_SPACE_MEM 0 +#define PCI_BASE_ADDR_MEM_MSK ~0xf +#define PCI_BASE_ADDR_IO_MSK ~0x3 + +#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 +#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ + +#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ +#define PCI_COMMAND 0x04 /* 16 bits */ +#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ +#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ +#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ +#define PCI_CLASS_BRIDGE_PCI 0x0604 + +#define PCIE1_PARF_SYS_CTRL 0x00 +#define PCIE1_PARF_DBI_BASE_ADDR 0x168 +#define PCIE1_PARF_MHI_CLOCK_RESET_CTRL 0x174 + + +/* QMP PHY, Serdes,Tx, Rx and PCS register definitions */ +#define PCIE1_QMP_PHY_PCS_COM 0x01C0EA00 +#define PCE1_QPHY_SERDES 0x01C0E000 +#define PCE1_QPHY_TX0 0x01C0E200 +#define PCE1_QPHY_RX0 0x01C0E400 +#define PCIE1_PARF_PHY_CTRL 0x40 + +#define PCE1_QPHY_TX1 0x01C0E600 +#define PCE1_QPHY_RX1 0x01C0E800 +#define PCE1_QPHY_PCS_MISC 0x01C0EE00 + +#define PCI_MEMORY_BASE 0x20 +#define PCIE1_MEM_END 0x404fffff + +#define GCC_PCIE_1_PHY_BCR 0x18E01C + +#define PCIE_DEV_FUNC (dev,func) PCI_SLOT(devfn) | PCI_FUNC(devfn) + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; +typedef unsigned long pci_addr_t; +typedef unsigned long pci_size_t; +typedef unsigned int pci_dev_t; + +struct pcie_region { + pci_addr_t bus_start; /* Start on the bus */ + phys_addr_t phys_start; /* Start in physical address space */ + pci_size_t size; /* Size */ + unsigned long flags; /* Resource flags */ + pci_addr_t bus_lower; +}; + + +#define PCIE_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) + +#define PCIE_DEV(_bus, _dev, _fn) (0x80000000 | \ + (uint32_t)(_bus << 16) | (uint32_t)(_dev << 11) | (uint32_t)(_fn << 8) + +#define PCIE_FUNC(d) (((d) >> 8) & 0x7) +#define PCIE_SLOT(devfn) (((devfn) >> 3) & 0x1f) +#define PCIE_MASK_BUS(bdf) ((bdf) & 0xffff) +#define PCIE_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn)) +#define PCIE_BUS(d) (((d) >> 16) & 0xff) +#define PCIE_BDF(b, d, f) ((b) << 16 | (d) << 11 | (f) << 8) +#define PCIE_VENDEV(v, d) (((v) << 16) | (d)) +#define PCIE_ANY_ID (~0) + +#define PCIE_BUS_CFG(pri, sec, sub) ((sub & 0xFF)<<16|(sec & 0xFF)<<8|(pri&0xFF)) +#define lower_32_bits(n) ((u32)(n)) +#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) + +/* Register address builder */ +#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9) + +struct qcom_qmp_phy_init_tbl { + unsigned int offset; + unsigned int val; + uint8_t lane_mask; +}; + +#define QMP_PHY_INIT_CFG(o, v) \ + { \ + .offset = o, \ + .val = v, \ + .lane_mask = 0xff, \ +} + +/* PCIe setup */ +void setup_pcie_host(void); + +#endif diff --git a/src/soc/qualcomm/sc7280/include/soc/qcom_qmp_phy.h b/src/soc/qualcomm/sc7280/include/soc/qcom_qmp_phy.h new file mode 100755 index 0000000..806df30 --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/qcom_qmp_phy.h @@ -0,0 +1,278 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_H_ +#define QCOM_PHY_QMP_H_ + +/* Only for QMP V4 PHY - QSERDES COM registers */ +#define QSERDES_V4_COM_SSC_EN_CENTER 0x010 +#define QSERDES_V4_COM_SSC_PER1 0x01c +#define QSERDES_V4_COM_SSC_PER2 0x020 +#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 +#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 +#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 +#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 +#define QSERDES_V4_COM_CLK_ENABLE1 0x048 +#define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 +#define QSERDES_V4_COM_PLL_IVCO 0x058 +#define QSERDES_V4_COM_CMN_IPTRIM 0x060 +#define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 +#define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 +#define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c +#define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 +#define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 +#define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 +#define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 +#define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 +#define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac +#define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 +#define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 +#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc +#define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 +#define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 +#define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc +#define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 +#define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4 +#define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 +#define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc +#define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 +#define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c +#define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 +#define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 +#define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 +#define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c +#define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 +#define QSERDES_V4_COM_CLK_SELECT 0x154 +#define QSERDES_V4_COM_HSCLK_SEL 0x158 +#define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c +#define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c +#define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 +#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac +#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 +#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 +#define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc +#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 + +/* Only for QMP V4 PHY - TX registers */ +#define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34 +#define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38 +#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c +#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40 +#define QSERDES_V4_TX_LANE_MODE_1 0x84 +#define QSERDES_V4_TX_LANE_MODE_2 0x88 +#define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c +#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 +#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC +#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 +#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 +#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 +#define QSERDES_V4_TX_PI_QEC_CTRL 0x104 + +/* Only for QMP V4 PHY - RX registers */ +#define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 +#define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 +#define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 +#define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 +#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c +#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 +#define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 +#define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 +#define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c +#define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 +#define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 +#define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 +#define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 +#define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064 +#define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 +#define QSERDES_V4_RX_AC_JTAG_MODE 0x078 +#define QSERDES_V4_RX_RX_TERM_BW 0x080 +#define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 +#define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 +#define QSERDES_V4_RX_GM_CAL 0x0dc +#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 +#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec +#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 +#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 +#define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 +#define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc +#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 +#define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 +#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 +#define QSERDES_V4_RX_SIGDET_ENABLES 0x118 +#define QSERDES_V4_RX_SIGDET_CNTRL 0x11c +#define QSERDES_V4_RX_SIGDET_LVL 0x120 +#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 +#define QSERDES_V4_RX_RX_BAND 0x128 +#define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 +#define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 +#define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 +#define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c +#define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 +#define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 +#define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 +#define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c +#define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 +#define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 +#define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 +#define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c +#define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 +#define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 +#define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 +#define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 +#define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 +#define QSERDES_V4_RX_DCC_CTRL1 0x1bc +#define QSERDES_V4_RX_VTH_CODE 0x1c4 + + +/* Only for QMP V4 PHY - PCIe PCS registers */ +#define QPHY_V4_PCS_SW_RESET 0x000 +#define QPHY_V4_PCS_REVISION_ID0 0x004 +#define QPHY_V4_PCS_REVISION_ID1 0x008 +#define QPHY_V4_PCS_REVISION_ID2 0x00c +#define QPHY_V4_PCS_REVISION_ID3 0x010 +#define QPHY_V4_PCS_PCS_STATUS1 0x014 +#define QPHY_V4_PCS_PCS_STATUS2 0x018 +#define QPHY_V4_PCS_PCS_STATUS3 0x01c +#define QPHY_V4_PCS_PCS_STATUS4 0x020 +#define QPHY_V4_PCS_PCS_STATUS5 0x024 +#define QPHY_V4_PCS_PCS_STATUS6 0x028 +#define QPHY_V4_PCS_PCS_STATUS7 0x02c +#define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 +#define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 +#define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 +#define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c +#define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 +#define QPHY_V4_PCS_START_CONTROL 0x044 +#define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 +#define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c +#define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 +#define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 +#define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 +#define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c +#define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 +#define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 +#define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 +#define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c +#define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 +#define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 +#define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 +#define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c +#define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 +#define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 +#define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 +#define QPHY_V4_PCS_CLAMP_ENABLE 0x08c +#define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 +#define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 +#define QPHY_V4_PCS_FLL_CNTRL1 0x098 +#define QPHY_V4_PCS_FLL_CNTRL2 0x09c +#define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 +#define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 +#define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 +#define QPHY_V4_PCS_TEST_CONTROL1 0x0ac +#define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 +#define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 +#define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 +#define QPHY_V4_PCS_TEST_CONTROL5 0x0bc +#define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 +#define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 +#define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc +#define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 +#define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 +#define QPHY_V4_PCS_BIST_CTRL 0x0e8 +#define QPHY_V4_PCS_PRBS_POLY0 0x0ec +#define QPHY_V4_PCS_PRBS_POLY1 0x0f0 +#define QPHY_V4_PCS_FIXED_PAT0 0x0f4 +#define QPHY_V4_PCS_FIXED_PAT1 0x0f8 +#define QPHY_V4_PCS_FIXED_PAT2 0x0fc +#define QPHY_V4_PCS_FIXED_PAT3 0x100 +#define QPHY_V4_PCS_FIXED_PAT4 0x104 +#define QPHY_V4_PCS_FIXED_PAT5 0x108 +#define QPHY_V4_PCS_FIXED_PAT6 0x10c +#define QPHY_V4_PCS_FIXED_PAT7 0x110 +#define QPHY_V4_PCS_FIXED_PAT8 0x114 +#define QPHY_V4_PCS_FIXED_PAT9 0x118 +#define QPHY_V4_PCS_FIXED_PAT10 0x11c +#define QPHY_V4_PCS_FIXED_PAT11 0x120 +#define QPHY_V4_PCS_FIXED_PAT12 0x124 +#define QPHY_V4_PCS_FIXED_PAT13 0x128 +#define QPHY_V4_PCS_FIXED_PAT14 0x12c +#define QPHY_V4_PCS_FIXED_PAT15 0x130 +#define QPHY_V4_PCS_TXMGN_CONFIG 0x134 +#define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 +#define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c +#define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 +#define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 +#define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 +#define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c +#define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 +#define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 +#define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 +#define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c +#define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 +#define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 +#define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 +#define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c +#define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 +#define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 +#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 +#define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c +#define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 +#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 +#define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c +#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 +#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 +#define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 +#define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c +#define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 +#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 +#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 +#define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac +#define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 +#define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 +#define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 +#define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc +#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 +#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 +#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 +#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc +#define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 +#define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 +#define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 +#define QPHY_V4_PCS_EQ_CONFIG1 0x1dc +#define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 +#define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 +#define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 +#define QPHY_V4_PCS_EQ_CONFIG5 0x1ec + + +/* Only for QMP V4 PHY - PCS_MISC registers */ +#define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 +#define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 +#define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 +#define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c +#define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 +#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 + +/* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ +#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c +#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 +#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c +#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 +#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 +#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 +#define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 +#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 +#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc +#define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 + +#endif + diff --git a/src/soc/qualcomm/sc7280/pcie_host.c b/src/soc/qualcomm/sc7280/pcie_host.c new file mode 100644 index 0000000..81b37f2 --- /dev/null +++ b/src/soc/qualcomm/sc7280/pcie_host.c @@ -0,0 +1,1152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <boot/coreboot_tables.h> +#include <device/mmio.h> +#include <soc/clock.h> +#include <soc/pcie.h> +#include <soc/qcom_qmp_phy.h> +#include <soc/addressmap.h> +#include <timer.h> +#include <delay.h> +#include <soc/gpio.h> +#include <gpio.h> + +/* QPHY_SW_RESET bit */ +#define SW_RESET BIT(0) +#define SW_PWRDN BIT(0) + +/* QPHY_PCS_STATUS bit */ +#define PHYSTATUS BIT(6) +#define PCS_START BIT(1) + +#define QPHY_SW_RESET 0x00 +#define QPHY_START_CTRL 0x44 +#define QPHY_PCS_STATUS 0x14 +#define QPHY_PCS_PWR_DWN_CNTRL 0x40 +#define PCIE1_BDF_TO_SID_CFG 0x2C00 + +/** + * struct pcie_rc_config_t - QCOM DW PCIe Controller state + * + *@lanes : Number of lanes + * @cfg_size : The size of the configuration space + * @db_base : The base address of dbi register space + * @atu_base : The base address of address translation unit + * @parf : The base address of PARF register space + * @elbi : The base address of ELBI space + * @phy : Base address of the PHY controller + * @pcie_1_bcr : address of the block controller register + * @reset : PERST gpio + * @io : Base address of the IO region + * @mem : Base address of memory region + * + */ +typedef struct { + uint32_t lanes; + uint32_t cfg_size; + void *cfg_base; + void *dbi_base; + void *atu_base; + void *parf; + void *elbi; + void *pcie1_bcr; + void *qmp_phy_bcr; + gpio_t perst; + /* IO and MEM PCI regions */ + struct pcie_region io; + struct pcie_region mem; +} pcie_rc_config_t; + +typedef struct { + void *qmp_phy_base; + void *serdes; + void *tx0; + void *rx0; + void *pcs; + void *tx1; + void *rx1; + void *pcs_misc; + + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qcom_qmp_phy_init_tbl *serdes_tbl; + int serdes_tbl_num; + const struct qcom_qmp_phy_init_tbl *serdes_tbl_sec; + int serdes_tbl_num_sec; + const struct qcom_qmp_phy_init_tbl *tx_tbl; + int tx_tbl_num; + const struct qcom_qmp_phy_init_tbl *tx_tbl_sec; + int tx_tbl_num_sec; + const struct qcom_qmp_phy_init_tbl *rx_tbl; + int rx_tbl_num; + const struct qcom_qmp_phy_init_tbl *rx_tbl_sec; + int rx_tbl_num_sec; + const struct qcom_qmp_phy_init_tbl *pcs_tbl; + int pcs_tbl_num; + const struct qcom_qmp_phy_init_tbl *pcs_tbl_sec; + int pcs_tbl_num_sec; + const struct qcom_qmp_phy_init_tbl *pcs_misc_tbl; + int pcs_misc_tbl_num; + const struct qcom_qmp_phy_init_tbl *pcs_misc_tbl_sec; + int pcs_misc_tbl_num_sec; +} qmp_phy_cfg_t; + +struct pcierc_dwc_t { + pcie_rc_config_t *rc_cfg; + qmp_phy_cfg_t *qmp_phy_cfg; + int bdf; + uint16_t vendor_id; + uint16_t device_id; + uint32_t class_code; + uint8_t header; + uint8_t current_bus; + uint8_t pri_bus; + uint8_t sec_bus; + uint8_t sub_bus; + /* Future purpose */ + uint32_t capabilities[MAX_CAPABILITY_CACHE]; +}; + +static const struct qcom_qmp_phy_init_tbl sc7280_qmp_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), +}; + +static const struct qcom_qmp_phy_init_tbl sc7280_qmp_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), +}; + +static const struct qcom_qmp_phy_init_tbl sc7280_qmp_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), +}; + +static const struct qcom_qmp_phy_init_tbl sc7280_qmp_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), +}; + +static const struct qcom_qmp_phy_init_tbl sc7280_qmp_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), +}; + +static const struct qcom_qmp_phy_init_tbl sc7280_qmp_gen3x2_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), +}; + +static const struct qcom_qmp_phy_init_tbl sc7280_qmp_gen3x2_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), +}; + +static const struct qcom_qmp_phy_init_tbl sc7280_qmp_gen3x2_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), +}; + +static const struct qcom_qmp_phy_init_tbl sc7280_qmp_gen3x2_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), +}; + +static pcie_rc_config_t pcie_host = { + .parf = (void *) PCIE1_PCIE_PARF, + .dbi_base = (void *) PCIE1_GEN3X2_PCIE_DBI, + .elbi = (void *) PCIE1_GEN3X2_PCIE_ELBI, + .atu_base = (void *) PCIE1_GEN3X2_DWC_PCIE_DM_IATU, + .cfg_base = (void *) PCIE1_GEN3x2_CONF, + .pcie1_bcr = (void *) PCIE1_BCR, + .qmp_phy_bcr = (void *) GCC_PCIE_1_PHY_BCR, + .lanes = PCIE1_3x2_NUM_LANES, + .cfg_size = PCIE1_GEN3x2_CONF_SIZE, + .perst = GPIO(2), + + /* Store the IO and MEM windows settings for future use by the ATU */ + .io.phys_start = PCIE1_IO_ADDR, /* IO base */ + .io.bus_start = PCIE1_IO_ADDR, /* IO_bus_addr */ + .io.size = PCIE1_IO_SIZE, /* IO size */ + + .mem.phys_start = PCIE1_MEM_ADDR, /* MEM base */ + .mem.bus_start = PCIE1_MEM_ADDR, /* MEM_bus_addr */ + .mem.size = PCIE1_MEM_SIZE, /* MEM size */ +}; + +static qmp_phy_cfg_t pcie1_qmp_phy_3x2 = { + .qmp_phy_base = (void *) PCIE_1_QMP_PHY, + .serdes = (void *) PCE1_QPHY_SERDES, + .tx0 = (void *) PCE1_QPHY_TX0, + .rx0 = (void *) PCE1_QPHY_RX0, + .pcs = (void *) PCIE1_QMP_PHY_PCS_COM, + .tx1 = (void *) PCE1_QPHY_TX1, + .rx1 = (void *) PCE1_QPHY_RX1, + .pcs_misc = (void *) PCE1_QPHY_PCS_MISC, + .serdes_tbl = sc7280_qmp_pcie_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sc7280_qmp_pcie_serdes_tbl), + .tx_tbl = sc7280_qmp_pcie_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sc7280_qmp_pcie_tx_tbl), + .tx_tbl_sec = sc7280_qmp_gen3x2_pcie_tx_tbl, + .tx_tbl_num_sec = ARRAY_SIZE(sc7280_qmp_gen3x2_pcie_tx_tbl), + .rx_tbl = sc7280_qmp_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sc7280_qmp_pcie_rx_tbl), + .rx_tbl_sec = sc7280_qmp_gen3x2_pcie_rx_tbl, + .rx_tbl_num_sec = ARRAY_SIZE(sc7280_qmp_gen3x2_pcie_rx_tbl), + .pcs_tbl = sc7280_qmp_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sc7280_qmp_pcie_pcs_tbl), + .pcs_tbl_sec = sc7280_qmp_gen3x2_pcie_pcs_tbl, + .pcs_tbl_num_sec = ARRAY_SIZE(sc7280_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc_tbl = sc7280_qmp_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num = ARRAY_SIZE(sc7280_qmp_pcie_pcs_misc_tbl), + .pcs_misc_tbl_sec = sc7280_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num_sec = ARRAY_SIZE(sc7280_qmp_gen3x2_pcie_pcs_misc_tbl), +}; + +void dw_pcie_setup_rc(struct pcierc_dwc_t *pcie); +int qcom_pcie_conv_size_to_32(int old, int value, uint32_t offset, + uint8_t size); + +int qcom_pcie_conv_32_to_size(int value, int offset, int size); + +static inline void qcom_pcie_set_region(struct pcie_region *reg, + pci_addr_t bus_start, + phys_addr_t phys_start, + pci_size_t size, + unsigned long flags) { + reg->bus_start = bus_start; + reg->phys_start = phys_start; + reg->size = size; + reg->flags = flags; +} + +/*fill EP config window */ +void lb_fill_ep_config_window(struct lb_pci_config_info *data) +{ + struct lb_pci_config_info pci_ep_cfg_info; + + pci_ep_cfg_info.config_base = (void*)PCIE1_GEN3x2_CONF; + + /* Add ep cfg addr in coreboot table and pass to libpayload */ + lb_add_pci_config(&pci_ep_cfg_info, data); +} + +/* + *Convtert 32 bit data into specified size. + * + */ +int qcom_pcie_conv_32_to_size(int value, int offset, int size) +{ + switch (size) { + case 8: + return (value >> ((offset & 3) * 8)) & 0xff; + case 16: + return (value >> ((offset & 2) * 8)) & 0xffff; + default: + return value; + } +} + +/* + *Convtert 8/16 bit data into 32 bit size for compatibility. + * + */ +int qcom_pcie_conv_size_to_32(int old, int value, uint32_t offset, + uint8_t size) +{ + uint32_t off_mask; + uint32_t val_mask, shift; + int ldata, mask; + + switch (size) { + case 8: + off_mask = 3; + val_mask = 0xff; + break; + case 16: + off_mask = 2; + val_mask = 0xffff; + break; + default: + return value; + } + shift = (offset & off_mask) * 8; + ldata = (value & val_mask) << shift; + mask = val_mask << shift; + value = (old & ~mask) | ldata; + + return value; +} + +static inline void dw_pcie_dbi_rd_wr_enable(struct pcierc_dwc_t *pcie, bool en) +{ + uint32_t val; + + val = read32(pcie->rc_cfg->dbi_base + PCIE_MISC_CONTROL_1_OFF); + + if (en) + val |= PCIE_DBI_RO_WR_EN; + else + val &= ~PCIE_DBI_RO_WR_EN; + + write32(pcie->rc_cfg->dbi_base + PCIE_MISC_CONTROL_1_OFF, val); +} + +static void dw_pcie_writel_ob_unroll(struct pcierc_dwc_t *pcie, + uint32_t index, uint32_t reg, uint32_t val) +{ + uint32_t offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); + + write32(pcie->rc_cfg->atu_base + offset + reg, val); +} + +static uint32_t dw_pcie_readl_ob_unroll(struct pcierc_dwc_t *pcie, + uint32_t index, uint32_t reg) +{ + int32_t val; + uint32_t offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); + + val = read32(pcie->rc_cfg->atu_base + offset + reg); + return val; +} + +static void qcom_dw_pcie_prog_outbound_atu(struct pcierc_dwc_t *pcie, + int index, int type, uint64_t cpu_addr, + uint64_t pcie_addr, uint32_t size) +{ + uint32_t retries, val; + + dw_pcie_writel_ob_unroll(pcie, index, PCIE_ATU_UNR_LOWER_BASE, + lower_32_bits(cpu_addr)); + dw_pcie_writel_ob_unroll(pcie, index, PCIE_ATU_UNR_UPPER_BASE, + upper_32_bits(cpu_addr)); + dw_pcie_writel_ob_unroll(pcie, index, PCIE_ATU_UNR_LIMIT, + lower_32_bits(cpu_addr + size - 1)); + dw_pcie_writel_ob_unroll(pcie, index, PCIE_ATU_UNR_LOWER_TARGET, + lower_32_bits(pcie_addr)); + dw_pcie_writel_ob_unroll(pcie, index, PCIE_ATU_UNR_UPPER_TARGET, + upper_32_bits(pcie_addr)); + dw_pcie_writel_ob_unroll(pcie, index, PCIE_ATU_UNR_REGION_CTRL1, + type); + dw_pcie_writel_ob_unroll(pcie, index, PCIE_ATU_UNR_REGION_CTRL2, + PCIE_ATU_ENABLE); + /* + * Make sure ATU enable takes effect before any subsequent config + * and I/O accesses. + */ + for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { + val = dw_pcie_readl_ob_unroll(pcie, index, + PCIE_ATU_UNR_REGION_CTRL2); + if (val & PCIE_ATU_ENABLE) + return; + udelay(LINK_WAIT_IATU); + } + printk(BIOS_EMERG, "outbound iATU is not being enabled\n"); +} + +static int qcom_dw_pcie_write(void *addr, int size, int val) +{ + switch (size) { + case 32: + write32(addr, val); + break; + case 16: + write16(addr, val); + break; + case 8: + write8(addr, val); + break; + default: + return PCIBIOS_BAD_REGISTER_NUMBER; + } + + return 0; +} + +static int qcom_dw_pcie_wr_own_config(struct pcierc_dwc_t *pcie, + int offset, int size, uint32_t val) +{ + return qcom_dw_pcie_write(pcie->rc_cfg->dbi_base + offset, size, val); +} + +static void configure_pcie_gpios(gpio_t perst_gpio) +{ + gpio_configure(perst_gpio, 0, GPIO_NO_PULL, + GPIO_16MA, GPIO_OUTPUT_ENABLE); + + printk(BIOS_INFO, "pcie ep PERST GPIO configured\n"); +} + +static void qcom_ep_reset_assert(gpio_t perst) +{ + gpio_set(perst, 0); + mdelay(100); + printk(BIOS_INFO,"pcie ep PERST asserted \n"); +} + +static void qcom_ep_reset_deassert(gpio_t perst) +{ + /* Ensure that PERST has been asserted for at least 100 ms */ + mdelay(100); + gpio_set(perst, 1); + mdelay(50); + printk(BIOS_NOTICE,"pcie ep PERST desserted\n"); +} + +/** + * pcie_dw_configure() - Configure link capabilities and speed + * + * Configure the link capabilities and speed in the PCIe root complex. + */ +static void qcom_pcie_dw_configure(struct pcierc_dwc_t *pci, uint32_t cap_speed) +{ + pcie_rc_config_t *pcierc = pci->rc_cfg; + uint32_t val; + + dw_pcie_dbi_rd_wr_enable(pci, ENABLE); + + val = read32(pcierc->dbi_base + PCIE_LINK_CAPABILITY); + val &= ~TARGET_LINK_SPEED_MASK; + val |= cap_speed; + write32(pcierc->dbi_base + PCIE_LINK_CAPABILITY, val); + + val = read32(pcierc->dbi_base + PCIE_LINK_CTL_2); + val &= ~TARGET_LINK_SPEED_MASK; + val |= cap_speed; + write32(pcierc->dbi_base + PCIE_LINK_CTL_2, val); + + dw_pcie_dbi_rd_wr_enable(pci, DISABLE); + printk(BIOS_INFO, "Link speed configured in Gen %d\n", cap_speed); +} + +/** + * is_link_up() - Return the link state + * + * Return: 1 (true) for active line and 0 (false) for no link + */ +static bool is_pcie_link_up(struct pcierc_dwc_t *pci) +{ + int val, res = 0; + + /* Read link status register*/ + val = read32(pci->rc_cfg->elbi+PCIE3X2_ELBI_SYS_STTS); + res = val & XMLH_LINK_UP; + return res; +} + +/** + * wait_link_up() - Wait for the link to come up + * + * Return: 1 (true) for active line and 0 (false) for no link (timeout) + */ +static int wait_link_up(struct pcierc_dwc_t *pci) +{ + int retries; + + /* Check if the link is up or not */ + for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + if (is_pcie_link_up(pci)) + return 0; + mdelay(PCIE_LINK_UP_MS); + } + printk(BIOS_EMERG, "link never came up\n"); + return -ETIMEDOUT; +} + +static bool qcom_pcie_dw_link_up(struct pcierc_dwc_t *pcie) +{ + uint32_t val; + + if (is_pcie_link_up(pcie)) { + printk(BIOS_EMERG, "PCIe Link is already up\n"); + return 0; + } + + /* DW pre link configurations */ + qcom_pcie_dw_configure(pcie, LINK_SPEED_GEN_2); + + /* enable link training */ + val = read32(pcie->rc_cfg->parf + PCIE1_PARF_LTSSM); + val |= BIT(8); + write32(pcie->rc_cfg->parf + PCIE1_PARF_LTSSM, val); + + /* Check that link was established */ + if (!wait_link_up(pcie)) { + printk(BIOS_EMERG, "Link up\n"); + return 0; + } + /* + * Link can be established in Gen 1. still need to wait + */ + udelay(100); + return -1; +} + +static int qcom_dw_pcie_write_cfg(struct pcierc_dwc_t *pcierc, uint32_t bdf, + int offset, int value, uint8_t size) +{ + int atu_type; + uint32_t cfg_size; + int old_value; + void *cfg_address; + int busdev; + + busdev = PCIE_ATU_BUS(pcierc->current_bus) | + PCIE_ATU_DEV(PCIE_SLOT(bdf)) | PCIE_ATU_FUNC(PCIE_FUNC(bdf)); + + /* Accessing root port configuration space. */ + if (!pcierc->current_bus) { + cfg_address = pcierc->rc_cfg->dbi_base; + cfg_address += offset & ~0x3; + old_value = read32(cfg_address); + value = qcom_pcie_conv_size_to_32(old_value, value, offset, size); + write32(cfg_address, value); + + qcom_dw_pcie_prog_outbound_atu(pcierc, PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_IO, + pcierc->rc_cfg->io.bus_start, + pcierc->rc_cfg->io.bus_start, + pcierc->rc_cfg->io.size); + return 0; + } + + if (pcierc->current_bus == 1) + /* For local bus, change TLP Type field to 4. */ + atu_type = PCIE_ATU_TYPE_CFG0; + else + /* Otherwise, change TLP Type field to 5. */ + atu_type = PCIE_ATU_TYPE_CFG1; + + cfg_address = pcierc->rc_cfg->cfg_base; + cfg_size = pcierc->rc_cfg->cfg_size; + + qcom_dw_pcie_prog_outbound_atu(pcierc, PCIE_ATU_REGION_INDEX1, + atu_type, (uint64_t)cfg_address, + busdev, cfg_size); + + cfg_address += offset & ~0x3; + old_value = read32(cfg_address); + + value = qcom_pcie_conv_size_to_32(old_value, value, offset, size); + + write32((void *)cfg_address, value); + + qcom_dw_pcie_prog_outbound_atu(pcierc, PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_IO, + pcierc->rc_cfg->io.bus_start, + pcierc->rc_cfg->io.bus_start, + pcierc->rc_cfg->io.size); + return 0; +} + +static int qcom_dw_pcie_read_cfg(struct pcierc_dwc_t *pcierc, int bdf, + int offset, int *val, uint8_t size) +{ + int atu_type; + uint32_t cfg_size; + int value; + void *cfg_address; + int busdev; + + busdev = PCIE_ATU_BUS(pcierc->current_bus) | + PCIE_ATU_DEV(PCIE_SLOT(bdf)) | + PCIE_ATU_FUNC(PCIE_FUNC(bdf)); + + /* Accessing root port configuration space. */ + if (!pcierc->current_bus) { + cfg_address = pcierc->rc_cfg->dbi_base; + cfg_address += offset & ~0x3; + value = read32(cfg_address); + *val = qcom_pcie_conv_32_to_size(value, offset, size); + + qcom_dw_pcie_prog_outbound_atu(pcierc, PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_IO, + pcierc->rc_cfg->io.bus_start, + pcierc->rc_cfg->io.bus_start, + pcierc->rc_cfg->io.size); + return 0; + } + + if (pcierc->current_bus == 1) + /* For local bus, change TLP Type field to 4. */ + atu_type = PCIE_ATU_TYPE_CFG0; + else + /* Otherwise, change TLP Type field to 5. */ + atu_type = PCIE_ATU_TYPE_CFG1; + + cfg_address = pcierc->rc_cfg->cfg_base; + cfg_size = pcierc->rc_cfg->cfg_size; + + qcom_dw_pcie_prog_outbound_atu(pcierc, PCIE_ATU_REGION_INDEX1, + atu_type, (uint64_t)cfg_address, + busdev, cfg_size); + + cfg_address += offset & ~0x3; + value = read32((void *)cfg_address); + *val = qcom_pcie_conv_32_to_size(value, offset, size); + + qcom_dw_pcie_prog_outbound_atu(pcierc, PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_IO, + pcierc->rc_cfg->io.bus_start, + pcierc->rc_cfg->io.bus_start, + pcierc->rc_cfg->io.size); + + return 0; +} + +static int qcom_dw_pcie_cfg_dev(struct pcierc_dwc_t *pcierc, pci_dev_t bdf, + unsigned long io, pci_addr_t mem) +{ + int32_t bar_response; + pci_addr_t bar_value; + pci_size_t bar_size; + int bar, found_mem64; + int bar_response_upper; + unsigned char pin; + int old_command; + uint64_t bar64; + + for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) { + qcom_dw_pcie_write_cfg(pcierc, bdf, bar, 0xffffffff, DWORD); + qcom_dw_pcie_read_cfg(pcierc, bdf, bar, &bar_response, DWORD); + + if (!bar_response) + continue; + + found_mem64 = 0; + + /* Check the BAR type and set our address mask */ + if (bar_response & PCI_BASE_ADDRESS_SPACE) { + bar_size = ~(bar_response & PCI_BASE_ADDR_IO_MSK) + 1; + /* round up region base address to a multiple of size */ + io = ((io - 1) | (bar_size - 1)) + 1; + bar_value = io; + /* compute new region base address */ + io = io + bar_size; + } else { + if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == + PCI_BASE_ADDRESS_MEM_TYPE_64) { + qcom_dw_pcie_write_cfg(pcierc, bdf, bar+4, + 0xffffffff, DWORD); + qcom_dw_pcie_read_cfg(pcierc, bdf, bar+4, + &bar_response_upper, + DWORD); + + bar64 = ((u64)bar_response_upper << 32) | + bar_response; + bar_size = ~(bar64 & PCI_BASE_ADDR_MEM_MSK) + 1; + found_mem64 = 1; + } else { + bar_size = (u32)(~(bar_response & + PCI_BASE_ADDR_MEM_MSK) + 1); + } + + /* round up region base address to multiple of size */ + mem = ((mem - 1) | (bar_size - 1)) + 1; + bar_value = mem; + /* compute new region base address */ + mem = mem + bar_size; + } + /* Write it out and update our limit */ + qcom_dw_pcie_write_cfg(pcierc, bdf, bar, bar_value, DWORD); + + if (found_mem64) { + bar += 4; + qcom_dw_pcie_write_cfg(pcierc, bdf, bar, + 0x00000000, DWORD); + } + } + + /* Configure Cache Line Size Register */ + qcom_dw_pcie_write_cfg(pcierc, bdf, PCI_CACHE_LINE_SIZE, 0x08, BYTE); + + /* Configure Latency Timer */ + qcom_dw_pcie_write_cfg(pcierc, bdf, PCI_LATENCY_TIMER, 0x80, BYTE); + + /* Disable interrupt line, if device says it wants to use interrupts */ + qcom_dw_pcie_read_cfg(pcierc, bdf, PCI_INTERRUPT_PIN, (int *)&pin, BYTE); + if (pin != 0) { + qcom_dw_pcie_write_cfg(pcierc, bdf, PCI_INTERRUPT_LINE, + PCI_INTERRUPT_LINE_DISABLE, BYTE); + } + + qcom_dw_pcie_read_cfg(pcierc, bdf, PCI_COMMAND, &old_command, DWORD); + qcom_dw_pcie_write_cfg(pcierc, bdf, PCI_COMMAND, + (old_command & 0xffff0000) | 0x6, DWORD); + + return 0; +} + +static void qcom_pcie_scan_bus(struct pcierc_dwc_t *pcierc, uint8_t bus) +{ + int vend_id, dev_id, class; + int dev, func, devfn; + int header_type; + + pcierc->current_bus = bus; + + for (devfn = 0; devfn < PCI_MAX_DEV_FN; devfn++) { + + func = devfn & 0x7; + dev = (devfn >> 3) & 0x1f; + + pcierc->bdf = PCIE_BDF(bus, dev, func); + + qcom_dw_pcie_read_cfg(pcierc, pcierc->bdf, + PCIE_VEND_ID, &vend_id, VEND_ID_SZ); + + if (vend_id == 0xffff || vend_id == 0x0000) { + return; + } + /* Device ID */ + qcom_dw_pcie_read_cfg(pcierc, pcierc->bdf, + PCIE_DEV_ID, &dev_id, DEV_ID_SZ); + + /* Class Code */ + qcom_dw_pcie_read_cfg(pcierc, pcierc->bdf, + PCIE_CLASS, &class, CLASS_SZ); + + /* Header type */ + qcom_dw_pcie_read_cfg(pcierc, pcierc->bdf, + PCIE_HDR_TYP, &header_type, HEADER_SZ); + + printk(BIOS_NOTICE, "Device found: Vend id: 0x%x " + "Dev id: 0x%x, class id: 0x%x on" + " 0x%x: 0x%x: 0x%x with header 0x%x\n", + vend_id, dev_id, class, + bus, dev, func, header_type); + + if (header_type == HEADER_TYPE_BRIDGE) { + pcierc->pri_bus = bus; + pcierc->sec_bus = bus + 1; + pcierc->sub_bus = 0xFF; + + qcom_dw_pcie_write_cfg(pcierc, pcierc->bdf, + PCIE_CFG_TYPE1_BUS, + PCIE_BUS_CFG(pcierc->pri_bus, pcierc->sec_bus, + pcierc->sub_bus), DWORD); + qcom_pcie_scan_bus(pcierc, pcierc->sec_bus); + } else { + qcom_dw_pcie_cfg_dev(pcierc, pcierc->bdf, + PCIE1_IO_ADDR, PCIE1_MEM_ADDR); + } + } +} + +void dw_pcie_setup_rc(struct pcierc_dwc_t *pcie) +{ + int val; + pcie_rc_config_t *pcierc = pcie->rc_cfg; + /* + * Enable DBI read-only registers for writing/updating configuration. + * Write permission gets disabled towards the end of this function. + */ + dw_pcie_dbi_rd_wr_enable(pcie, ENABLE); + + val = read32(pcierc->dbi_base + PCIE_PORT_LINK_CONTROL); + /* Set the number of lanes */ + val &= ~PORT_LINK_MODE_MASK; + + switch (pcierc->lanes) { + case 1: + val |= PORT_LINK_MODE_1_LANES; + break; + case 2: + val |= PORT_LINK_MODE_2_LANES; + break; + case 4: + val |= PORT_LINK_MODE_4_LANES; + break; + case 8: + val |= PORT_LINK_MODE_8_LANES; + break; + default: + printk(BIOS_INFO, "num-lanes %u: invalid value\n", + pcierc->lanes); + return; + } + + write32(pcierc->dbi_base + PCIE_PORT_LINK_CONTROL, val); + + /* Set link width speed control register */ + val = read32(pcierc->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); + val &= ~PORT_LOGIC_LINK_WIDTH_MASK; + + switch (pcierc->lanes) { + case 1: + val |= PORT_LOGIC_LINK_WIDTH_1_LANES; + break; + case 2: + val |= PORT_LOGIC_LINK_WIDTH_2_LANES; + break; + case 4: + val |= PORT_LOGIC_LINK_WIDTH_4_LANES; + break; + case 8: + val |= PORT_LOGIC_LINK_WIDTH_8_LANES; + break; + default: + printk(BIOS_INFO, "invalid option\n"); + return; + } + + write32(pcierc->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL, val); + + /* + * Need to confirm before commit + */ + write32(pcierc->dbi_base + PCI_BASE_ADDRESS_0, 0x00000004); + write32(pcierc->dbi_base + PCI_BASE_ADDRESS_1, 0x0); + + val = read32(pcierc->dbi_base + PCI_INTERRUPT_LINE); + val &= 0xffff00ff; + val |= 0x00000100; + write32(pcierc->dbi_base+PCI_INTERRUPT_LINE, val); + + /* Setup bus numbers */ + val = read32(pcierc->dbi_base + PCI_PRIMARY_BUS); + val &= 0xff000000; + val |= 0x00ff0100; + write32(pcierc->dbi_base + PCI_PRIMARY_BUS, val); + + /* Setup command register */ + val = read32(pcierc->dbi_base + PCI_COMMAND); + val &= 0xffff0000; + + /* Enable BUS master and Memory Space Enable bits*/ + val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_SERR; + write32(pcierc->dbi_base + PCI_COMMAND, val); + + /* Disable SMMU */ + write32(pcierc->parf + PCIE1_BDF_TO_SID_CFG, 0x1); + + /* Configure ATU for outbound accesses */ + qcom_dw_pcie_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_MEM, pcierc->mem.phys_start, + pcierc->mem.bus_start, pcierc->mem.size); + + /* Program correct class for RC */ + qcom_dw_pcie_wr_own_config(pcie, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); + + /* Better disable write permission right after the update */ + val = read32(pcierc->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); + val |= PORT_LOGIC_SPEED_CHANGE; + write32(pcierc->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL, val); + + dw_pcie_dbi_rd_wr_enable(pcie, DISABLE); +} + +static void qcom_qmp_phy_configure_lane(void *base, + const struct qcom_qmp_phy_init_tbl tbl[], + int num, uint8_t ln_mask) +{ + int i; + const struct qcom_qmp_phy_init_tbl *t = tbl; + + for (i = 0; i < num; i++, t++) { + if (!(t->lane_mask & ln_mask)) + continue; + write32(base + t->offset, t->val); + } +} + +static void qcom_qmp_phy_configure(void *base, + const struct qcom_qmp_phy_init_tbl tbl[], + int num) +{ + qcom_qmp_phy_configure_lane(base, tbl, num, 0xff); +} + +static int qcom_qmp_phy_power_on(qmp_phy_cfg_t *qphy) +{ + int ret; + long lock_us; + + write32(qphy->qmp_phy_base + QPHY_PCS_PWR_DWN_CNTRL, 0x01); + + /* Serdes configuration */ + qcom_qmp_phy_configure(qphy->serdes, + qphy->serdes_tbl, qphy->serdes_tbl_num); + + /* Tx, Rx, and PCS configurations */ + qcom_qmp_phy_configure_lane(qphy->tx0, qphy->tx_tbl, qphy->tx_tbl_num, 1); + qcom_qmp_phy_configure_lane(qphy->tx0, qphy->tx_tbl_sec, qphy->tx_tbl_num_sec, 1); + qcom_qmp_phy_configure_lane(qphy->tx1, qphy->tx_tbl, qphy->tx_tbl_num, 2); + qcom_qmp_phy_configure_lane(qphy->tx1, qphy->tx_tbl_sec, qphy->tx_tbl_num_sec, 2); + qcom_qmp_phy_configure_lane(qphy->rx0, qphy->rx_tbl, qphy->rx_tbl_num, 1); + qcom_qmp_phy_configure_lane(qphy->rx0, qphy->rx_tbl_sec, qphy->rx_tbl_num_sec, 1); + qcom_qmp_phy_configure_lane(qphy->rx1, qphy->rx_tbl, qphy->rx_tbl_num, 2); + qcom_qmp_phy_configure_lane(qphy->rx1, qphy->rx_tbl_sec, qphy->rx_tbl_num_sec, 2); + qcom_qmp_phy_configure(qphy->pcs, qphy->pcs_tbl, qphy->pcs_tbl_num); + qcom_qmp_phy_configure(qphy->pcs, qphy->pcs_tbl_sec, qphy->pcs_tbl_num_sec); + qcom_qmp_phy_configure(qphy->pcs_misc, qphy->pcs_misc_tbl, qphy->pcs_misc_tbl_num); + qcom_qmp_phy_configure(qphy->pcs_misc, qphy->pcs_misc_tbl_sec, qphy->pcs_tbl_num_sec); + + /* perform software reset of PCS/Serdes */ + write32(qphy->pcs + QPHY_SW_RESET, 0x00); + /* start PCS/Serdes to operation mode */ + write32(qphy->pcs + QPHY_START_CTRL, 0x03); + + /* Pull out PHY from POWER DOWN state.*/ + write32(qphy->pcs + QPHY_PCS_PWR_DWN_CNTRL, 0x03); + /* + * Wait for PHY initialization to be done + * PCS_STATUS: wait for 1ms for PHY STATUS; + * SW can continuously check for PHYSTATUS = 1.b0. + */ + lock_us = wait_us(1000, + !(read32(qphy->qmp_phy_base + + QPHY_PCS_STATUS) & QPHY_PCS_STATUS)); + if (!lock_us) + printk(BIOS_ERR, "ERROR: QMP PHY PLL LOCK fails:\n"); + else + printk(BIOS_DEBUG, "QPHY Initialized... %ldus\n", lock_us); + + /* Set pipe clock source */ + ret = clock_configure_mux(GCC_PCIE_1_PIPE_MUXR, PCIE_1_PIPE_SRC_SEL); + if (ret) { + printk(BIOS_ERR, " %s(): Pipe clock enable failed\n", __func__); + return -1; + } + + /* Enable pipe clock */ + ret = clock_enable_pcie(PCIE_1_PIPE_CLK); + if (ret) { + printk(BIOS_ERR, "Failed to enable pipe clock\n"); + return -1; + } + + return 0; +} + +/* + * Configure ATU for outbound accesses + */ +static void qcom_dw_pcie_setup_iatu(struct pcierc_dwc_t *pcie) +{ + pcie_rc_config_t *pcierc = pcie->rc_cfg; + uint64_t ep_config_base, ep_config_size; + + ep_config_base = (uint64_t)pcierc->cfg_base; + ep_config_size = pcierc->cfg_size; + + /* Read the config space of Bus 1 */ + qcom_dw_pcie_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_CFG0, + ep_config_base, + (1 << 24), ep_config_size); +} + +static void reset_qmp_phy(struct pcierc_dwc_t *pcie) +{ + /* reset the PHY*/ + clock_reset_bcr(pcie->rc_cfg->qmp_phy_bcr, 1); + + /* clear the reset*/ + clock_reset_bcr(pcie->rc_cfg->qmp_phy_bcr, 0); + udelay(100); +} + +static void reset_pcie_core(struct pcierc_dwc_t *pcie) +{ + /* reset the PCIe core*/ + clock_reset_bcr(pcie->rc_cfg->pcie1_bcr, 1); + + udelay(1200); + + /* clear the reset */ + clock_reset_bcr(pcie->rc_cfg->pcie1_bcr, 0); +} + +/* + * Assign bridge window + */ +static void qcom_pcie_assign_resources(struct pcierc_dwc_t *pcie) +{ + uint32_t l; + + /* Set up the top and bottom of the PCI Memory segment for this bus */ + l = (PCIE1_MEM_ADDR >> 16) & 0xfff0; + l |= PCIE1_MEM_END & 0xfff00000; + + printk(BIOS_INFO, "bridge window size 0x%x\n", l); + + qcom_dw_pcie_wr_own_config(pcie, PCI_MEMORY_BASE, DWORD, l); +} + +static int qcom_pcie_enable(struct pcierc_dwc_t *pcie) +{ + int val, ret; + uint32_t clk; + pcie_rc_config_t *pcierc = pcie->rc_cfg; + qmp_phy_cfg_t *qmp_phy = pcie->qmp_phy_cfg; + + /* assert PCIe reset link to keep EP in reset */ + qcom_ep_reset_assert(pcierc->perst); + + /* Enable gdsc before enable pcie clocks */ + ret = pcie_enable_gdsc(PCIE_1_GDSC); + if (ret) { + printk(BIOS_ERR, "Failed to enable gdsc\n"); + return -1; + } + + /* Enable pcie and PHY clocks */ + for (clk = PCIE_1_SLV_Q2A_AXI_CLK; clk < PCIE_CLK_COUNT - 3; clk++) { + ret = clock_enable_pcie(clk); + if (ret) { + printk(BIOS_ERR, "Failed to enable %d clock\n", clk); + return -1; + } + } + + reset_pcie_core(pcie); + + /* configure PCIe to RC mode */ + write32(pcierc->parf + PCIE1_PARF_DEVICE_TYPE, DEVICE_TYPE_RC); + + /* enable PCIe clocks and resets */ + val = read32(pcierc->parf + PCIE1_PARF_PHY_CTRL); + val &= ~BIT(0); + write32(pcierc->parf + PCIE1_PARF_PHY_CTRL, val); + + /* change DBI base address */ + write32(pcierc->parf + PCIE1_PARF_DBI_BASE_ADDR, 0); + + /* MAC PHY_POWERDOWN MUX DISABLE : Need to confirm */ + val = read32(pcierc->parf + PCIE1_PARF_SYS_CTRL); + val &= ~BIT(29); + write32(pcierc->parf + PCIE1_PARF_SYS_CTRL, val); + + /*Recommended to set when MHI isn't needed */ + val = read32(pcierc->parf + PCIE1_PARF_MHI_CLOCK_RESET_CTRL); + val |= BIT(4); + write32(pcierc->parf + PCIE1_PARF_MHI_CLOCK_RESET_CTRL, val); + + reset_qmp_phy(pcie); + + /* Initialize QMP PHY */ + ret = qcom_qmp_phy_power_on(qmp_phy); + if (ret) { + printk(BIOS_EMERG, "PHY init failed\n"); + return -1; + } + + dw_pcie_setup_rc(pcie); + + /* de-assert PCIe reset link to bring EP out of reset */ + qcom_ep_reset_deassert(pcierc->perst); + + /* establisth the link */ + ret = qcom_pcie_dw_link_up(pcie); + if (ret) { + printk(BIOS_ERR, "Link init failed\n"); + return -1; + } + return 0; +} + +void setup_pcie_host(void) +{ + int ret; + int bus = 0; + struct pcierc_dwc_t pcierc; + + pcierc.rc_cfg = &pcie_host; + pcierc.qmp_phy_cfg = &pcie1_qmp_phy_3x2; + + printk(BIOS_INFO, "Setup PCIe in RC mode\n"); + + /* Configure PERST gpio */ + configure_pcie_gpios(pcie_host.perst); + + ret = qcom_pcie_enable(&pcierc); + if(!ret) + printk(BIOS_NOTICE, "PCIe enumerated succussfully..\n"); + else + printk(BIOS_EMERG, "Failed to enable PCIe\n"); + + /* Scan the bus */ + qcom_pcie_scan_bus(&pcierc, bus); + + /* program and enable address translation region 0 (dev config addr space) */ + qcom_dw_pcie_setup_iatu(&pcierc); + + qcom_pcie_assign_resources(&pcierc); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/53902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631 Gerrit-Change-Number: 53902 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: sc7180: Add backlight support for sn65dsi86bridge
by Ravi kumar (Code Review) 07 May '21

07 May '21

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney. Hello Shelley Chen, build bot (Jenkins), Julius Werner, mturney mturney, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52663 to look at the new patch set (#4). Change subject: sc7180: Add backlight support for sn65dsi86bridge ...................................................................... sc7180: Add backlight support for sn65dsi86bridge Add backlight support in sn65dsi86bridge through the AUX channel using eDP DPCD registers. Change-Id: Ie700080f1feabe2d3397c38088a64cff27bfbe55 Signed-off-by: Vinod Polimera <vpolimer(a)codeaurora.org> --- M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h M src/mainboard/google/trogdor/Kconfig M src/mainboard/google/trogdor/mainboard.c 4 files changed, 36 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/52663/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie700080f1feabe2d3397c38088a64cff27bfbe55 Gerrit-Change-Number: 52663 Gerrit-PatchSet: 4 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: herobrine: Enable macronix SPI config
by Ravi kumar (Code Review) 07 May '21

07 May '21

Attention is currently required from: Ravi kumar, Sajida Bhanu, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Sajida Bhanu, mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50583 to look at the new patch set (#33). Change subject: herobrine: Enable macronix SPI config ...................................................................... herobrine: Enable macronix SPI config Enable macronix SPI config on herobrine board. Change-Id: I505ee95d9f2ca16baf244135b3e2e8fe72f93491 Signed-off-by: Shaik Sajida Bhanu <sbhanu(a)codeaurora.org> --- M src/mainboard/google/herobrine/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/50583/33 -- To view, visit https://review.coreboot.org/c/coreboot/+/50583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I505ee95d9f2ca16baf244135b3e2e8fe72f93491 Gerrit-Change-Number: 50583 Gerrit-PatchSet: 33 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: sc7280: Reserve wlan & wpss dram memory regions
by Ravi kumar (Code Review) 07 May '21

07 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50587 to look at the new patch set (#31). Change subject: sc7280: Reserve wlan & wpss dram memory regions ...................................................................... sc7280: Reserve wlan & wpss dram memory regions Change-Id: Ic98b5d08a0a7b3f772582bf85d94f901a7c53010 Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> --- M src/soc/qualcomm/common/include/soc/symbols_common.h M src/soc/qualcomm/sc7280/memlayout.ld M src/soc/qualcomm/sc7280/soc.c 3 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/50587/31 -- To view, visit https://review.coreboot.org/c/coreboot/+/50587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic98b5d08a0a7b3f772582bf85d94f901a7c53010 Gerrit-Change-Number: 50587 Gerrit-PatchSet: 31 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2021