coreboot-gerrit May 2021

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Change in coreboot[master]: vc/amd/pi/00660F01: Remove unused code and directory
by Michał Żygowski (Code Review) 11 May '21

11 May '21

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54056 ) Change subject: vc/amd/pi/00660F01: Remove unused code and directory ...................................................................... vc/amd/pi/00660F01: Remove unused code and directory This is some leftover omitted during 00660F01 removal, since corresponding CPU and northbridge code is not present in the tree already. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ib7ccbc088766b5a4f59c47bd48790c6a2af8ca61 --- D src/vendorcode/amd/pi/00660F01/AGESA.h D src/vendorcode/amd/pi/00660F01/AMD.h D src/vendorcode/amd/pi/00660F01/Dispatcher.h D src/vendorcode/amd/pi/00660F01/Include/Filecode.h D src/vendorcode/amd/pi/00660F01/Include/GeneralServices.h D src/vendorcode/amd/pi/00660F01/Include/Ids.h D src/vendorcode/amd/pi/00660F01/Include/IdsPerf.h D src/vendorcode/amd/pi/00660F01/Include/Options.h D src/vendorcode/amd/pi/00660F01/Include/PlatformMemoryConfiguration.h D src/vendorcode/amd/pi/00660F01/Include/Topology.h D src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h D src/vendorcode/amd/pi/00660F01/Proc/CPU/Feature/cpuCacheInit.h D src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuEarlyInit.h D src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuLateInit.h D src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h D src/vendorcode/amd/pi/00660F01/Proc/CPU/heapManager.h D src/vendorcode/amd/pi/00660F01/Proc/Common/AmdFch.h D src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/AcpiLib.h D src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchBiosRamUsage.h D src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h D src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchDef.h D src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchLib.c D src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchPeLib.c D src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/MemLib.c D src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/PciLib.c D src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h D src/vendorcode/amd/pi/00660F01/Proc/Fch/FchPlatform.h D src/vendorcode/amd/pi/00660F01/Proc/Fch/Kern/KernFch.h D src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.c D src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h D src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspDirectory.h D src/vendorcode/amd/pi/00660F01/binaryPI/OptionsIds.h D src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc 33 files changed, 0 insertions(+), 18,238 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/54056/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/54056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7ccbc088766b5a4f59c47bd48790c6a2af8ca61 Gerrit-Change-Number: 54056 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/octopus/var/phaser: add audio codec into SSFC support for P...
by Kevin Chang (Code Review) 11 May '21

11 May '21

Attention is currently required from: Henry Sun, Paul Menzel, Marco Chen. Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52878 ) Change subject: mb/google/octopus/var/phaser: add audio codec into SSFC support for Phaser ...................................................................... Patch Set 8: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52878/comment/d17aa352_aa05695f PS7, Line 7: mb/google/octopus/variant/phaser: add audio codec into SSFC support for Phaser > mb/google/octopus/var/phaser Update in patchset 8, correct wording. https://review.coreboot.org/c/coreboot/+/52878/comment/9da89939_66652732 PS7, Line 9: RT5682I > RT5682 Update in patchset 8. https://review.coreboot.org/c/coreboot/+/52878/comment/545094bb_1e375ace PS7, Line 9: define GPIO_137 : for audio codec IRQ using. : > define GPIO_137 in the override_table for SSFC framework to adjust IRQ configuration. Update in patchset 8, correct wording. File src/mainboard/google/octopus/variants/phaser/overridetree.cb: https://review.coreboot.org/c/coreboot/+/52878/comment/60887303_34099127 PS7, Line 119: Realtek RT5682I > Just for consistency, please have desc as "Realtek RT5682" Update in patchset 8. -- To view, visit https://review.coreboot.org/c/coreboot/+/52878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I202f71f57ad2db84fb90b52f9ffd7a1fd05494a3 Gerrit-Change-Number: 52878 Gerrit-PatchSet: 8 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)chromium.org> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tiffany Li <tiffany.li(a)lcfc.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Attention: Marco Chen <marcochen(a)chromium.org> Gerrit-Comment-Date: Tue, 11 May 2021 09:26:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marco Chen <marcochen(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/octopus/var/phaser: add audio codec into SSFC support for P...
by Kevin Chang (Code Review) 11 May '21

11 May '21

Attention is currently required from: Kevin Chang, Henry Sun, Paul Menzel, Marco Chen. Hello build bot (Jenkins), Henry Sun, Marco Chen, Marco Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52878 to look at the new patch set (#8). Change subject: mb/google/octopus/var/phaser: add audio codec into SSFC support for Phaser ...................................................................... mb/google/octopus/var/phaser: add audio codec into SSFC support for Phaser Add audio codec module RT5682 in project and define GPIO_137 in the override_table for SSFC framework to adjust IRQ configuration. BUG=b:182221327 BRANCH=octopus TEST=adjust SSFC value of CBI to select RT5682I or DA7219 then check whether device tree is updated correspondingly by disabling unselected one. Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I202f71f57ad2db84fb90b52f9ffd7a1fd05494a3 --- M src/mainboard/google/octopus/Kconfig.name M src/mainboard/google/octopus/variants/phaser/gpio.c M src/mainboard/google/octopus/variants/phaser/overridetree.cb 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/52878/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/52878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I202f71f57ad2db84fb90b52f9ffd7a1fd05494a3 Gerrit-Change-Number: 52878 Gerrit-PatchSet: 8 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)chromium.org> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tiffany Li <tiffany.li(a)lcfc.corp-partner.google.com> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marco Chen <marcochen(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer/var/volteer: add specific wifi SAR for volta
by Sheng-Liang Pan (Code Review) 11 May '21

11 May '21

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54051 to look at the new patch set (#2). Change subject: mb/google/volteer/var/volteer: add specific wifi SAR for volta ...................................................................... mb/google/volteer/var/volteer: add specific wifi SAR for volta volta will use different wifi SAR from voxel. Using clamshell mode of fw config to decide to load volta wifi sar. BUG=b:184820057 TEST=build and verify wifi power as expect. Cq-Depend: chrome-internal:3824093 Signed-off-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: I000aefca63346c70556688f232ca54360b3badef --- M src/mainboard/google/volteer/Kconfig.name M src/mainboard/google/volteer/variants/voxel/Makefile.inc A src/mainboard/google/volteer/variants/voxel/variant.c 3 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/54051/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I000aefca63346c70556688f232ca54360b3badef Gerrit-Change-Number: 54051 Gerrit-PatchSet: 2 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/octopus/variant/phaser: add audio codec into SSFC support f...
by Marco Chen (Code Review) 11 May '21

11 May '21

Attention is currently required from: Kevin Chang, Henry Sun, Paul Menzel, Marco Chen. Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52878 ) Change subject: mb/google/octopus/variant/phaser: add audio codec into SSFC support for Phaser ...................................................................... Patch Set 7: Code-Review+1 (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52878/comment/6132e2ce_e157cba6 PS7, Line 7: mb/google/octopus/variant/phaser: add audio codec into SSFC support for Phaser mb/google/octopus/var/phaser https://review.coreboot.org/c/coreboot/+/52878/comment/d57895a8_016b3165 PS7, Line 9: RT5682I RT5682 https://review.coreboot.org/c/coreboot/+/52878/comment/1eb7be0a_ba4be227 PS7, Line 9: define GPIO_137 : for audio codec IRQ using. : define GPIO_137 in the override_table for SSFC framework to adjust IRQ configuration. File src/mainboard/google/octopus/variants/phaser/overridetree.cb: https://review.coreboot.org/c/coreboot/+/52878/comment/c7ad19f9_90c6a448 PS7, Line 119: Realtek RT5682I Just for consistency, please have desc as "Realtek RT5682" -- To view, visit https://review.coreboot.org/c/coreboot/+/52878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I202f71f57ad2db84fb90b52f9ffd7a1fd05494a3 Gerrit-Change-Number: 52878 Gerrit-PatchSet: 7 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)chromium.org> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tiffany Li <tiffany.li(a)lcfc.corp-partner.google.com> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marco Chen <marcochen(a)chromium.org> Gerrit-Comment-Date: Tue, 11 May 2021 09:07:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: set dram dma property
by Rex-BC Chen (Code Review) 11 May '21

11 May '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54052 ) Change subject: soc/mediatek/mt8195: set dram dma property ...................................................................... soc/mediatek/mt8195: set dram dma property Set dram dma to be non-cacheable to load blob correctly. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0 --- M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/mmu_operations.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/54052/1 diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 67ceed3..a78b7193 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -27,6 +27,10 @@ romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/pll.c pll.c +romstage-y += ../common/dram_init.c +romstage-y += ../common/dramc_param.c +romstage-y += ../common/memory.c ../common/memory_test.c +romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += scp.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c diff --git a/src/soc/mediatek/mt8195/mmu_operations.c b/src/soc/mediatek/mt8195/mmu_operations.c index 7018093..063402c 100644 --- a/src/soc/mediatek/mt8195/mmu_operations.c +++ b/src/soc/mediatek/mt8195/mmu_operations.c @@ -29,3 +29,11 @@ MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); dsb(); } + +/* mtk_soc_after_dram is called in romstage */ +void mtk_soc_after_dram(void) +{ + mmu_config_range(_dram_dma, REGION_SIZE(dram_dma), + NONSECURE_UNCACHED_MEM); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/54052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0 Gerrit-Change-Number: 54052 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/var/volteer: add specific wifi SAR for volta
by Sheng-Liang Pan (Code Review) 11 May '21

11 May '21

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54051 ) Change subject: mb/google/volteer/var/volteer: add specific wifi SAR for volta ...................................................................... mb/google/volteer/var/volteer: add specific wifi SAR for volta volta will use different wifi SAR from voxel. Using clamshell mode of fw config to decide to load volta wifi sar. BUG=b:184820057 TEST=build and verify wifi power as expect. Signed-off-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: I000aefca63346c70556688f232ca54360b3badef --- M src/mainboard/google/volteer/Kconfig.name M src/mainboard/google/volteer/variants/voxel/Makefile.inc A src/mainboard/google/volteer/variants/voxel/variant.c 3 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/54051/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 8777994..c666f30 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -75,6 +75,7 @@ config BOARD_GOOGLE_VOXEL bool "-> Voxel" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select SOC_INTEL_CSE_LITE_SKU config BOARD_GOOGLE_BOLDAR diff --git a/src/mainboard/google/volteer/variants/voxel/Makefile.inc b/src/mainboard/google/volteer/variants/voxel/Makefile.inc index b0bfc56..e34a40b 100644 --- a/src/mainboard/google/volteer/variants/voxel/Makefile.inc +++ b/src/mainboard/google/volteer/variants/voxel/Makefile.inc @@ -5,3 +5,4 @@ romstage-y += memory.c ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/volteer/variants/voxel/variant.c b/src/mainboard/google/volteer/variants/voxel/variant.c new file mode 100644 index 0000000..70fa3a0 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voxel/variant.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fw_config.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + + if (fw_config_probe(FW_CONFIG(TABLETMODE, TABLETMODE_DISABLED))) + filename = "wifi_sar-volta.hex"; + + return filename; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/54051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I000aefca63346c70556688f232ca54360b3badef Gerrit-Change-Number: 54051 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP: soc/mediatek/mt8192: add apusys init flow
by Chien-Chih Tseng (Code Review) 11 May '21

11 May '21

Chien-Chih Tseng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48622 ) Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ...................................................................... WIP: soc/mediatek/mt8192: add apusys init flow Signed-off-by: Chien-Chih Tseng <chien-chih.tseng(a)mediatek.com> Change-Id: If05a8af1a2f96598adcf70e15003e4f5dc94e337 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/apusys.c A src/soc/mediatek/mt8192/include/soc/apusys.h M src/soc/mediatek/mt8192/soc.c 4 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/48622/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc old mode 100644 new mode 100755 index c01d716..0b23296 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -54,6 +54,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += devapc.c ramstage-y += mcupm.c +ramstage-y += apusys.c ramstage-y += soc.c ramstage-y += sspm.c ramstage-y += ufs.c diff --git a/src/soc/mediatek/mt8192/apusys.c b/src/soc/mediatek/mt8192/apusys.c new file mode 100755 index 0000000..605f1c9 --- /dev/null +++ b/src/soc/mediatek/mt8192/apusys.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <soc/apusys.h> +#include <soc/mtlib_common.h> + +#define INFRA2APU_SRAM_PROT_EN (INFRACFG_AO_BASE + 0xe98) +#define APUSYS_MBOX (0x19000000) + +void apusys_init(void) +{ + write32((void *)INFRA2APU_SRAM_PROT_EN, + read32((void *)INFRA2APU_SRAM_PROT_EN) & (~0xc0000000)); + write32((void *)(APUSYS_MBOX + 0x0b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x1b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x2b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x3b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x4b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x5b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x6b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x7b0), 0x00010001); + + printk(BIOS_INFO, "INFRA2APU_SRAM_PROT_EN = 0x%x\n", + read32((void *)INFRA2APU_SRAM_PROT_EN)); + printk(BIOS_INFO, "0x190000b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x0b0))); + printk(BIOS_INFO, "0x190001b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x1b0))); + printk(BIOS_INFO, "0x190002b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x2b0))); + printk(BIOS_INFO, "0x190003b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x3b0))); + printk(BIOS_INFO, "0x190004b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x4b0))); + printk(BIOS_INFO, "0x190005b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x5b0))); + printk(BIOS_INFO, "0x190006b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x6b0))); + printk(BIOS_INFO, "0x190007b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x7b0))); +} diff --git a/src/soc/mediatek/mt8192/include/soc/apusys.h b/src/soc/mediatek/mt8192/include/soc/apusys.h new file mode 100755 index 0000000..389d1e8 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/apusys.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_APUSYS_H +#define SOC_MEDIATEK_MT8192_APUSYS_H + +#include <soc/addressmap.h> +#include <types.h> + +void apusys_init(void); +#endif /* SOC_MEDIATEK_MT8192_APUSYS_H */ diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c old mode 100644 new mode 100755 index 883f4dc..8c16906 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -4,10 +4,12 @@ #include <soc/devapc.h> #include <soc/emi.h> #include <soc/mcupm.h> +#include <soc/apusys.h> #include <soc/mmu_operations.h> #include <soc/sspm.h> #include <soc/ufs.h> #include <symbols.h> +#include <console/console.h> static void soc_read_resources(struct device *dev) { @@ -17,6 +19,7 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + apusys_init(); dapc_init(); mcupm_init(); sspm_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/48622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If05a8af1a2f96598adcf70e15003e4f5dc94e337 Gerrit-Change-Number: 48622 Gerrit-PatchSet: 1 Gerrit-Owner: Chien-Chih Tseng <chien-chih.tseng(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/crossgcc: Update gcc to 11.1
by Patrick Georgi (Code Review) 11 May '21

11 May '21

Attention is currently required from: Werner Zeh, Harshit Sharma. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54050 ) Change subject: util/crossgcc: Update gcc to 11.1 ...................................................................... Patch Set 1: (1 comment) File util/crossgcc/patches/gcc-11.1.0_asan_shadow_offset_callback.patch: PS1: Werner, Harshit: I had to adapt the patch a bit to fit into the new GCC options handling scheme. Please take a look. -- To view, visit https://review.coreboot.org/c/coreboot/+/54050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdee2a8beedd109ee1f0eef6f32f7accbf66674b Gerrit-Change-Number: 54050 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Comment-Date: Tue, 11 May 2021 08:39:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/crossgcc: Update gcc to 11.1
by Patrick Georgi (Code Review) 11 May '21

11 May '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54050 ) Change subject: util/crossgcc: Update gcc to 11.1 ...................................................................... util/crossgcc: Update gcc to 11.1 Various fixes to gnat and the improved nds32 backend have been merged into gcc by now, so we don't need to carry those patches anymore. Change-Id: Icdee2a8beedd109ee1f0eef6f32f7accbf66674b Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-11.1.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-11.1.0_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-11.1.0_gnat.patch R util/crossgcc/patches/gcc-11.1.0_libcpp.patch R util/crossgcc/patches/gcc-11.1.0_libgcc.patch D util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch D util/crossgcc/patches/gcc-8.3.0_gnat_eh.patch D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch A util/crossgcc/sum/gcc-11.1.0.tar.xz.cksum D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum 11 files changed, 21 insertions(+), 21,479 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/54050/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/54050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdee2a8beedd109ee1f0eef6f32f7accbf66674b Gerrit-Change-Number: 54050 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit May 2021