coreboot-gerrit May 2021

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Change in coreboot[master]: mb/google/dedede/var/cret: Enable/disable LTE function based on FW_CO...
by Dtrain Hsu (Code Review) 11 May '21

11 May '21

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54057 ) Change subject: mb/google/dedede/var/cret: Enable/disable LTE function based on FW_CONFIG ...................................................................... mb/google/dedede/var/cret: Enable/disable LTE function based on FW_CONFIG Enable/disable LTE function based on LTE bit of FW_CONFIG. The LTE function settings are included GPIO settings, USB port settings and power off sequence. BUG=b:187797408 BRANCH=dedede TEST=Build and test the change on cret. Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: Ib926e99aaf9df433a7cff71180ee55431d69f718 --- M src/lib/Makefile.inc M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/cret/gpio.c M src/mainboard/google/dedede/variants/cret/overridetree.cb M src/mainboard/google/dedede/variants/cret/variant.c 5 files changed, 73 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/54057/1 diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 358035d..491312c 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -185,6 +185,7 @@ verstage-$(CONFIG_FW_CONFIG) += fw_config.c romstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +smm-$(CONFIG_FW_CONFIG) += fw_config.c bootblock-$(CONFIG_ESPI_DEBUG) += espi_debug.c verstage-$(CONFIG_ESPI_DEBUG) += espi_debug.c diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index f33995c..954e573 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -17,6 +17,10 @@ option RT1015_I2C 2 option RT1015P_AUTO 3 end + field LTE 11 + option LTE_ABSENT 0 + option LTE_PRESENT 1 + end end chip soc/intel/jasperlake diff --git a/src/mainboard/google/dedede/variants/cret/gpio.c b/src/mainboard/google/dedede/variants/cret/gpio.c index 3dd15ef..6d411d8 100644 --- a/src/mainboard/google/dedede/variants/cret/gpio.c +++ b/src/mainboard/google/dedede/variants/cret/gpio.c @@ -2,9 +2,59 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <fw_config.h> /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { + /* C12 : AP_PEN_DET_ODL ==> NC */ + PAD_NC(GPP_C12, UP_20K), + /* C18 : AP_I2C_EMR_SDA */ + PAD_NC(GPP_C18, NONE), + /* C19 : AP_I2C_EMR_SCL */ + PAD_NC(GPP_C19, NONE), + /* C22 : UART2_RTS_N ==> NC */ + PAD_NC(GPP_C22, UP_20K), + /* D12 : WCAM_RST_L ==> NC */ + PAD_NC(GPP_D12, NONE), + /* D14 : EN_PP1200_CAMERA ==> NC */ + PAD_NC(GPP_D14, NONE), + /* D15 : UCAM_RST_L ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D19 : WWAN_WLAN_COEX1 ==> NC */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 ==> NC */ + PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 ==> NC */ + PAD_NC(GPP_D21, NONE), + /* E0 : CLK_24M_UCAM ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E2 : CLK_24M_WCAM ==> NC */ + PAD_NC(GPP_E2, NONE), + /* H1 : EN_PP3300_SD_U ==> NC */ + PAD_NC(GPP_H1, NONE), + /* H6 : AP_I2C_CAM_SDA ==> NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL ==> NC */ + PAD_NC(GPP_H7, NONE), + /* G0 : SD_CMD ==> NC */ + PAD_NC(GPP_G0, NONE), + /* G1 : SD_DATA0 ==> NC */ + PAD_NC(GPP_G1, NONE), + /* G2 : SD_DATA1 ==> NC */ + PAD_NC(GPP_G2, NONE), + /* G3 : SD_DATA2 ==> NC */ + PAD_NC(GPP_G3, NONE), + /* G4 : SD_DATA3 ==> NC */ + PAD_NC(GPP_G4, NONE), + /* G5 : SD_CD_ODL ==> NC */ + PAD_NC(GPP_G5, UP_20K), + /* G6 : SD_CLK ==> NC */ + PAD_NC(GPP_G6, NONE), + /* G7 : SD_SDIO_WP ==> NC */ + PAD_NC(GPP_G7, NONE), +}; + +static const struct pad_config override_gpio_table_lte[] = { /* A10 : WWAN_EN */ PAD_CFG_GPO(GPP_A10, 1, PWROK), /* C12 : AP_PEN_DET_ODL ==> NC */ @@ -61,6 +111,11 @@ const struct pad_config *variant_override_gpio_table(size_t *num) { - *num = ARRAY_SIZE(override_gpio_table); - return override_gpio_table; + if (fw_config_probe(FW_CONFIG(LTE, LTE_PRESENT))) { + *num = ARRAY_SIZE(override_gpio_table_lte); + return override_gpio_table_lte; + } else { + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; + } } diff --git a/src/mainboard/google/dedede/variants/cret/overridetree.cb b/src/mainboard/google/dedede/variants/cret/overridetree.cb index 0cf3bdf..a1958b7 100644 --- a/src/mainboard/google/dedede/variants/cret/overridetree.cb +++ b/src/mainboard/google/dedede/variants/cret/overridetree.cb @@ -57,7 +57,9 @@ chip drivers/usb/acpi register "desc" = ""LTE"" register "type" = "UPC_TYPE_INTERNAL" - device usb 2.3 on end + device usb 2.3 on + probe LTE LTE_PRESENT + end end chip drivers/usb/acpi register "desc" = ""Camera (UFC)"" @@ -82,7 +84,9 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" register "enable_delay_ms" = "20" - device usb 3.3 on end + device usb 3.3 on + probe LTE LTE_PRESENT + end end end end diff --git a/src/mainboard/google/dedede/variants/cret/variant.c b/src/mainboard/google/dedede/variants/cret/variant.c index 2540fc7..2cc1c69 100644 --- a/src/mainboard/google/dedede/variants/cret/variant.c +++ b/src/mainboard/google/dedede/variants/cret/variant.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <baseboard/variants.h> #include <delay.h> +#include <fw_config.h> #include <gpio.h> static void power_off_lte_module(void) @@ -14,10 +15,8 @@ void variant_smi_sleep(u8 slp_typ) { - /* - * Once the FW_CONFIG is provisioned, power off LTE module only under - * the situation where it is stuffed. - */ - if (slp_typ == ACPI_S5) - power_off_lte_module(); + if (fw_config_probe(FW_CONFIG(LTE, LTE_PRESENT))) { + if (slp_typ == ACPI_S5) + power_off_lte_module(); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/54057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib926e99aaf9df433a7cff71180ee55431d69f718 Gerrit-Change-Number: 54057 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/intel/xeon_sp: add hardware error support (HEST)
by Lance Zhao (Code Review) 11 May '21

11 May '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Martin Roth, Johnny Lin, Rocky Phagura, Tim Wawrzynczak, David Hendricks, Angel Pons, Morgan Jang, Patrick Rudolph, Tim Chu. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52090 ) Change subject: src/intel/xeon_sp: add hardware error support (HEST) ...................................................................... Patch Set 14: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52090/comment/bb4b595c_d738d001 PS14, Line 19: : After boot to Linux, the following will show in dmesg: : HEST: Table parsing has been initialized Did we have seen an actual error entry had been created? -- To view, visit https://review.coreboot.org/c/coreboot/+/52090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If76b2af153616182cc053ca878f30fe056e9c8bd Gerrit-Change-Number: 52090 Gerrit-PatchSet: 14 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Rocky Phagura Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 11 May 2021 10:02:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation
by Michał Żygowski (Code Review) 11 May '21

11 May '21

Attention is currently required from: Arthur Heymans. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52922 ) Change subject: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > Thanks for splitting the patch. It's still a bit big, though. Took > me almost 3 hours to read through the first two platforms (fam14 > and fam15tn). The new functions look similar enough to extract > common code. What generally works well to get a break during > review is to add common code in one commit, and then update the > individual platforms one-by-one in separate commits. > I will try doing better in that matter. Thanks for the advise. > The code changes look sane, alas the comments and the commit > message don't. Without kowing further details, it seems possible > that the change of the granularity for the newer platforms results > in further problems. And this change is not even mentioned in the > commit message. > > IMHO, a simple comment like > > /* The upper half of each register provides the DRAM base/limit in 16MiB steps. */ > > could replace all the error-prone and redundant (considering that the > documentation is public) comments about bit offsets. That bit offset error is my bad, indeed it is documented in public BKDGs, although I thought it gives more readability. > > I did not see any overflowing shift operations. Though, it looks like > the original code treated the limit as exclusive, while it wasn't. I didn't dig that deep where the data is lost in limit calculation, but certainly on a 2GB platform, where the limit should be 0x7f000000, it calculated 0x78000000 (112MB lost). I have implemented it in a way that is more understandable to me and does less bitshifts than this: d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; But if we look closer the `// mask out DramMask [26:24] too` may be the case why we lose 112MB, that's exactly those 3 least significant bits. I will address your comments in a new patch -- To view, visit https://review.coreboot.org/c/coreboot/+/52922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b5c1df96c308ff50c8de104e213219a98f25e10 Gerrit-Change-Number: 52922 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 11 May 2021 09:59:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: src/intel/xeon_sp: add hardware error support (HEST)
by Lance Zhao (Code Review) 11 May '21

11 May '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Martin Roth, Johnny Lin, Rocky Phagura, Tim Wawrzynczak, David Hendricks, Angel Pons, Morgan Jang, Patrick Rudolph, Tim Chu. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52090 ) Change subject: src/intel/xeon_sp: add hardware error support (HEST) ...................................................................... Patch Set 14: (1 comment) File src/soc/intel/xeon_sp/uncore.c: https://review.coreboot.org/c/coreboot/+/52090/comment/d17ddf35_dfd6d3c8 PS14, Line 292: /* Reserve memory for Enhanced error logging */ : if (CONFIG(SOC_RAS_ELOG)) { : base_kb = cbmem_top_addr >> 10; : size_kb = CONFIG_ERROR_LOG_BUFFER_SIZE >> 10; : LOG_MEM_RESOURCE("elog_sts_blk", dev, index, base_kb, size_kb); : reserved_ram_resource(dev, index++, base_kb, size_kb); : elog_addr = cbmem_top_addr; : printk(BIOS_DEBUG, "%s elog_addr = %llx size = %x\n", : __func__, elog_addr, CONFIG_ERROR_LOG_BUFFER_SIZE); : } Would you like to update the map in line 148 as well to describe the elog area range? And what's the fail safe handling if ERROR_LOG_BUFFER_SIZE is too big? -- To view, visit https://review.coreboot.org/c/coreboot/+/52090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If76b2af153616182cc053ca878f30fe056e9c8bd Gerrit-Change-Number: 52090 Gerrit-PatchSet: 14 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Rocky Phagura Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 11 May 2021 09:57:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec: Add Star Labs ITE 8987E support
by Star Labs (Code Review) 11 May '21

11 May '21

Attention is currently required from: Andy Pont, Patrick Rudolph. Star Labs has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52797 ) Change subject: ec: Add Star Labs ITE 8987E support ...................................................................... Patch Set 8: (1 comment) File src/ec/starlabs/it8987/ec.c: https://review.coreboot.org/c/coreboot/+/52797/comment/55dbfb1a_3647c489 PS7, Line 16: IT8987E_ADDR > this address can be optioned from the struct device* passed in it8987_init. […] Resolved with patch set 8 -- To view, visit https://review.coreboot.org/c/coreboot/+/52797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1967f7c4a7e3cab714f22844bf36749e0c9652b6 Gerrit-Change-Number: 52797 Gerrit-PatchSet: 8 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 11 May 2021 09:48:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ec: Add Star Labs ITE 8987E support
by Star Labs (Code Review) 11 May '21

11 May '21

Attention is currently required from: Star Labs, Andy Pont. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52797 to look at the new patch set (#8). Change subject: ec: Add Star Labs ITE 8987E support ...................................................................... ec: Add Star Labs ITE 8987E support Support for Star Labs labtop series EC Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I1967f7c4a7e3cab714f22844bf36749e0c9652b6 --- A src/ec/starlabs/it8987/Kconfig A src/ec/starlabs/it8987/Makefile.inc A src/ec/starlabs/it8987/acpi/ac.asl A src/ec/starlabs/it8987/acpi/battery.asl A src/ec/starlabs/it8987/acpi/cmos.asl A src/ec/starlabs/it8987/acpi/ec.asl A src/ec/starlabs/it8987/acpi/hid.asl A src/ec/starlabs/it8987/acpi/keyboard.asl A src/ec/starlabs/it8987/acpi/lid.asl A src/ec/starlabs/it8987/acpi/thermal.asl A src/ec/starlabs/it8987/chip.h A src/ec/starlabs/it8987/ec.c A src/ec/starlabs/it8987/ec.h 13 files changed, 1,085 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/52797/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/52797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1967f7c4a7e3cab714f22844bf36749e0c9652b6 Gerrit-Change-Number: 52797 Gerrit-PatchSet: 8 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Star Labs <admin(a)starlabs.systems> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer/var/volteer: add specific wifi SAR for volta
by Sheng-Liang Pan (Code Review) 11 May '21

11 May '21

Attention is currently required from: Tim Wawrzynczak, Paul Fagerburg, YH Lin. Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54051 ) Change subject: mb/google/volteer/var/volteer: add specific wifi SAR for volta ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/54051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I000aefca63346c70556688f232ca54360b3badef Gerrit-Change-Number: 54051 Gerrit-PatchSet: 3 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Tue, 11 May 2021 09:36:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/volteer: add specific wifi SAR for volta
by Sheng-Liang Pan (Code Review) 11 May '21

11 May '21

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54051 to look at the new patch set (#3). Change subject: mb/google/volteer/var/volteer: add specific wifi SAR for volta ...................................................................... mb/google/volteer/var/volteer: add specific wifi SAR for volta volta will use different wifi SAR from voxel. Using clamshell mode of fw config to decide to load volta wifi sar. BUG=b:184820057 TEST=build and verify wifi power as expect. Cq-Depend: chrome-internal:3824093 Signed-off-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: I000aefca63346c70556688f232ca54360b3badef --- M src/mainboard/google/volteer/Kconfig.name M src/mainboard/google/volteer/variants/voxel/Makefile.inc A src/mainboard/google/volteer/variants/voxel/variant.c 3 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/54051/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/54051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I000aefca63346c70556688f232ca54360b3badef Gerrit-Change-Number: 54051 Gerrit-PatchSet: 3 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/amd/pi/00730F01: Use generic allocation functions for northbridge
by Michał Żygowski (Code Review) 11 May '21

11 May '21

Attention is currently required from: Nico Huber, Krystian Hebel, Kyösti Mälkki, Felix Held. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52926 ) Change subject: nb/amd/pi/00730F01: Use generic allocation functions for northbridge ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > It basically changes nothing, except the order the code is executed. […] Felix, 4 days passed without any action. Maybe we could proceed with submitting this patch series for PI 00730F01, since the coverage is 100% anyway? -- To view, visit https://review.coreboot.org/c/coreboot/+/52926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dd5e40bce513c5ba7f1d42a06e7ab0846666942 Gerrit-Change-Number: 52926 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 11 May 2021 09:33:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: set dram dma property
by Rex-BC Chen (Code Review) 11 May '21

11 May '21

Attention is currently required from: Hung-Te Lin. Hello Hung-Te Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54052 to look at the new patch set (#2). Change subject: soc/mediatek/mt8195: set dram dma property ...................................................................... soc/mediatek/mt8195: set dram dma property Set dram dma to be non-cacheable to load blob correctly. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0 --- M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/mmu_operations.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/54052/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0 Gerrit-Change-Number: 54052 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021