coreboot-gerrit May 2021

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Change in coreboot[master]: build system: Use more robust linker options
by Patrick Georgi (Code Review) 11 May '21

11 May '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54062 ) Change subject: build system: Use more robust linker options ...................................................................... build system: Use more robust linker options ld accepts a few of its options both as -single-dash and --double-dash options, but later versions (e.g. in binutils 2.36.1) seem to abandon that. Besides that the single-dash variant is also more risky because misspellings are interpreted as multiple single-letter options: -nostdllib is accepted, while --nostdllib returns an error. Change-Id: Icee24ba79df4df3b1a06af59f7ad268b01ba9e2f Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/54062/1 diff --git a/Makefile.inc b/Makefile.inc index ce70a30..71b52f9 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -489,7 +489,7 @@ # Disable style checks for now ADAFLAGS_common += -gnatyN -LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static +LDFLAGS_common := --gc-sections --nostdlib --nostartfiles --static # Workaround for RISC-V linker bug, merge back into above line when fixed. # https://sourceware.org/bugzilla/show_bug.cgi?id=27180 -- To view, visit https://review.coreboot.org/c/coreboot/+/54062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icee24ba79df4df3b1a06af59f7ad268b01ba9e2f Gerrit-Change-Number: 54062 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/prodrive/hermes: Disable ACPI S3 and S4 with SPS
by Michael Niewöhner (Code Review) 11 May '21

11 May '21

Attention is currently required from: wouter.eckhardt(a)prodrive-technologies.com, Guido Beyer @ Prodrive Technologies, Justin van Son, Patrick Rudolph, Christian Walter, Angel Pons, Stef van Os. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54058 ) Change subject: mb/prodrive/hermes: Disable ACPI S3 and S4 with SPS ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > What about doing that in a more generic way by adding !HAVE_SPS / HAVE_SPS as dependency to HAVE_ACP […] x11 boards could use that too, then -- To view, visit https://review.coreboot.org/c/coreboot/+/54058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d0fa8530e198e86415f92da6719d2fb0d2401ec Gerrit-Change-Number: 54058 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: wouter.eckhardt(a)prodrive-technologies.com Gerrit-Attention: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Attention: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Comment-Date: Tue, 11 May 2021 13:11:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/prodrive/hermes: Disable ACPI S3 and S4 with SPS
by Michael Niewöhner (Code Review) 11 May '21

11 May '21

Attention is currently required from: wouter.eckhardt(a)prodrive-technologies.com, Guido Beyer @ Prodrive Technologies, Justin van Son, Patrick Rudolph, Christian Walter, Angel Pons, Stef van Os. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54058 ) Change subject: mb/prodrive/hermes: Disable ACPI S3 and S4 with SPS ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: What about doing that in a more generic way by adding !HAVE_SPS / HAVE_SPS as dependency to HAVE_ACPI_RESUME and DISABLE_ACPI_HIBERNATE? -- To view, visit https://review.coreboot.org/c/coreboot/+/54058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d0fa8530e198e86415f92da6719d2fb0d2401ec Gerrit-Change-Number: 54058 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: wouter.eckhardt(a)prodrive-technologies.com Gerrit-Attention: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Attention: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Comment-Date: Tue, 11 May 2021 13:11:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/shuboz: update USB OC pin mapping
by chris wang (Code Review) 11 May '21

11 May '21

Attention is currently required from: Kane Chen, Chris Wang. chris wang has uploaded a new patch set (#10) to the change originally created by Kane Chen. ( https://review.coreboot.org/c/coreboot/+/51523 ) Change subject: mb/google/zork/var/shuboz: update USB OC pin mapping ...................................................................... mb/google/zork/var/shuboz: update USB OC pin mapping modify USB OC pin setting for Shuboz, as follow: usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0 usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0 usb_port_overcurrent_pin[2] = "USB_OC_NONE" # NONE usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1 BUG=b:182879559 BRANCH=zork TEST=emerge-zork coreboot, validate the OC mapping. Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/shuboz/variant.c 3 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/51523/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/51523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 Gerrit-Change-Number: 51523 Gerrit-PatchSet: 10 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/crossgcc: Update acpica to 20210331
by Patrick Georgi (Code Review) 11 May '21

11 May '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54061 ) Change subject: util/crossgcc: Update acpica to 20210331 ...................................................................... util/crossgcc: Update acpica to 20210331 Change-Id: Ic517a2b9c9b7122d2a65f67380d3ce368303d725 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20210331_iasl.patch D util/crossgcc/sum/acpica-unix2-20200717.tar.gz.cksum D util/crossgcc/sum/acpica-unix2-20200925.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20210331.tar.gz.cksum 5 files changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/54061/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index fc7883e..06d405d 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -39,7 +39,7 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.36.1 GDB_VERSION=9.2 -IASL_VERSION=20200925 +IASL_VERSION=20210331 PYTHON_VERSION=3.8.5 EXPAT_VERSION=2.2.9 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20200925_iasl.patch b/util/crossgcc/patches/acpica-unix2-20210331_iasl.patch similarity index 100% rename from util/crossgcc/patches/acpica-unix2-20200925_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20210331_iasl.patch diff --git a/util/crossgcc/sum/acpica-unix2-20200717.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20200717.tar.gz.cksum deleted file mode 100644 index 9bcfe83..0000000 --- a/util/crossgcc/sum/acpica-unix2-20200717.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -92b0177f36b5209e6a667808ca58ef7462c4a6c7 tarballs/acpica-unix2-20200717.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20200925.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20200925.tar.gz.cksum deleted file mode 100644 index fe1665e..0000000 --- a/util/crossgcc/sum/acpica-unix2-20200925.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -3d5fd9725e0229eb009685f4d356ffda488edc02 tarballs/acpica-unix2-20200925.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20210331.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20210331.tar.gz.cksum new file mode 100644 index 0000000..1aa77c2 --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20210331.tar.gz.cksum @@ -0,0 +1 @@ +1a4006727962daf63a181c853695ca69bdf7d541 tarballs/acpica-unix2-20210331.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/54061 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic517a2b9c9b7122d2a65f67380d3ce368303d725 Gerrit-Change-Number: 54061 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/crossgcc: Avoid complex filename sets
by Patrick Georgi (Code Review) 11 May '21

11 May '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54060 ) Change subject: util/crossgcc: Avoid complex filename sets ...................................................................... util/crossgcc: Avoid complex filename sets For some reasons I didn't want to debug further my shell doesn't accept bin/{foo,bar,baz} and complains about a missing file. Instead, cd into the directory and list the files individually. Change-Id: I042b2e45fded1b63551d8e65ead2a7bbbf96b1e7 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/crossgcc/buildgcc 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/54060/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index e2c633f..fc7883e 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -844,8 +844,9 @@ HOST="$HOST" CFLAGS="$CFLAGS" \ OPT_CFLAGS="-O -D_FORTIFY_SOURCE=2 -D COREBOOT_TOOLCHAIN_VERSION='\"coreboot toolchain v$CROSSGCC_VERSION\"' " \ $MAKE $JOBS CC="$(hostcc host)" iasl acpibin acpidump acpiexec acpihelp acpisrc acpixtract - rm -f "$DESTDIR$TARGETDIR/bin/{iasl,acpibin,acpidump,acpiexec,acpihelp,acpisrc,acpixtract}" || touch "$RDIR/.failed" - cp bin/{iasl,acpibin,acpidump,acpiexec,acpihelp,acpisrc,acpixtract} "$DESTDIR$TARGETDIR/bin" || touch "$RDIR/.failed" + mkdir -p "$DESTDIR$TARGETDIR/bin/" + (cd "$DESTDIR$TARGETDIR/bin" && rm -f iasl acpibin acpidump acpiexec acpihelp acpisrc acpixtract) || touch "$RDIR/.failed" + (cd bin && cp iasl acpibin acpidump acpiexec acpihelp acpisrc acpixtract "$DESTDIR$TARGETDIR/bin") || touch "$RDIR/.failed" } build_LLVM() { -- To view, visit https://review.coreboot.org/c/coreboot/+/54060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I042b2e45fded1b63551d8e65ead2a7bbbf96b1e7 Gerrit-Change-Number: 54060 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: enable DPTF functionality for brya
by Sumeet R Pawnikar (Code Review) 11 May '21

11 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52859 ) Change subject: mb/google/brya: enable DPTF functionality for brya ...................................................................... Patch Set 2: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52859/comment/c0e3db62_75af1411 PS2, Line 13: tested > What all did you test? sysfs entries for sensors, power limit values File src/mainboard/google/brya/variants/brya0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/52859/comment/0fb160a3_a4c44552 PS2, Line 11: # Default DPTF Policy for all Brya boards if not overridden > This comment is not true anymore (this isn't the baseboard) Ack https://review.coreboot.org/c/coreboot/+/52859/comment/d59567e8_bb6aec29 PS2, Line 23: > nit: remove a few of these tabs? Done https://review.coreboot.org/c/coreboot/+/52859/comment/e22cea89_6d0b6c1b PS2, Line 12: ## sensor information : register "options.tsr[0].desc" = ""DRAM"" : register "options.tsr[1].desc" = ""Charger"" : register "options.tsr[2].desc" = ""Ambient"" : : # TODO: below values are initial reference values only : ## Active Policy : register "policies.active" = "{ : [0] = { : .target = DPTF_CPU, : .thresholds = { : TEMP_PCT(85, 90), : TEMP_PCT(80, 80), : TEMP_PCT(75, 70), : } : }, : [1] = { : .target = DPTF_TEMP_SENSOR_2, : .thresholds = { : TEMP_PCT(70, 90), : TEMP_PCT(60, 80), : TEMP_PCT(50, 70), : } : } : }" : : ## Passive Policy : register "policies.passive" = "{ : [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), : [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), : [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), : [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000) : }" : : ## Critical Policy : register "policies.critical" = "{ : [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), : [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), : [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), : [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN) : }" : : register "controls.power_limits" = "{ : .pl1 = { : .min_power = 3000, : .max_power = 15000, : .time_window_min = 28 * MSECS_PER_SEC, : .time_window_max = 32 * MSECS_PER_SEC, : .granularity = 200, : }, : .pl2 = { : .min_power = 55000, : .max_power = 55000, : .time_window_min = 28 * MSECS_PER_SEC, : .time_window_max = 32 * MSECS_PER_SEC, : .granularity = 1000, : } : }" : : ## Charger Performance Control (Control, mA) : register "controls.charger_perf" = "{ : [0] = { 255, 1700 }, : [1] = { 24, 1500 }, : [2] = { 16, 1000 }, : [3] = { 8, 500 } : }" : : ## Fan Performance Control (Percent, Speed, Noise, Power) : register "controls.fan_perf" = "{ : [0] = { 90, 6700, 220, 2200, }, : [1] = { 80, 5800, 180, 1800, }, : [2] = { 70, 5000, 145, 1450, }, : [3] = { 60, 4900, 115, 1150, }, : [4] = { 50, 3838, 90, 900, }, : [5] = { 40, 2904, 55, 550, }, : [6] = { 30, 2337, 30, 300, }, : [7] = { 20, 1608, 15, 150, }, : [8] = { 10, 800, 10, 100, }, : [9] = { 0, 0, 0, 50, } : }" : : ## Fan options : register "options.fan.fine_grained_control" = "1" : register "options.fan.step_size" = "2" : : device generic 0 on end > indent this one more level Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0 Gerrit-Change-Number: 52859 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 11 May 2021 13:00:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/shuboz: update USB OC pin mapping
by chris wang (Code Review) 11 May '21

11 May '21

Attention is currently required from: Kane Chen, Chris Wang. chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51523 ) Change subject: mb/google/zork/var/shuboz: update USB OC pin mapping ...................................................................... Patch Set 9: (3 comments) File src/mainboard/google/zork/variants/baseboard/helpers.c: https://review.coreboot.org/c/coreboot/+/51523/comment/342da199_d25c5b61 PS6, Line 117: return !!extract_field(FW_CONFIG_MASK_LID_ANGLE_TABLET_MODE, FW_CONFIG_LID_ANGLE_TABLET_MODE_SHIFT); > line over 96 characters Please fix. File src/mainboard/google/zork/variants/shuboz/variant.c: https://review.coreboot.org/c/coreboot/+/51523/comment/54f345d4_73c7a8eb PS6, Line 7: uint32_t usb_oc_map_override [USB_PORT_COUNT] = { > space prohibited before open square bracket '[' Please fix. https://review.coreboot.org/c/coreboot/+/51523/comment/5e14882e_b8ad001b PS6, Line 55: } > adding a line without newline at end of file Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/51523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 Gerrit-Change-Number: 51523 Gerrit-PatchSet: 9 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Tue, 11 May 2021 12:57:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/metaknight: Update LTE USB port configuration
by Patrick Georgi (Code Review) 11 May '21

11 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52960 ) Change subject: mb/google/dedede/var/metaknight: Update LTE USB port configuration ...................................................................... mb/google/dedede/var/metaknight: Update LTE USB port configuration Update LTE USB port configuration at run-time after probing the firmware config. By default the concerned USB port takes the Type-A port configuration. BUG=b:186380807 BRANCH=dedede TEST=Build and boot to OS in metaknight Change-Id: I5ad5a1670adef54075923cf912fb41a1ce776155 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52960 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-by: Evan Green <evgreen(a)chromium.org> Reviewed-by: Raymond Wong <wongraymond(a)google.com> --- M src/mainboard/google/dedede/variants/metaknight/Makefile.inc M src/mainboard/google/dedede/variants/metaknight/overridetree.cb A src/mainboard/google/dedede/variants/metaknight/ramstage.c 3 files changed, 58 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified David Wu: Looks good to me, but someone else must approve Evan Green: Looks good to me, approved Raymond Wong: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/metaknight/Makefile.inc b/src/mainboard/google/dedede/variants/metaknight/Makefile.inc index 67a7ab2..2479ae9 100644 --- a/src/mainboard/google/dedede/variants/metaknight/Makefile.inc +++ b/src/mainboard/google/dedede/variants/metaknight/Makefile.inc @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only ramstage-y += gpio.c +ramstage-y += ramstage.c smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index 0052ec7..c8c56f9 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -69,23 +69,12 @@ chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi - register "desc" = ""LTE"" - register "type" = "UPC_TYPE_INTERNAL" - register "has_power_resource" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" - register "reset_off_delay_ms" = "10" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" - register "enable_delay_ms" = "20" - device usb 2.3 on - probe DB_PORTS DB_PORTS_LTE_HDMI - end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port"" + register "desc" = ""Multi-use Port"" register "type" = "UPC_TYPE_A" register "group" = "ACPI_PLD_GROUP(2, 2)" device usb 2.3 on probe DB_PORTS DB_PORTS_1A_HDMI + probe DB_PORTS DB_PORTS_LTE_HDMI end end chip drivers/usb/acpi @@ -99,18 +88,12 @@ device usb 2.6 on end end chip drivers/usb/acpi - register "desc" = ""LTE"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.3 on - probe DB_PORTS DB_PORTS_LTE_HDMI - end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port"" + register "desc" = ""Multi-use Port"" register "type" = "UPC_TYPE_USB3_A" register "group" = "ACPI_PLD_GROUP(2, 2)" device usb 3.3 on probe DB_PORTS DB_PORTS_1A_HDMI + probe DB_PORTS DB_PORTS_LTE_HDMI end end end diff --git a/src/mainboard/google/dedede/variants/metaknight/ramstage.c b/src/mainboard/google/dedede/variants/metaknight/ramstage.c new file mode 100644 index 0000000..3c8e196 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/ramstage.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <drivers/usb/acpi/chip.h> +#include <fw_config.h> +#include <gpio.h> +#include <soc/pci_devs.h> + +#define LTE_USB_PORT_ID 3 +#define LTE_USB_PORT_TYPE 2 +static struct acpi_gpio lte_reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17); +static struct acpi_gpio lte_enable_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10); + +static void update_xhci_devtree(void) +{ + struct device *xhci, *hub = NULL, *port = NULL; + struct drivers_usb_acpi_config *config; + + xhci = pcidev_path_on_root(PCH_DEVFN_XHCI); + if (!xhci) { + printk(BIOS_ERR, "%s: Could not locate XHCI device in DT\n", __func__); + return; + } + + while ((hub = dev_bus_each_child(xhci->link_list, hub)) != NULL) { + while ((port = dev_bus_each_child(hub->link_list, port)) != NULL) { + if (!port->chip_info || port->path.usb.port_id != LTE_USB_PORT_ID) + continue; + + if (!fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_LTE_HDMI))) + continue; + + config = port->chip_info; + config->type = UPC_TYPE_INTERNAL; + if (port->path.usb.port_type == LTE_USB_PORT_TYPE) { + config->has_power_resource = 1; + memcpy(&config->reset_gpio, &lte_reset_gpio, + sizeof(config->reset_gpio)); + config->reset_off_delay_ms = 10; + memcpy(&config->enable_gpio, &lte_enable_gpio, + sizeof(config->enable_gpio)); + config->enable_delay_ms = 20; + } + } + } +} + +void variant_devtree_update(void) +{ + update_xhci_devtree(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ad5a1670adef54075923cf912fb41a1ce776155 Gerrit-Change-Number: 52960 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raymond Wong <wongraymond(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede: Add a variant callback to update devicetree config
by Patrick Georgi (Code Review) 11 May '21

11 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52887 ) Change subject: mb/google/dedede: Add a variant callback to update devicetree config ...................................................................... mb/google/dedede: Add a variant callback to update devicetree config This callback is required to update the devicetree config at run-time after probing the firmware config. BUG=b:186380807 BRANCH=dedede TEST=Build and boot to OS in metaknight. Change-Id: I857211bfc4beb36ab225f3786c1707336a34aae9 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52887 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Evan Green <evgreen(a)chromium.org> Reviewed-by: Raymond Wong <wongraymond(a)google.com> --- M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h 2 files changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Evan Green: Looks good to me, approved Raymond Wong: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index 26afb69..6d544b5 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -40,10 +40,17 @@ gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); + variant_devtree_update(); + if (CONFIG(BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50)) mainboard_update_soc_chip_config(); } +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ +} + static void mainboard_dev_init(struct device *dev) { mainboard_ec_init(); diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index e7bfd86..a3dcd91 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -39,4 +39,7 @@ /* Allow each variants to customize SMI sleep flow. */ void variant_smi_sleep(u8 slp_typ); +/* Modify devictree settings during ramstage. */ +void variant_devtree_update(void); + #endif /*__BASEBOARD_VARIANTS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I857211bfc4beb36ab225f3786c1707336a34aae9 Gerrit-Change-Number: 52887 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raymond Wong <wongraymond(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: merged

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coreboot-gerrit May 2021