coreboot-gerrit May 2021

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Change in coreboot[master]: console: Allow VPD to disable an otherwise enabled coreboot console
by Patrick Georgi (Code Review) 17 May '21

17 May '21

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45208 ) Change subject: console: Allow VPD to disable an otherwise enabled coreboot console ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Elsewhere Julius requested a design doc, so I made CB:54385. Please Take A Look. -- To view, visit https://review.coreboot.org/c/coreboot/+/45208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f1f5c45e5ea889176d04e0db438ca2aa7c536ee Gerrit-Change-Number: 45208 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Greg Edelston <gredelston(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 17 May 2021 14:18:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add proposal to allow enabling serial console with a flag
by Patrick Georgi (Code Review) 17 May '21

17 May '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54385 ) Change subject: Documentation: Add proposal to allow enabling serial console with a flag ...................................................................... Documentation: Add proposal to allow enabling serial console with a flag BUG=b:172341184, b:151780766 Change-Id: If1b0efc55880095f9d5d6d6e448f2c8677d57ff5 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- A Documentation/technotes/2021-05-selectable-serial-console.md M Documentation/technotes/index.md 2 files changed, 137 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/54385/1 diff --git a/Documentation/technotes/2021-05-selectable-serial-console.md b/Documentation/technotes/2021-05-selectable-serial-console.md new file mode 100644 index 0000000..361be00 --- /dev/null +++ b/Documentation/technotes/2021-05-selectable-serial-console.md @@ -0,0 +1,136 @@ +# Selectable serial console + +## Problem statement + +The primary mechanism to provide visibility into what coreboot is doing is +its "console", providing insight at configurable verbosity levels to multiple +potential outputs. + +The main two outputs are cbmem, a buffer in RAM that can be read out from the +payload or operating system, and the serial console, sending the log to an +external system through UART controllers. There are a few other options, e.g. +EHCI Debug and even a few esoteric options like modulating the output onto +the PC speaker output. + +While writing the log into RAM costs only a negligible amount of time, +others are more expensive: To write a character to UART, the driver needs +to wait for the hardware FIFOs to be ready, so enabling serial output can +add a significant amount of time (10 seconds aren't unusual) to the boot time. + +For this reason shipping coreboot images usually come without serial console +support compiled in, but sometimes it would be desirable to get additional +visibility into the behavior of a given configuration with little effort +and as little behavior change as possible. + +Regarding behavioral changes, adding serial console output to arbitrary +parts of the code flow obviously _does_ induce differences, e.g. by messing +up timings. However, those differences are inherent to the change - there +are others that can be avoided, e.g. changes that come from differences in +code size or layout. + +To facilitate this, this document discusses options on how to selectively +enable serial output in a given binary image and a few related approaches. + +## Approaches considered + +### Have separate images with serial support compiled in or not + +This is how the problem is usually approached at the time of writing this doc: +Take a configuration for normal boot and if there's a need to dig in deeper, +rebuild the same configuration but with serial enabled. + +This strategy is simple but comes with downsides: First, even though that +seems to happen less often recently, differences in code size, even as benign +as compiling serial console support in or not, can lead to behavioral changes. + +Switching images wholesale can come at a major increase in complexity in the +environment. For example, there are plans to use serial output as a signal +for some (but not all) automated tests in Chrome OS but the way firmware +images are delivered in that environment doesn't allow keeping serial-enabled +images around right now. + +While that specific testing infrastructure could be extended, similar issues +would have to be solved individually for all affected coreboot users, making +users reinvent the wheel. + +### Add a configuration flag (CMOS nvram) + +The CMOS nvram would be an obvious place to put such a flag but sadly it's +an x86-specific solution: None of the other platforms provide something like +this and even on x86 this is supposed to be on the way out (although vendors +have already been saying that decades ago.) + +### Add a configuration flag (VPD) + +While VPD isn't universal, it's used in more than just Chrome OS contexts +these days. Due to its key/value design, adding more flags is simple. + +The downside is that VPD isn't guaranteed to be available in the bootblock +(since it doesn't use it yet) and there have been concerns that adding +support for that significantly increases the overhead on platforms without +memory mapped SPI flash. + +### Add a configuration flag (GBB) + +GBB also isn't universal, and the way it allows adding flags is much more +static than with VPD. It should bring less complexity though, avoiding all +the string parsing, but the bootblock might still not be able to access it. + +### Add a configuration flag (into the bootblock binary) + +It would be feasible to put a global variable into the bootblock, read out +the offset to that byte to the bootblock's memory map and store it somewhere. +That way the serial console could be enabled or disabled by flipping a byte +in the bootblock. + +However this requires updating signatures on platforms with a signed bootblock +(Intel Boot Guard) and it likely isn't feasible to keep the signing key +around on arbitrary testing machines. This wouldn't affect Chrome OS but +given that there's lots of activity on building such a "trusted" boot path +in other coreboot based projects, using this approach guarantees that such +efforts would have to build their own flag of this kind if they need it, +instead of reusing this work. + +### Add a configuration flag in flash but ignore the bootblock + +By forgoing the bootblock, visibility into the very earliest parts of the +boot process is limited (unless always enabled, which might be an option +since even with slow serial ports there isn't much for the console to do: +At some point we didn't have serial output in the bootblock _at all_!) + +On the upside, by the next stage (romstage or verstage) enough infrastructure +is present to access flash for various purposes that reading a flag shouldn't +add a significant amount of complexity even when using VPD. + +## Proposal + +Forgo the bootblock in these considerations (and default to the serial +console being enabled there if it's compiled in). Allow overriding that +default through Kconfig, so that serial is compiled in but not used even in +the bootblock. In verstage or romstage (if there is no verstage), read out +a VPD flag (the most portable and flexible mechanism in this evaluation) +and change the default to whatever is found there. + +## Discussion + +### How widely is VPD used? + +It originates with Chrome OS devices and all of them use it. The default fmap +layout for x86 (`util/cbfstool/default-x86.fmd`) adds a VPD if the support +code is compiled in. Various other devices (e.g. across our lenovo ports) +have a VPD region in their vboot-enabled FMAPs. + +The main issue might be to support non-Chrome OS non-x86 devices, but right +now these are underserved anyway. + +### Messing up secured boot processes? + +On vboot-enabled designs, the VPD region is put in the RO part of the flash. +This means that enabling the serial console through this mechanism is already +a privileged operation: People who could mess up the boot flow (e.g. through +timing) can also mess up the boot flow by writing their own image. + +Platforms merely enforcing boot trust through a signature scheme (e.g. Boot +Guard) need to treat the VPD variable (like all other configuration options) +as untrusted input and evaluate if this capability should be enabled in +their builds. diff --git a/Documentation/technotes/index.md b/Documentation/technotes/index.md index a9320fb..7463edf 100644 --- a/Documentation/technotes/index.md +++ b/Documentation/technotes/index.md @@ -3,4 +3,5 @@ * [Dealing with Untrusted Input in SMM](2017-02-dealing-with-untrusted-input-in-smm.md) * [Rebuilding coreboot image generation](2015-11-rebuilding-coreboot-image-generation.md) * [Unit testing coreboot](2020-03-unit-testing-coreboot.md) +* [Selectable serial console](2021-05-selectable-serial-console.md) * [Address Sanitizer](asan.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/54385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1b0efc55880095f9d5d6d6e448f2c8677d57ff5 Gerrit-Change-Number: 54385 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/smm: Fix u32 type mismatch in print statement
by Paul Menzel (Code Review) 17 May '21

17 May '21

Attention is currently required from: Paul Menzel, Werner Zeh. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54343 to look at the new patch set (#3). Change subject: cpu/x86/smm: Fix u32 type mismatch in print statement ...................................................................... cpu/x86/smm: Fix u32 type mismatch in print statement CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c:415:42: error: format '%lx' expects argument of type 'long unsigned int', but argument 4 has type 'u32' {aka 'unsigned int'} [-Werror=format=] 415 | printk(BIOS_DEBUG, "%s: stack_end = 0x%lx\n", | ~~^ | | | long unsigned int | %x 416 | __func__, stub_params->stack_top - total_stack_size); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | u32 {aka unsigned int} Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Change-Id: Ib504bc5e5b19f62d4702b7f485522a2ee3d26685 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/54343/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/54343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib504bc5e5b19f62d4702b7f485522a2ee3d26685 Gerrit-Change-Number: 54343 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/ifdtool: Use Pch Strap Length(PSL) to uniquely identify IFDv2 ch...
by Paul Menzel (Code Review) 17 May '21

17 May '21

Attention is currently required from: Tim Wawrzynczak, Stefan Reinauer, Subrata Banik, Angel Pons. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54305 ) Change subject: util/ifdtool: Use Pch Strap Length(PSL) to uniquely identify IFDv2 chipsets ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54305/comment/17412ec4_d8728bb4 PS3, Line 7: Pch Strap Length(PSL) Please add a space before (. -- To view, visit https://review.coreboot.org/c/coreboot/+/54305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25f69ce775454409974056d8326c02e29038ec8a Gerrit-Change-Number: 54305 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Mon, 17 May 2021 14:07:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/ifdtool: Use Pch Strap Length(PSL) to uniquely identify IFDv2 ch...
by Angel Pons (Code Review) 17 May '21

17 May '21

Attention is currently required from: Tim Wawrzynczak, Stefan Reinauer, Subrata Banik, Angel Pons. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54305 ) Change subject: util/ifdtool: Use Pch Strap Length(PSL) to uniquely identify IFDv2 chipsets ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54305/comment/ef64a7bc_408098b1 PS2, Line 35: TEST > Hi Angel, Ping! any improvement ? Sorry, haven't been able to test this patch yet. 😞 I'll test it right now. -- To view, visit https://review.coreboot.org/c/coreboot/+/54305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25f69ce775454409974056d8326c02e29038ec8a Gerrit-Change-Number: 54305 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Mon, 17 May 2021 13:37:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] kontron/mal10: setup GPIOs in EC
by Maxim Polyakov (Code Review) 17 May '21

17 May '21

Attention is currently required from: Felix Singer, Nico Huber. Hello Felix Singer, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54380 to look at the new patch set (#2). Change subject: [WIP] kontron/mal10: setup GPIOs in EC ...................................................................... [WIP] kontron/mal10: setup GPIOs in EC Change-Id: I7d354aa32ac8c64f54b2bcbdb4f1b8915f55264e Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/kontron/mal10/variants/mal10/devicetree.cb 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/54380/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d354aa32ac8c64f54b2bcbdb4f1b8915f55264e Gerrit-Change-Number: 54380 Gerrit-PatchSet: 2 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/ifdtool: Use Pch Strap Length(PSL) to uniquely identify IFDv2 ch...
by Subrata Banik (Code Review) 17 May '21

17 May '21

Attention is currently required from: Tim Wawrzynczak, Stefan Reinauer, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54305 ) Change subject: util/ifdtool: Use Pch Strap Length(PSL) to uniquely identify IFDv2 chipsets ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54305/comment/55538341_dd044948 PS2, Line 35: TEST > I'll test tomorrow Hi Angel, Ping! any improvement ? -- To view, visit https://review.coreboot.org/c/coreboot/+/54305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25f69ce775454409974056d8326c02e29038ec8a Gerrit-Change-Number: 54305 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Mon, 17 May 2021 13:24:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Upgrade LZMA Decoder to version 19.0
by Krystian Hebel (Code Review) 17 May '21

17 May '21

Attention is currently required from: Harshit Sharma. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41963 ) Change subject: lib: Upgrade LZMA Decoder to version 19.0 ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Just tested this on a ramstage that was copied to RAM before decompression (PPC64, mmap_helper_region_device is used because flash is protected with ECC) and I see a speed improvement. Before: ``` FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 51634 none fallback/ramstage 0xca80 stage 23842 none config 0x12800 raw 177 none revision 0x12900 raw 674 none (empty) 0x12c00 null 315800 none header pointer 0x5fdc0 cbfs header 4 none --------------- CBFS: Found 'fallback/ramstage' @0xca80 size 0x5d22 in mcache @0x00013070 Timestamp - starting to load ramstage: 4315892 Timestamp - starting LZMA decompress (ignore for x86): 4327646 Timestamp - finished LZMA decompress (ignore for x86): 4332315 Timestamp - finished loading ramstage: 4332708 ``` After: ``` FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 55225 none fallback/ramstage 0xd880 stage 26339 none config 0x13fc0 raw 177 none revision 0x140c0 raw 674 none (empty) 0x143c0 null 309720 none header pointer 0x5fdc0 cbfs header 4 none --------------- CBFS: Found 'fallback/ramstage' @0xd880 size 0x66e3 in mcache @0x00013070 Timestamp - starting to load ramstage: 4321871 Timestamp - starting LZMA decompress (ignore for x86): 4334852 Timestamp - finished LZMA decompress (ignore for x86): 4339430 Timestamp - finished loading ramstage: 4339818 ``` This gives ~2% shorter time required for decompressing ~10% bigger ramstage, so the change is somewhat noticeable. This ramstage is relatively small so printing the timestamps through serial may take more time than the decompression itself. Unfortunately I must print them, this port is not ready yet so I have no way of reading them later. -- To view, visit https://review.coreboot.org/c/coreboot/+/41963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31f43e8bdda6536c719879381cad6a921dd94718 Gerrit-Change-Number: 41963 Gerrit-PatchSet: 5 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes HAOUAS Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: qma ster <qmastery16(a)gmail.com> Gerrit-Attention: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Comment-Date: Mon, 17 May 2021 13:24:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] autoport: support generating BDW mainboard files for HSW
by Iru Cai (vimacs) (Code Review) 17 May '21

17 May '21

Attention is currently required from: Iru Cai. Hello build bot (Jenkins), Iru Cai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51917 to look at the new patch set (#3). Change subject: [WIP] autoport: support generating BDW mainboard files for HSW ...................................................................... [WIP] autoport: support generating BDW mainboard files for HSW Not tested. Change-Id: Ie00ec26d62739b3aed598ad8f80952e631925668 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/autoport/haswell.go M util/autoport/lynxpoint.go M util/autoport/wildcatpoint.go 3 files changed, 19 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/51917/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/51917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00ec26d62739b3aed598ad8f80952e631925668 Gerrit-Change-Number: 51917 Gerrit-PatchSet: 3 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/intelp2m/snr: Remove incorrent GPO macro
by Maxim Polyakov (Code Review) 17 May '21

17 May '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44472 ) Change subject: util/intelp2m/snr: Remove incorrent GPO macro ...................................................................... util/intelp2m/snr: Remove incorrent GPO macro GPIO Driver mode is used for configuration interrupt routing for external devices through GPI. But there is no point in configuring this for GPO and according to the changes in the project [1], this patch removes the code to generate PAD_CFG_GPO_GPIO_DRIVER macro. [1] Change-Id: I74c318897647836f4604a937543254f44b470433 Change-Id: Ibe7b787d455b638e70e54fb8b048c8aad8283037 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/intelp2m/platforms/snr/macro.go 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/44472/1 diff --git a/util/intelp2m/platforms/snr/macro.go b/util/intelp2m/platforms/snr/macro.go index 86cc7b7..3340ec0 100644 --- a/util/intelp2m/platforms/snr/macro.go +++ b/util/intelp2m/platforms/snr/macro.go @@ -213,11 +213,6 @@ dw0.CntrMaskFieldsClear(common.RxLevelEdgeConfigurationMask) } macro.Set("PAD_CFG") - if macro.IsOwnershipDriver() { - // PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) - macro.Add("_GPO_GPIO_DRIVER").Add("(").Id().Val().Rstsrc().Pull().Add("),") - return - } if term != 0 { // e.g. PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), macro.Add("_TERM") -- To view, visit https://review.coreboot.org/c/coreboot/+/44472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe7b787d455b638e70e54fb8b048c8aad8283037 Gerrit-Change-Number: 44472 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit May 2021