coreboot-gerrit May 2021

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Change in coreboot[master]: mb/intel/adlrvp: Disable EC sync for adlrvp_ext_ec
by Rizwan Qureshi (Code Review) 17 May '21

17 May '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54016 ) Change subject: mb/intel/adlrvp: Disable EC sync for adlrvp_ext_ec ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62a4fceb83dc6b20f699b4662e8f421aadafdee5 Gerrit-Change-Number: 54016 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Mon, 17 May 2021 16:00:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool:cezanne: use correct bootloader binary for whitelist support
by Martin Roth (Code Review) 17 May '21

17 May '21

Attention is currently required from: Raul Rangel, Bao Zheng, Marshall Dawson, Nikolai Vyssotski. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53892 ) Change subject: amdfwtool:cezanne: use correct bootloader binary for whitelist support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71539a2065546547edc8a2621474cd1388b6434b Gerrit-Change-Number: 53892 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 17 May 2021 15:57:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/acpi: Add device tree driver to generate thermal zone
by Raul Rangel (Code Review) 17 May '21

17 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54132 ) Change subject: drivers/acpi: Add device tree driver to generate thermal zone ...................................................................... Patch Set 2: (2 comments) File src/drivers/acpi/thermal_zone/thermal_zone.c: https://review.coreboot.org/c/coreboot/+/54132/comment/313388bb_e4872bfc PS2, Line 98: !config->passive_config.time_constant_1 : || !config->passive_config.time_constant_2 : || !config->passive_config.time_sampling_period) { : acpigen_write_name_integer("_TC1", 2); : acpigen_write_name_integer("_TC2", 5); : acpigen_write_name_integer("_TSP", SECONDS_TO_DECI_SECONDS(10)); > Should there be an error instead of emitting defaults? The same values have been copied so many times, I wanted to centralize it: git grep _TC1, src/ec/lenovo/h8/acpi/thermal.asl: Name (_TC1, 0x02) src/ec/lenovo/h8/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/getac/p470/acpi/thermal.asl: Method (_TC1, 0, Serialized) src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/google/auron/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/google/beltino/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/google/butterfly/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/google/link/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/google/parrot/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/google/slippy/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/google/stout/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/intel/baskingridge/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/intel/emeraldlake2/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/intel/wtm2/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/kontron/ktqm77/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/roda/rk886ex/acpi/thermal.asl: Method (_TC1, 0, Serialized) src/mainboard/roda/rk9/acpi/thermal.asl: Method (_TC1, 0, Serialized) src/mainboard/roda/rv11/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/samsung/lumpy/acpi/thermal.asl: Name (_TC1, 0x02) src/mainboard/samsung/stumpy/acpi/thermal.asl: Name (_TC1, 0x02) Do you think I should still error out? https://review.coreboot.org/c/coreboot/+/54132/comment/341b74ff_c9b4061e PS2, Line 114: : config->temperature_controller->ops->acpigen_write_TMP(dev); > Hmm... I'm not a big fan of adding a new callback to `struct device *`... […] That would also work. The reason I went with the callback is that we can actually perform error checking to see if it's been implemented. We don't have a way to verify that the temperature controller has implemented _TMP. You think I should still go with the pure ACPI version? -- To view, visit https://review.coreboot.org/c/coreboot/+/54132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee2a42db749f18eef6c3f73cdbb3441567301e5d Gerrit-Change-Number: 54132 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 17 May 2021 15:56:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Enable PCIe Power Management and Clock Features
by Martin Roth (Code Review) 17 May '21

17 May '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Eric Peers, Matt Papageorge, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54282 ) Change subject: mb/google/guybrush: Enable PCIe Power Management and Clock Features ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Matt, could you do the same on mancomb? -- To view, visit https://review.coreboot.org/c/coreboot/+/54282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefc4b5b489cb8caf59f21dd4333d7af66ba47c32 Gerrit-Change-Number: 54282 Gerrit-PatchSet: 6 Gerrit-Owner: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 17 May 2021 15:56:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Makefile.inc: Drop unused `cbfs-files-processor-vsa`
by Martin Roth (Code Review) 17 May '21

17 May '21

Attention is currently required from: Angel Pons. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54360 ) Change subject: Makefile.inc: Drop unused `cbfs-files-processor-vsa` ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28bf61cb953e3352b59aa91059341e4de8f84f23 Gerrit-Change-Number: 54360 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 17 May 2021 15:52:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/asus/p8h61-m_lx: Switch to overridetree setup
by Angel Pons (Code Review) 17 May '21

17 May '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54390 ) Change subject: mb/asus/p8h61-m_lx: Switch to overridetree setup ...................................................................... mb/asus/p8h61-m_lx: Switch to overridetree setup Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M LX remains identical when not adding the .config file in it. Change-Id: I3142773e8c8f11f27f7926933097ffde8ba241e2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asus/h61-series/Kconfig R src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb 2 files changed, 1 insertion(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/54390/1 diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig index 06c4a57..c3a871c 100644 --- a/src/mainboard/asus/h61-series/Kconfig +++ b/src/mainboard/asus/h61-series/Kconfig @@ -31,22 +31,10 @@ default "P8H61-M LX3 R2.0" if BOARD_ASUS_P8H61_M_LX3_R2_0 default "P8H61-M PRO" if BOARD_ASUS_P8H61_M_PRO -# TODO: remove once all boards use overridetrees -if !BOARD_ASUS_P8H61_M_LX - config OVERRIDE_DEVICETREE string default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -endif -if BOARD_ASUS_P8H61_M_LX - -config DEVICETREE - string - default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" - -endif - config CMOS_DEFAULT_FILE default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.default" diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb similarity index 71% rename from src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb rename to src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb index 05b8e38..aa9f8c8 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb @@ -1,36 +1,11 @@ ## SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end - device domain 0 on subsystemid 0x1043 0x844d inherit - - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics - device pci 02.0 on end # VGA controller - chip southbridge/intel/bd82x6x - register "c2_latency" = "0x0065" register "gen1_dec" = "0x00000295" # Super I/O HWM - register "sata_port_map" = "0x33" - register "spi_lvscc" = "0x2005" - register "spi_uvscc" = "0x2005" - device pci 16.0 on end # Management Engine interface 1 - device pci 16.1 off end # Management Engine interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on # HD audio controller subsystemid 0x1043 0x8445 end @@ -48,8 +23,7 @@ device pci 1c.5 off end # Unused PCIe port device pci 1c.6 off end # Unused PCIe port device pci 1c.7 off end # Unused PCIe port - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy @@ -106,10 +80,6 @@ device pnp 2e.17 off end # GPIOA end end - device pci 1f.2 on end # SATA controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA controller 2 - device pci 1f.6 off end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/54390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3142773e8c8f11f27f7926933097ffde8ba241e2 Gerrit-Change-Number: 54390 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/h61m-cs: Switch to overridetree setup
by Angel Pons (Code Review) 17 May '21

17 May '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54389 ) Change subject: mb/asus/h61m-cs: Switch to overridetree setup ...................................................................... mb/asus/h61m-cs: Switch to overridetree setup Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus H61M-CS remains identical when not adding the .config file in it. Change-Id: I34eb5387fddcb3505c9218b20b706b773e979b0e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asus/h61-series/Kconfig R src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb 2 files changed, 4 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/54389/1 diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig index 8b3f04d..06c4a57 100644 --- a/src/mainboard/asus/h61-series/Kconfig +++ b/src/mainboard/asus/h61-series/Kconfig @@ -32,14 +32,14 @@ default "P8H61-M PRO" if BOARD_ASUS_P8H61_M_PRO # TODO: remove once all boards use overridetrees -if BOARD_ASUS_P8H61_M_LX3_R2_0 || BOARD_ASUS_P8H61_M_PRO +if !BOARD_ASUS_P8H61_M_LX config OVERRIDE_DEVICETREE string default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" endif -if !BOARD_ASUS_P8H61_M_LX3_R2_0 && !BOARD_ASUS_P8H61_M_PRO +if BOARD_ASUS_P8H61_M_LX config DEVICETREE string diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/devicetree.cb b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb similarity index 63% rename from src/mainboard/asus/h61-series/variants/h61m-cs/devicetree.cb rename to src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb index 3ec5e5f..89ef419 100644 --- a/src/mainboard/asus/h61-series/variants/h61m-cs/devicetree.cb +++ b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb @@ -1,32 +1,10 @@ ## SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0x0 on end - device lapic 0xacac off end - end - end device domain 0 on subsystemid 0x1043 0x844d inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" + chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - register "sata_port_map" = "0x33" - register "spi_lvscc" = "0x2005" - register "spi_uvscc" = "0x2005" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on # High Definition Audio Audio controller subsystemid 0x1043 0x8445 end @@ -40,8 +18,7 @@ end device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge PCI-LPC bridge chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel @@ -78,10 +55,6 @@ device pnp 2e.16 off end # Deep Sleep end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/54389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34eb5387fddcb3505c9218b20b706b773e979b0e Gerrit-Change-Number: 54389 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/p8h61-m_pro: Switch to overridetree setup
by Angel Pons (Code Review) 17 May '21

17 May '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54388 ) Change subject: mb/asus/p8h61-m_pro: Switch to overridetree setup ...................................................................... mb/asus/p8h61-m_pro: Switch to overridetree setup Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M PRO remains identical when not adding the .config file in it. Change-Id: I443d3823e32a246a89ff12e52a0301b2c252e23b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asus/h61-series/Kconfig R src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb 2 files changed, 4 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/54388/1 diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig index 3e802d3..8b3f04d 100644 --- a/src/mainboard/asus/h61-series/Kconfig +++ b/src/mainboard/asus/h61-series/Kconfig @@ -32,14 +32,14 @@ default "P8H61-M PRO" if BOARD_ASUS_P8H61_M_PRO # TODO: remove once all boards use overridetrees -if BOARD_ASUS_P8H61_M_LX3_R2_0 +if BOARD_ASUS_P8H61_M_LX3_R2_0 || BOARD_ASUS_P8H61_M_PRO config OVERRIDE_DEVICETREE string default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" endif -if !BOARD_ASUS_P8H61_M_LX3_R2_0 +if !BOARD_ASUS_P8H61_M_LX3_R2_0 && !BOARD_ASUS_P8H61_M_PRO config DEVICETREE string diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb similarity index 63% rename from src/mainboard/asus/h61-series/variants/p8h61-m_pro/devicetree.cb rename to src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb index b1292e7..d726131 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/overridetree.cb @@ -1,34 +1,10 @@ ## SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end device domain 0 on - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics (PCIEX16_1) - device pci 02.0 on end # Internal graphics VGA controller - - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" + chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" # HWM - register "sata_port_map" = "0x33" - register "spi_lvscc" = "0x2005" - register "spi_uvscc" = "0x2005" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller device pci 1c.0 on end # PCIe x1 Port (PCIEX1_1) device pci 1c.1 on end # PCIe x1 Port (PCIEX1_2) device pci 1c.2 on # Realtek RTL8111E Ethernet Controller @@ -43,8 +19,7 @@ device pci 1c.5 on end # ASMedia ASM1062 SATA Controller device pci 1c.6 off end # Unused PCIe Port device pci 1c.7 off end # Unused PCIe Port - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy @@ -101,10 +76,6 @@ device pnp 4e.0 on end # TPM end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/54388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I443d3823e32a246a89ff12e52a0301b2c252e23b Gerrit-Change-Number: 54388 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/p8h61-m_lx3_r2_0: Extract overridetree
by Angel Pons (Code Review) 17 May '21

17 May '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54387 ) Change subject: mb/asus/p8h61-m_lx3_r2_0: Extract overridetree ...................................................................... mb/asus/p8h61-m_lx3_r2_0: Extract overridetree Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M LX3 R2.0 remains identical when not adding the .config file in it. Change-Id: I989f69d000a38a7b1f4e0832341aa347cc0bfe98 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asus/h61-series/Kconfig A src/mainboard/asus/h61-series/devicetree.cb R src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb 3 files changed, 62 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/54387/1 diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig index f35cdae..3e802d3 100644 --- a/src/mainboard/asus/h61-series/Kconfig +++ b/src/mainboard/asus/h61-series/Kconfig @@ -31,10 +31,22 @@ default "P8H61-M LX3 R2.0" if BOARD_ASUS_P8H61_M_LX3_R2_0 default "P8H61-M PRO" if BOARD_ASUS_P8H61_M_PRO +# TODO: remove once all boards use overridetrees +if BOARD_ASUS_P8H61_M_LX3_R2_0 + +config OVERRIDE_DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +endif +if !BOARD_ASUS_P8H61_M_LX3_R2_0 + config DEVICETREE string default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" +endif + config CMOS_DEFAULT_FILE default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.default" diff --git a/src/mainboard/asus/h61-series/devicetree.cb b/src/mainboard/asus/h61-series/devicetree.cb new file mode 100644 index 0000000..07c0a86 --- /dev/null +++ b/src/mainboard/asus/h61-series/devicetree.cb @@ -0,0 +1,50 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + device domain 0 on + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x + register "c2_latency" = "0x0065" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + device pci 19.0 off end # Intel GbE + device pci 1a.0 on end # EHCI #2 + device pci 1b.0 on end # HD Audio + + device pci 1c.0 off end # RP #1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 off end # RP #3 + device pci 1c.3 off end # RP #4 + device pci 1c.4 off end # RP #5 + device pci 1c.5 off end # RP #6 + device pci 1c.6 off end # RP #7 + device pci 1c.7 off end # RP #8 + + device pci 1d.0 on end # EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb similarity index 64% rename from src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb rename to src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb index 1ae77ad..5d9635c 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb @@ -1,35 +1,10 @@ ## SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end device domain 0 on subsystemid 0x1043 0x844d inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PEG - device pci 02.0 on end # iGPU - chip southbridge/intel/bd82x6x - register "c2_latency" = "0x0065" register "gen1_dec" = "0x000c0291" - register "sata_port_map" = "0x33" - register "spi_lvscc" = "0x2005" - register "spi_uvscc" = "0x2005" - - device pci 16.0 on end # MEI #1 - device pci 16.1 off end # MEI #2 - device pci 16.2 off end # ME IDE-R - device pci 16.3 off end # ME KT - device pci 19.0 off end # Intel GbE - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # HD Audio device pci 1c.0 on end # RP #1 device pci 1c.1 off end # RP #2 @@ -40,8 +15,6 @@ device pci 1c.6 off end # RP #7 device pci 1c.7 off end # RP #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge device pci 1f.0 on # LPC bridge chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel @@ -78,10 +51,6 @@ device pnp 2e.16 off end # Deep Sleep end end - device pci 1f.2 on end # SATA (AHCI) - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA (Legacy) - device pci 1f.6 off end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/54387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I989f69d000a38a7b1f4e0832341aa347cc0bfe98 Gerrit-Change-Number: 54387 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/p8h61-m_lx3_r2_0: List all PCH PCIe RPs in devicetree
by Angel Pons (Code Review) 17 May '21

17 May '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54386 ) Change subject: mb/asus/p8h61-m_lx3_r2_0: List all PCH PCIe RPs in devicetree ...................................................................... mb/asus/p8h61-m_lx3_r2_0: List all PCH PCIe RPs in devicetree Done to preserve reproducibility when switching to overridetrees. The H61 PCH only supports 6 PCIe root ports anyway. Change-Id: I926d62dda512e435d44c0646083c7722427dc80b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/54386/1 diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb index 62dbb37..1ae77ad 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb @@ -37,6 +37,8 @@ device pci 1c.3 on end # RP #4: PCIEX1_1 device pci 1c.4 on end # RP #5: PCIEX1_2 device pci 1c.5 on end # RP #6: RTL8111 GbE NIC + device pci 1c.6 off end # RP #7 + device pci 1c.7 off end # RP #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge -- To view, visit https://review.coreboot.org/c/coreboot/+/54386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926d62dda512e435d44c0646083c7722427dc80b Gerrit-Change-Number: 54386 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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