Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54413 )
Change subject: mb/asus/p8z77-v_lx2: Extract overridetree
......................................................................
mb/asus/p8z77-v_lx2: Extract overridetree
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8Z77-V LX2
remains identical when not adding the .config file in it.
Change-Id: Ia84b07f5fec3c2969134b0d0bc39248d50ac04ff
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/mainboard/asus/p8z77-series/Kconfig
A src/mainboard/asus/p8z77-series/devicetree.cb
R src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/overridetree.cb
3 files changed, 68 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/54413/1
diff --git a/src/mainboard/asus/p8z77-series/Kconfig b/src/mainboard/asus/p8z77-series/Kconfig
index d09b3cb..d963b09 100644
--- a/src/mainboard/asus/p8z77-series/Kconfig
+++ b/src/mainboard/asus/p8z77-series/Kconfig
@@ -29,10 +29,22 @@
default "P8Z77-M PRO" if BOARD_ASUS_P8Z77_M_PRO
default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2
+# TODO: remove once all boards use overridetrees
+if BOARD_ASUS_P8Z77_M_PRO
+
config DEVICETREE
string
default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
+endif
+if !BOARD_ASUS_P8Z77_M_PRO
+
+config OVERRIDE_DEVICETREE
+ string
+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+endif
+
config CMOS_DEFAULT_FILE
default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.default"
diff --git a/src/mainboard/asus/p8z77-series/devicetree.cb b/src/mainboard/asus/p8z77-series/devicetree.cb
new file mode 100644
index 0000000..1b9d14d
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/devicetree.cb
@@ -0,0 +1,56 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
+ device cpu_cluster 0 on
+ chip cpu/intel/model_206ax
+ register "acpi_c1" = "1"
+ register "acpi_c2" = "3"
+ register "acpi_c3" = "5"
+ device lapic 0 on end
+ device lapic 0xacac off end
+ end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # PCIEX16_1
+ device pci 02.0 on end # iGPU
+
+ chip southbridge/intel/bd82x6x
+ register "c2_latency" = "0x0065"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x3f"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+
+ device pci 14.0 on end # xHCI
+ device pci 16.0 on end # MEI #1
+ device pci 16.1 off end # MEI #2
+ device pci 16.2 off end # ME IDE-R
+ device pci 16.3 off end # ME KT
+ device pci 19.0 off end # Intel GbE
+ device pci 1a.0 on end # EHCI #2
+ device pci 1b.0 on end # HD Audio
+
+ device pci 1c.0 off end # RP #1
+ device pci 1c.1 off end # RP #2
+ device pci 1c.2 off end # RP #3
+ device pci 1c.3 off end # RP #4
+ device pci 1c.4 off end # RP #5
+ device pci 1c.5 off end # RP #6
+ device pci 1c.6 off end # RP #7
+ device pci 1c.7 off end # RP #8
+
+ device pci 1d.0 on end # EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on # LPC bridge
+ end
+ device pci 1f.2 on end # SATA (AHCI)
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA (Legacy)
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/devicetree.cb b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/overridetree.cb
similarity index 60%
rename from src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/devicetree.cb
rename to src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/overridetree.cb
index 40f8e6d..6be23fa 100644
--- a/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/devicetree.cb
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/overridetree.cb
@@ -1,40 +1,10 @@
## SPDX-License-Identifier: GPL-2.0-only
chip northbridge/intel/sandybridge
- device cpu_cluster 0 on
- chip cpu/intel/model_206ax
- register "acpi_c1" = "1"
- register "acpi_c2" = "3"
- register "acpi_c3" = "5"
- device lapic 0 on end
- device lapic 0xacac off end
- end
- end
device domain 0 on
subsystemid 0x1043 0x84ca inherit
- device pci 00.0 on end # Host bridge
- device pci 01.0 on end # PCIEX16_1
- device pci 02.0 on end # iGPU
-
chip southbridge/intel/bd82x6x
- register "c2_latency" = "0x0065"
register "gen1_dec" = "0x000c0291"
- register "sata_interface_speed_support" = "0x3"
- register "sata_port_map" = "0x3f"
- register "spi_lvscc" = "0x2005"
- register "spi_uvscc" = "0x2005"
- register "superspeed_capable_ports" = "0x0000000f"
- register "xhci_overcurrent_mapping" = "0x00000c03"
- register "xhci_switchable_ports" = "0x0000000f"
-
- device pci 14.0 on end # xHCI
- device pci 16.0 on end # MEI #1
- device pci 16.1 off end # MEI #2
- device pci 16.2 off end # ME IDE-R
- device pci 16.3 off end # ME KT
- device pci 19.0 off end # Intel GbE
- device pci 1a.0 on end # EHCI #2
- device pci 1b.0 on end # HD Audio
device pci 1c.0 on end # RP #1: PCIEX16_2 (electrical x4)
device pci 1c.1 off end # RP #2:
@@ -45,8 +15,6 @@
device pci 1c.6 on end # RP #7: PCIEX1_1
device pci 1c.7 on end # RP #8: PCIEX1_2
- device pci 1d.0 on end # EHCI #1
- device pci 1e.0 off end # PCI bridge
device pci 1f.0 on # LPC bridge
chip superio/nuvoton/nct6779d
device pnp 2e.1 off end # Parallel
@@ -88,10 +56,6 @@
device pnp 2e.16 off end # Deep Sleep
end
end
- device pci 1f.2 on end # SATA (AHCI)
- device pci 1f.3 on end # SMBus
- device pci 1f.5 off end # SATA (Legacy)
- device pci 1f.6 off end # Thermal
end
end
end
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Gerrit-Change-Id: Ia84b07f5fec3c2969134b0d0bc39248d50ac04ff
Gerrit-Change-Number: 54413
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54133 )
Change subject: ec/google/chromeec: Implement support for DRIVERS_ACPI_THERMAL_ZONE
......................................................................
Patch Set 2:
(1 comment)
File src/ec/google/chromeec/ec_acpi.c:
https://review.coreboot.org/c/coreboot/+/54133/comment/50dbc280_ef1c25c1
PS2, Line 267:
: void google_chromeec_acpigen_write_TMP(const struct device *dev)
: {
: struct drivers_acpi_thermal_zone_config *config = config_of(dev);
: static char buf[DEVICE_PATH_MAX] = {};
: const char *ec_path = acpi_device_path(config->temperature_controller);
:
: /*
: * The cros EC device returns EC0.CREC as the acpi_name. The method
: * we want is on the EC0 device.
: */
: snprintf(buf, sizeof(buf), "%.*s.TSRD", strlen(ec_path) - 5,
: acpi_device_path(config->temperature_controller));
:
: acpigen_write_method_serialized("_TMP", 0);
:
: acpigen_emit_byte(RETURN_OP);
: acpigen_emit_namestring(buf);
: acpigen_write_integer(config->sensor_id);
:
: acpigen_write_method_end();
: }
> consider a refactor? https://review.coreboot. […]
Can we inject the EC0 device into the device tree at runtime? I'm not sure how complicated it is to update all the pointers though...
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Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50582 )
Change subject: sc7280: add qclib support
......................................................................
Patch Set 36:
(1 comment)
Patchset:
PS35:
> Ravi, can you please for reference put the qclib version (BOOT. […]
Thank you! However, I think that you uploaded on an old checkout. You need to rebased on top of latest head, mainly make sure https://review.coreboot.org/c/coreboot/+/54037 is in your repo.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/54379
to look at the new patch set (#2).
Change subject: mb/asus/h61-series: Always select `INTEL_INT15`
......................................................................
mb/asus/h61-series: Always select `INTEL_INT15`
The mainboard.c guard was only added to preserve reproducibility when
unifying the boards. The `install_intel_vga_int15_handler` function does
nothing when `VGA_ROM_RUN` is not selected. Remove the guard and always
select `INTEL_INT15` for simplicity.
Change-Id: If51a0ab1c57b0856018a62cf669e5d1b53e5333c
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/mainboard/asus/h61-series/Kconfig
M src/mainboard/asus/h61-series/Kconfig.name
M src/mainboard/asus/h61-series/mainboard.c
3 files changed, 1 insertion(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/54379/2
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54360 )
Change subject: Makefile.inc: Drop unused `cbfs-files-processor-vsa`
......................................................................
Patch Set 1: Code-Review+2
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