coreboot-gerrit April 2021

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Change in coreboot[master]: xeon_sp/cpx: Check FSP version for WW45 and die if version mismatch
by Johnny Lin (Code Review) 12 May '21

12 May '21

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47560 ) Change subject: xeon_sp/cpx: Check FSP version for WW45 and die if version mismatch ...................................................................... xeon_sp/cpx: Check FSP version for WW45 and die if version mismatch Change-Id: I19082ec210a270649e203779757fe39cb2e284f7 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/soc/intel/xeon_sp/cpx/Makefile.inc A src/soc/intel/xeon_sp/cpx/fsp.c M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h 3 files changed, 62 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/47560/1 diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index b2e653e..a0d9797 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -8,7 +8,7 @@ subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/intel/microcode -romstage-y += romstage.c ddr.c +romstage-y += romstage.c ddr.c fsp.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c diff --git a/src/soc/intel/xeon_sp/cpx/fsp.c b/src/soc/intel/xeon_sp/cpx/fsp.c new file mode 100644 index 0000000..0358143 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/fsp.c @@ -0,0 +1,54 @@ +#include <console/console.h> +#include <fsp/util.h> +#include <FspmUpd.h> + +void soc_validate_fsp_version(const struct fsp_header *hdr) +{ + bool mismatch = false; + union { + uint32_t val; + struct { + uint8_t bld_num; + uint8_t revision; + uint8_t minor; + uint8_t major; + } rev; + } revision; + revision.val = hdr->fsp_revision; + + if (((hdr->spec_version >> 4) != CPX_SPEC_MAJOR)) { + printk(BIOS_ALERT, "FSP spec major version %d doesn't match!\n", + hdr->spec_version >> 4); + mismatch = true; + } + if (((hdr->spec_version & 0xf) != CPX_SPEC_MINOR)) { + printk(BIOS_ALERT, "FSP spec minor version %d doesn't match!\n", + hdr->spec_version & 0xf); + mismatch = true; + } + if (revision.rev.major != CPX_REV_MAJOR) { + printk(BIOS_ALERT, "FSP revision major version %d doesn't match!\n", + revision.rev.major); + mismatch = true; + } + if (revision.rev.minor != CPX_REV_MINOR) { + printk(BIOS_ALERT, "FSP revision minor version %d doesn't match!\n", + revision.rev.minor); + mismatch = true; + } + if (revision.rev.revision != CPX_REV_VER) { + printk(BIOS_ALERT, "FSP revision version %d doesn't match!\n", + revision.rev.revision); + mismatch = true; + } + if (revision.rev.bld_num != CPX_REV_BUILD) { + printk(BIOS_ALERT, "FSP revision build number %d doesn't match!\n", + revision.rev.bld_num); + mismatch = true; + } + + if (mismatch) + die("FSP version is not correct\n"); + + printk(BIOS_INFO, "FSP version is expected\n"); +} diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index b4d4cad..15de4be 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -64,7 +64,13 @@ {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), 0x2C35363F, ADAPTIVE_CTLE} #define CPXSP_2S6KTI_EPARAM_TABLE_COUNT 12 // NOTE - needs to match number of elements in CPXSP_2S6KTI_EPARAM_TABLE - +/* FSP version */ +#define CPX_SPEC_MAJOR 2 +#define CPX_SPEC_MINOR 1 +#define CPX_REV_MAJOR 0 +#define CPX_REV_MINOR 2 +#define CPX_REV_VER 1 +#define CPX_REV_BUILD 45 #pragma pack(1) -- To view, visit https://review.coreboot.org/c/coreboot/+/47560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19082ec210a270649e203779757fe39cb2e284f7 Gerrit-Change-Number: 47560 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in libgfxinit[master]: [HACK] Switch LSPCON to PCON mode
by Angel Pons (Code Review) 11 May '21

11 May '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/46631 ) Change subject: [HACK] Switch LSPCON to PCON mode ...................................................................... [HACK] Switch LSPCON to PCON mode Change-Id: I3c9e67caf9511d62b19c0c175e8e75080fb7ac7d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M common/hw-gfx-dp_aux_ch.adb M common/hw-gfx-dp_aux_ch.ads M common/hw-gfx-dp_info.adb 3 files changed, 156 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/31/46631/1 diff --git a/common/hw-gfx-dp_aux_ch.adb b/common/hw-gfx-dp_aux_ch.adb index b8eb510..7406d5e 100644 --- a/common/hw-gfx-dp_aux_ch.adb +++ b/common/hw-gfx-dp_aux_ch.adb @@ -371,6 +371,42 @@ ---------------------------------------------------------------------------- + procedure I2C_Write_Byte + (Port : in T; + Address : in I2C.Transfer_Address; + Offset : in Word8; + Value : in Word8; + Success : out Boolean) + is + Index_Payload : constant DP_Defs.Aux_Payload := (Offset, Value, others => 16#00#); + + Length : constant I2C.Transfer_Length := 1; + Data : constant I2C.Transfer_Data := (Value, others => 16#00#); + begin + Do_I2C_Write (Port, Address, 1 + Length, Index_Payload, Success); + end I2C_Write_Byte; + + procedure I2C_Read_Byte + (Port : in T; + Address : in I2C.Transfer_Address; + Offset : in Word8; + Value : out Word8; + Success : out Boolean) + is + Index_Payload : constant DP_Defs.Aux_Payload := (Offset, others => 16#00#); + + Length : I2C.Transfer_Length := 1; + Data : I2C.Transfer_Data := (others => 16#00#); + begin + Do_I2C_Write (Port, Address, 1, Index_Payload, Success); + + if Success then + Do_I2C_Read (Port, Address, Length, Data, Success); + Success := Success and Length = 1; + end if; + Value := Data (0); + end I2C_Read_Byte; + procedure I2C_Read (Port : in T; Address : in I2C.Transfer_Address; diff --git a/common/hw-gfx-dp_aux_ch.ads b/common/hw-gfx-dp_aux_ch.ads index 85fddd0..78709a8 100644 --- a/common/hw-gfx-dp_aux_ch.ads +++ b/common/hw-gfx-dp_aux_ch.ads @@ -45,6 +45,20 @@ ---------------------------------------------------------------------------- + procedure I2C_Write_Byte + (Port : in T; + Address : in I2C.Transfer_Address; + Offset : in Word8; + Value : in Word8; + Success : out Boolean); + + procedure I2C_Read_Byte + (Port : in T; + Address : in I2C.Transfer_Address; + Offset : in Word8; + Value : out Word8; + Success : out Boolean); + procedure I2C_Read (Port : in T; Address : in I2C.Transfer_Address; diff --git a/common/hw-gfx-dp_info.adb b/common/hw-gfx-dp_info.adb index bf09933..93a1caf 100644 --- a/common/hw-gfx-dp_info.adb +++ b/common/hw-gfx-dp_info.adb @@ -15,15 +15,115 @@ with Ada.Unchecked_Conversion; with HW.Debug; +with HW.Time; with GNAT.Source_Info; with HW.GFX.DP_Defs; +with HW.GFX.I2C; use type HW.Word8; use type HW.Word16; package body HW.GFX.DP_Info is + procedure Read_Lspcon_Mode + (Port : in T; + Mode : out Word8; + Success : out Boolean) + is + begin + pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + + for I in 1 .. 6 loop + Aux_Ch.I2C_Read_Byte + (Port => Port, + Address => 16#40#, + Offset => 16#41#, + Value => Mode, + Success => Success); + exit when Success; + Time.U_Delay (500); + end loop; + end Read_Lspcon_Mode; + + procedure Write_Lspcon_Mode + (Port : in T; + Mode : in Word8; + Success : out Boolean) + is + begin + pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + + for I in 1 .. 6 loop + Aux_Ch.I2C_Write_Byte + (Port => Port, + Address => 16#40#, + Offset => 16#40#, + Value => 16#01#, + Success => Success); + exit when Success; + Time.U_Delay (500); + end loop; + end Write_Lspcon_Mode; + + procedure Set_Lspcon_To_Pcon_Mode (Port : in T; Success : out Boolean) + is + Timeout : constant Natural := 20; + Lspcon_Mode : Word8; + begin + pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + + Read_Lspcon_Mode + (Port => Port, + Mode => Lspcon_Mode, + Success => Success); + + if not Success then + pragma Debug (Debug.Put_Line ("Could not determine LSPCON mode.")); + return; + end if; + + pragma Debug (Debug.Put_Line ("Current LSPCON mode: " & Lspcon_Mode'Image)); + + if Lspcon_Mode /= 0 then + pragma Debug (Debug.Put_Line ("LSPCON mode is good enough.")); + return; + end if; + + -- Change to PCON mode if necessary + Write_Lspcon_Mode + (Port => Port, + Mode => Lspcon_Mode, + Success => Success); + + if not Success then + pragma Debug (Debug.Put_Line ("Could not write new LSPCON mode.")); + return; + end if; + + for I in 1 .. Timeout loop + Read_Lspcon_Mode + (Port => Port, + Mode => Lspcon_Mode, + Success => Success); + if not Success then + pragma Debug (Debug.Put_Line ("Could not determine new LSPCON mode.")); + return; + end if; + if Lspcon_Mode /= 0 then + pragma Debug (Debug.Put_Line ("Successfully set LSPCON to PCON mode.")); + pragma Debug (Debug.Put_Line ("Current LSPCON mode: " & Lspcon_Mode'Image)); + return; + end if; + Time.M_Delay (100); + end loop; + if Success then + pragma Debug (Debug.Put_Line ("Timed out waiting for LSPCON mode change.")); + pragma Debug (Debug.Put_Line ("Current LSPCON mode: " & Lspcon_Mode'Image)); + Success := False; + end if; + end Set_Lspcon_To_Pcon_Mode; + procedure Read_Caps (Link : in out DP_Link; Port : in T; @@ -36,6 +136,12 @@ begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + Set_Lspcon_To_Pcon_Mode (Port, Success); + + if not Success then + pragma Debug (Debug.Put_Line ("Could not change LSPCON mode.")); + end if; + Length := Caps_Size; Aux_Ch.Aux_Read (Port => Port, -- To view, visit https://review.coreboot.org/c/libgfxinit/+/46631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I3c9e67caf9511d62b19c0c175e8e75080fb7ac7d Gerrit-Change-Number: 46631 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 13

Change in coreboot[master]: WIP: soc/mediatek/mt8192: add apusys init flow
by Chien-Chih Tseng (Code Review) 11 May '21

11 May '21

Chien-Chih Tseng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48622 ) Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ...................................................................... WIP: soc/mediatek/mt8192: add apusys init flow Signed-off-by: Chien-Chih Tseng <chien-chih.tseng(a)mediatek.com> Change-Id: If05a8af1a2f96598adcf70e15003e4f5dc94e337 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/apusys.c A src/soc/mediatek/mt8192/include/soc/apusys.h M src/soc/mediatek/mt8192/soc.c 4 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/48622/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc old mode 100644 new mode 100755 index c01d716..0b23296 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -54,6 +54,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += devapc.c ramstage-y += mcupm.c +ramstage-y += apusys.c ramstage-y += soc.c ramstage-y += sspm.c ramstage-y += ufs.c diff --git a/src/soc/mediatek/mt8192/apusys.c b/src/soc/mediatek/mt8192/apusys.c new file mode 100755 index 0000000..605f1c9 --- /dev/null +++ b/src/soc/mediatek/mt8192/apusys.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <soc/apusys.h> +#include <soc/mtlib_common.h> + +#define INFRA2APU_SRAM_PROT_EN (INFRACFG_AO_BASE + 0xe98) +#define APUSYS_MBOX (0x19000000) + +void apusys_init(void) +{ + write32((void *)INFRA2APU_SRAM_PROT_EN, + read32((void *)INFRA2APU_SRAM_PROT_EN) & (~0xc0000000)); + write32((void *)(APUSYS_MBOX + 0x0b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x1b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x2b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x3b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x4b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x5b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x6b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x7b0), 0x00010001); + + printk(BIOS_INFO, "INFRA2APU_SRAM_PROT_EN = 0x%x\n", + read32((void *)INFRA2APU_SRAM_PROT_EN)); + printk(BIOS_INFO, "0x190000b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x0b0))); + printk(BIOS_INFO, "0x190001b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x1b0))); + printk(BIOS_INFO, "0x190002b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x2b0))); + printk(BIOS_INFO, "0x190003b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x3b0))); + printk(BIOS_INFO, "0x190004b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x4b0))); + printk(BIOS_INFO, "0x190005b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x5b0))); + printk(BIOS_INFO, "0x190006b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x6b0))); + printk(BIOS_INFO, "0x190007b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x7b0))); +} diff --git a/src/soc/mediatek/mt8192/include/soc/apusys.h b/src/soc/mediatek/mt8192/include/soc/apusys.h new file mode 100755 index 0000000..389d1e8 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/apusys.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_APUSYS_H +#define SOC_MEDIATEK_MT8192_APUSYS_H + +#include <soc/addressmap.h> +#include <types.h> + +void apusys_init(void); +#endif /* SOC_MEDIATEK_MT8192_APUSYS_H */ diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c old mode 100644 new mode 100755 index 883f4dc..8c16906 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -4,10 +4,12 @@ #include <soc/devapc.h> #include <soc/emi.h> #include <soc/mcupm.h> +#include <soc/apusys.h> #include <soc/mmu_operations.h> #include <soc/sspm.h> #include <soc/ufs.h> #include <symbols.h> +#include <console/console.h> static void soc_read_resources(struct device *dev) { @@ -17,6 +19,7 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + apusys_init(); dapc_init(); mcupm_init(); sspm_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/48622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If05a8af1a2f96598adcf70e15003e4f5dc94e337 Gerrit-Change-Number: 48622 Gerrit-PatchSet: 1 Gerrit-Owner: Chien-Chih Tseng <chien-chih.tseng(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/riscv: Fixed exception handling when CONFIG_RISCV_WORKING_HARTID...
by Xiang Wang (Code Review) 08 May '21

08 May '21

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37461 ) Change subject: arch/riscv: Fixed exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0 ...................................................................... arch/riscv: Fixed exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0 Change-Id: Ic45560b4bfbf9366425ef4006ac2765113457349 Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M src/arch/riscv/trap_util.S 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/37461/1 diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 8aba48b..8c1f6cc 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -118,6 +118,7 @@ # someday this gets fixed. //csrr sp, mhartid csrr sp, 0xf14 + addi sp, sp, -CONFIG_RISCV_WORKING_HARTID .Lsmp_hang: bnez sp, .Lsmp_hang -- To view, visit https://review.coreboot.org/c/coreboot/+/37461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic45560b4bfbf9366425ef4006ac2765113457349 Gerrit-Change-Number: 37461 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

3 7

Change in libgfxinit[master]: [HACK] Implement more WAs
by Angel Pons (Code Review) 07 May '21

07 May '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/46635 ) Change subject: [HACK] Implement more WAs ...................................................................... [HACK] Implement more WAs Change-Id: I4cd64cf4c1e702dc05709adc345a976a4e3c1ded Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M common/skylake/hw-gfx-gma-power_and_clocks.adb 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/35/46635/1 diff --git a/common/skylake/hw-gfx-gma-power_and_clocks.adb b/common/skylake/hw-gfx-gma-power_and_clocks.adb index c860e1b..1501ea7 100644 --- a/common/skylake/hw-gfx-gma-power_and_clocks.adb +++ b/common/skylake/hw-gfx-gma-power_and_clocks.adb @@ -82,6 +82,9 @@ CNP_PWM_CGE_GATING_DISABLE : constant := 1 * 2 ** 13; + DISP_FBC_MEMORY_WAKE : constant := 1 * 2 ** 31; + DISP_FBC_WM_DIS : constant := 1 * 2 ** 15; + ---------------------------------------------------------------------------- CDCLK_CTL_CD_FREQ_SELECT_MASK : constant := 3 * 2 ** 26; @@ -340,6 +343,13 @@ (Register => Registers.PCH_DSPCLK_GATE_D, Mask => CNP_PWM_CGE_GATING_DISABLE); + -- Display WA #0562 WaFbcTurnOffFbcWatermark:cfl + -- Display WA #0859 WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl + Registers.Set_Mask + (Register => Registers.ARB_CTL, + Mask => DISP_FBC_WM_DIS or + DISP_FBC_MEMORY_WAKE); + Get_Cur_CDClk (Config.CDClk); Get_Max_CDClk (Config.Max_CDClk); Set_CDClk (Config.Default_CDClk_Freq); -- To view, visit https://review.coreboot.org/c/libgfxinit/+/46635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I4cd64cf4c1e702dc05709adc345a976a4e3c1ded Gerrit-Change-Number: 46635 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 11

Change in coreboot[master]: Do-NOT-SUBMIT: mt8192 apusys ToT - Coreboot
by flora.fu＠mediatek.com (Code Review) 06 May '21

06 May '21

flora.fu(a)mediatek.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48626 ) Change subject: Do-NOT-SUBMIT: mt8192 apusys ToT - Coreboot ...................................................................... Do-NOT-SUBMIT: mt8192 apusys ToT - Coreboot For mt8192 apusys development. Signed-off-by: Flora Fu <flora.fu(a)mediatek.com> Change-Id: Ifae98ed97c40e5a384cf3d1c19c0f1656b0cb835 --- M README.md 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/48626/1 diff --git a/README.md b/README.md index d2b1bc8..26c8e34 100644 --- a/README.md +++ b/README.md @@ -103,3 +103,4 @@ This makes the resulting coreboot images licensed under the GPL, version 2. + -- To view, visit https://review.coreboot.org/c/coreboot/+/48626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifae98ed97c40e5a384cf3d1c19c0f1656b0cb835 Gerrit-Change-Number: 48626 Gerrit-PatchSet: 1 Gerrit-Owner: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-MessageType: newchange

1 7

Change in coreboot[master]: [TEST] mb/google/volteer: Update PL1 and PL2 setting on halvor
by John Su (Code Review) 04 May '21

04 May '21

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44630 ) Change subject: [TEST] mb/google/volteer: Update PL1 and PL2 setting on halvor ...................................................................... [TEST] mb/google/volteer: Update PL1 and PL2 setting on halvor This is test patch to update PL1 and PL2 on halvor. Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I26be0031c70264cd652ceb288ade30dd4d0c7c92 --- M src/mainboard/google/volteer/variants/halvor/overridetree.cb 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/44630/1 diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb index c6ac1b7..d85bc3e 100644 --- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb @@ -17,7 +17,32 @@ register "SaGv" = "SaGv_Disabled" + register "power_limits_config[POWER_LIMITS_Y_4_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 15, + }" + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 7000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + + register "controls.power_limits.pl2" = "{ + .min_power = 7000, + .max_power = 15000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + + device generic 0 on end + end + end # DPTF device pci 15.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/44630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26be0031c70264cd652ceb288ade30dd4d0c7c92 Gerrit-Change-Number: 44630 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: HACK: soc/mediatek: Add function to raise the big CPU frequency
by Yidi Lin (Code Review) 03 May '21

03 May '21

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46410 to review the following change. Change subject: HACK: soc/mediatek: Add function to raise the big CPU frequency ...................................................................... HACK: soc/mediatek: Add function to raise the big CPU frequency Implement mt_pll_raise_ca76_freq() in MT8192 to raise the frequency. usage: mt_pll_raise_ca76_freq(2200UL * MHz); Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: I2ebc4c0230e7c42c887bdac227eb366deb743986 --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/pll.c 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/46410/1 diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index d9ba230..54b12e8 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -59,6 +59,7 @@ int pll_set_rate(const struct pll *pll, u32 rate); void mt_pll_init(void); void mt_pll_raise_little_cpu_freq(u32 freq); +void mt_pll_raise_ca76_freq(u32 freq); enum fmeter_type { FMETER_ABIST = 0, diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index 0366cd6..cd65d25 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -546,3 +546,30 @@ return 0; } + +void mt_pll_raise_ca76_freq(u32 freq) +{ + /* enable [4] intermediate clock armpll_divider_pll1_ck */ + setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); + + /* switch ca76 clock source to intermediate clock */ + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, + MCU_MUX_SRC_DIV_PLL1); + + /* disable armpll_bl frequency output */ + clrbits32(plls[APMIXED_ARMPLL_BL].reg, PLL_EN); + + /* raise armpll_bl frequency */ + pll_set_rate(&plls[APMIXED_ARMPLL_BL], freq); + + /* enable armpll_bl frequency output */ + setbits32(plls[APMIXED_ARMPLL_BL].reg, PLL_EN); + udelay(PLL_EN_DELAY); + + /* switch ca76 clock source back to armpll_bl */ + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, + MCU_MUX_SRC_PLL); + + /* disable [4] intermediate clock armpll_divider_pll1_ck */ + clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ebc4c0230e7c42c887bdac227eb366deb743986 Gerrit-Change-Number: 46410 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC] soc/intel/skylake: Introduce new method for setting device states
by Michael Niewöhner (Code Review) 01 May '21

01 May '21

Attention is currently required from: Felix Singer, Nico Huber, Raul Rangel, Furquan Shaikh, Matt DeVillier, Angel Pons, Patrick Rudolph, Felix Held. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52493 ) Change subject: [RFC] soc/intel/skylake: Introduce new method for setting device states ...................................................................... Patch Set 13: (4 comments) File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/52493/comment/d14dace1_cb4ef3da PS13, Line 461: if (!xdci_can_enable()) : params->XdciEnable = 0; params->XdciEnable = xdci_can_enable(); File src/soc/intel/skylake/fspdevmap.c: https://review.coreboot.org/c/coreboot/+/52493/comment/de653e90_2798cf2e PS13, Line 15: devmap[i].inverted ^ dev->enabled nit: I would exchange them, because we're inverting the dev state, not the invert field. File src/soc/intel/skylake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/52493/comment/4b7a83db_2569a7a7 PS13, Line 137: PCH_DEVFN_SMBUS }, : { &m_cfg->EnableTraceHub, PCH alignment https://review.coreboot.org/c/coreboot/+/52493/comment/03ea8207_f0d4c2cc PS13, Line 138: tab -- To view, visit https://review.coreboot.org/c/coreboot/+/52493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70fde306c65a8881f565c5f923be20f380ea64d3 Gerrit-Change-Number: 52493 Gerrit-PatchSet: 13 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 30 Apr 2021 23:53:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Enable support for Chrome OS mode switches
by Felix Held (Code Review) 01 May '21

01 May '21

Attention is currently required from: Anil Kumar K, Shaunak Saha, Maulik V Vaghela, Selma Bensaid, Usha P, Bernardo Perez Priego. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52614 ) Change subject: mb/intel/adlrvp: Enable support for Chrome OS mode switches ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Hi Felix. can u help in fixing the QA job.. […] moving the selection of the two new kconfig options to the ADL_CHROME_EC block below might fix the build failure, since that option gets only selected for the boards with chromeec support and all dependencies should be met for that case. if ADL_INTEL_EC or ADL_CHROME_EC will be selected depends on which board is selected; see line 72 and 73 -- To view, visit https://review.coreboot.org/c/coreboot/+/52614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I771f0ef14b1c273f9d1af22c96de0eabd08e9a8c Gerrit-Change-Number: 52614 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 30 Apr 2021 23:51:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: comment

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