coreboot-gerrit April 2021

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Change in coreboot[master]: mb/lenovo/x220/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 09 Jun '21

09 Jun '21

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37297 ) Change subject: mb/lenovo/x220/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/x220/devicetree: Use subsystemid inheritance Change-Id: Ia9367d03b6f97f1eb8c35045fd7bb79e5f45b535 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/x220/devicetree.cb 1 file changed, 15 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/37297/1 diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 26fa1a4..5ae1427 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -37,13 +37,11 @@ register "pci_mmio_size" = "1024" device domain 0 on - device pci 00.0 on - subsystemid 0x17aa 0x21db - end # host bridge + subsystemid 0x17aa 0x21db inherit + + device pci 00.0 on end # host bridge device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on - subsystemid 0x17aa 0x21db - end # vga controller + device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -80,49 +78,29 @@ device pci 19.0 on subsystemid 0x17aa 0x21ce end # Intel Gigabit Ethernet - device pci 1a.0 on - subsystemid 0x17aa 0x21db - end # USB2 EHCI #2 - device pci 1b.0 on - subsystemid 0x17aa 0x21db - end # High Definition Audio - device pci 1c.0 on - subsystemid 0x17aa 0x21db - end # PCIe Port #1 - device pci 1c.1 on - subsystemid 0x17aa 0x21db - end # PCIe Port #2 (wlan) - device pci 1c.2 on - subsystemid 0x17aa 0x21db - end # PCIe Port #3 + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 (wlan) + device pci 1c.2 on end # PCIe Port #3 device pci 1c.3 on - subsystemid 0x17aa 0x21db smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 device pci 1c.4 on - subsystemid 0x17aa 0x21db chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87" - device pci 00.0 on - subsystemid 0x17aa 0x21fa - end + device pci 00.0 on end end end # PCIe Port #5 (SD) device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on - subsystemid 0x17aa 0x21db - end # PCIe Port #7 + device pci 1c.6 on end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on - subsystemid 0x17aa 0x21db - end # USB2 EHCI #1 + device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on #LPC bridge - subsystemid 0x17aa 0x21db chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end @@ -172,11 +150,8 @@ register "wwan_gpio_lvl" = "0" end end # LPC bridge - device pci 1f.2 on - subsystemid 0x17aa 0x21db - end # SATA Controller 1 + device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on - subsystemid 0x17aa 0x21db # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -190,9 +165,7 @@ end end # SMBus device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on - subsystemid 0x17aa 0x21db - end # Thermal + device pci 1f.6 on end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/37297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9367d03b6f97f1eb8c35045fd7bb79e5f45b535 Gerrit-Change-Number: 37297 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: sb/intel/bd82x6x: Add missing ID for PCI bridge
by James (Code Review) 07 Jun '21

07 Jun '21

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41015 ) Change subject: sb/intel/bd82x6x: Add missing ID for PCI bridge ...................................................................... sb/intel/bd82x6x: Add missing ID for PCI bridge The PCI device ID 0x244e for the "Intel Corporation 82801 PCI Bridge" was missing. Change-Id: I22cdbcf518d86af7b93de7731d175088a81bbc1f Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/southbridge/intel/bd82x6x/pci.c 1 file changed, 9 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/41015/1 diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 459ed46..757bdeb 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -58,8 +58,14 @@ .ops_pci = &pci_ops, }; +static const unsigned short pci_device_ids[] = { + 0x244e, /* Desktop */ + 0x2448, /* Mobile */ + 0 +}; + static const struct pci_driver pch_pci __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x2448, + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/41015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22cdbcf518d86af7b93de7731d175088a81bbc1f Gerrit-Change-Number: 41015 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: soc/intel/xeon_sp/cpx/acpi: Align MADT IO APIC ID's with DMAR
by Arthur Heymans (Code Review) 07 Jun '21

07 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46503 ) Change subject: soc/intel/xeon_sp/cpx/acpi: Align MADT IO APIC ID's with DMAR ...................................................................... soc/intel/xeon_sp/cpx/acpi: Align MADT IO APIC ID's with DMAR In MADT loop over each stack and compare it against the same IO APIC ID table as during the DMAR table generation. This fixes Linux (5.8) warning: "DMAR-IR: [Firmware Bug]: ioapic 12 has no mapping iommu, interrupt remapping will be disabled" Change-Id: I32caf9036f0d548520b30b82324265cd4d0c3b8f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/acpi.c 1 file changed, 42 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/46503/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index a1ebc4a..c7172b2 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -78,49 +78,56 @@ unsigned long acpi_fill_madt(unsigned long current) { - int cur_index; - struct iiostack_resource stack_info = {0}; + int cur_index = 0; + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); /* With CPX-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */ - int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 }; - int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; + const int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 }; + const int IoApicID[] = { + // socket 0 + PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, + PC04_IOAPIC_ID, PC05_IOAPIC_ID, + // socket 1 + PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, + PC10_IOAPIC_ID, PC11_IOAPIC_ID, + }; + + assert(hob != NULL && hob_size != 0); /* Local APICs */ current = xeonsp_acpi_create_madt_lapics(current); - cur_index = 0; - get_iiostack_info(&stack_info); + /* + * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. + * Add entry for PCH IOAPIC. + */ + { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[0].StackRes[0]; + const int gsi_base = gsi_bases[cur_index]; + printk(BIOS_DEBUG, "Adding MADT IOAPIC for PCH: ioapic_id: 0x%x, " + "ioapic_base: 0x%x, gsi_base: 0x%x\n", + PCH_IOAPIC_ID, ri->IoApicBase, gsi_base); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, PCH_IOAPIC_ID, + ri->IoApicBase, gsi_base); + cur_index++; + } - for (int stack = 0; stack < stack_info.no_of_stacks; ++stack) { - const STACK_RES *ri = &stack_info.res[stack]; - assert(cur_index < ARRAY_SIZE(ioapic_ids)); - assert(cur_index < ARRAY_SIZE(gsi_bases)); - int ioapic_id = ioapic_ids[cur_index]; - int gsi_base = gsi_bases[cur_index]; - printk(BIOS_DEBUG, "Adding MADT IOAPIC for stack: %d, ioapic_id: 0x%x, " - "ioapic_base: 0x%x, gsi_base: 0x%x\n", - stack, ioapic_id, ri->IoApicBase, gsi_base); - current += acpi_create_madt_ioapic( - (acpi_madt_ioapic_t *)current, - ioapic_id, ri->IoApicBase, gsi_base); - ++cur_index; - /* - * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. - * Add entry for PCH IOAPIC. - */ - if (stack == 0) { /* PCH IOAPIC */ - assert(cur_index < ARRAY_SIZE(ioapic_ids)); - assert(cur_index < ARRAY_SIZE(gsi_bases)); - ioapic_id = ioapic_ids[cur_index]; - gsi_base = gsi_bases[cur_index]; - printk(BIOS_DEBUG, "Adding MADT IOAPIC for stack: %d, ioapic_id: 0x%x, " - "ioapic_base: 0x%x, gsi_base: 0x%x\n", - stack, ioapic_id, - ri->IoApicBase + 0x1000, gsi_base); - current += acpi_create_madt_ioapic( - (acpi_madt_ioapic_t *)current, - ioapic_id, ri->IoApicBase + 0x1000, gsi_base); + // DRHD + for (int iio = 0; iio < hob->PlatformData.numofIIO; ++iio) { + for (int stack = 0; stack < MAX_IIO_STACK; stack++) { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[iio].StackRes[stack]; + if (ri->Personality != TYPE_UBOX_IIO) + continue; + const int ioapic_id = IoApicID[(iio * MAX_IIO_STACK) + stack]; + const int gsi_base = gsi_bases[cur_index]; + uint32_t apic_base = ri->IoApicBase; + if (iio == 0 && stack == 0) + apic_base += 0x1000; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + ioapic_id, apic_base, gsi_base); ++cur_index; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32caf9036f0d548520b30b82324265cd4d0c3b8f Gerrit-Change-Number: 46503 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST] Enable link time optimization
by Jacob Garber (Code Review) 05 Jun '21

05 Jun '21

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40815 ) Change subject: [TEST] Enable link time optimization ...................................................................... [TEST] Enable link time optimization Enable LTO to shake out the bugs. Current problems: - GCC does not track symbol origins when using LTO, so it must be disabled for AGESA so it can be excluded from the illegal_globals check. - GCC segfaults when compiling ARMV7 - Most of the Google boards do not compile because of a missing reference to _watchdog_tombstone Change-Id: I37474d4adbf653729bb2e631a1ff812b4319c17a Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M src/Kconfig M src/vendorcode/amd/agesa/Makefile.inc 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/40815/1 diff --git a/src/Kconfig b/src/Kconfig index e4821e8..375bca2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -116,7 +116,7 @@ config LTO bool "Use link time optimization (LTO)" - default n + default y depends on COMPILER_GCC help Compile with link time optimization. This can often decrease the diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index b96af84..3e4a53c 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -14,6 +14,12 @@ AGESA_CFLAGS := -march=k8-sse3 -mtune=k8-sse3 -fno-strict-aliasing +# GCC currently does not track symbol origins when using LTO, so +# AGESA gets caught in the illegal_globals check. Disable for now. +ifeq ($(CONFIG_LTO),y) +AGESA_CFLAGS += -fno-lto +endif + CFLAGS_x86_32 += $(AGESA_CFLAGS) CFLAGS_x86_64 += $(AGESA_CFLAGS) -- To view, visit https://review.coreboot.org/c/coreboot/+/40815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37474d4adbf653729bb2e631a1ff812b4319c17a Gerrit-Change-Number: 40815 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE
by Subrata Banik (Code Review) 05 Jun '21

05 Jun '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44014 ) Change subject: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE ...................................................................... src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE This patch ensures that the TSEG region is only mapped as cacheable so that one can perform SMRAM relocation faster. Ideally don't need to mark the entire TOP_OF_RAM till BGSM range (used for ME stolen memory, PTT, DPR, PRMRR, TSEG etc) as cacheable as no executable code exist there except TSEG region. Hence only mark TSEG range as cacheable (+ reserved) and other ranges as reserve alone. TEST=Able to build and boot ICL, TGL RVP. Without this CL: PCI: 00:00.0 resource base 77000000 size 4800000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index a With this CL: PCI: 00:00.0 resource base 77000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 9 PCI: 00:00.0 resource base 7b000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index a PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index b Change-Id: I64c14b14caf0a53219fdc02ec6bbd375955a0c8e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44014/1 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e12e07c..b15ca01 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -173,8 +173,13 @@ sa_get_mem_map(dev, &sa_map_values[0]); - /* top_of_ram -> BGSM */ + /* top_of_ram -> TSEG */ base_k = top_of_ram; + size_k = sa_map_values[SA_TSEG_REG] - base_k; + mmio_resource(dev, index++, base_k / KiB, size_k / KiB); + + /* TSEG -> BGSM */ + base_k = sa_map_values[SA_TSEG_REG]; size_k = sa_map_values[SA_BGSM_REG] - base_k; reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB); -- To view, visit https://review.coreboot.org/c/coreboot/+/44014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64c14b14caf0a53219fdc02ec6bbd375955a0c8e Gerrit-Change-Number: 44014 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Add KASAN stubs to coreboot.
by Abdullah Zafar (Code Review) 04 Jun '21

04 Jun '21

Abdullah Zafar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32231 Change subject: Add KASAN stubs to coreboot. ...................................................................... Add KASAN stubs to coreboot. Add option in Kconfig to compile with KASAN. Modify src/lib/Makefile.inc to enable gcc KASAN. Remove lint errors and warnings from kasan.c. Signed-off-by: 11abdullah11 <abdullahzafar4876(a)yahoo.com> Changes to be committed: modified: src/Kconfig modified: src/lib/Makefile.inc new file: src/lib/kasan.c Change-Id: Id13970514e37dfffb751391fb3e7e6b53ccc7577 --- M src/Kconfig M src/lib/Makefile.inc A src/lib/kasan.c 3 files changed, 45 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32231/1 diff --git a/src/Kconfig b/src/Kconfig index 62b3818..96e746e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -219,6 +219,15 @@ coverage information in CBMEM for extraction from user space. If unsure, say N. +config KASAN + bool "Kernel Address sanitizer support" + default y + help + Instrument the code with checks for UAF and OOB erros. If unsure, + say N because it adds a small performance penalty and may abort + on code that happens to work in spite of the UB. + + config UBSAN bool "Undefined behavior sanitizer support" default n diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1350152..88afaaa 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -19,6 +19,12 @@ CFLAGS_ramstage += -fsanitize=undefined endif +ifeq ($(CONFIG_KASAN),y) +ramstage-y += kasan.c +CFLAGS_ramstage += -fsanitize=kernel-address +endif + + decompressor-y += decompressor.c $(call src-to-obj,decompressor,$(dir)/decompressor.c): $(objcbfs)/bootblock.lz4 $(call src-to-obj,decompressor,$(dir)/decompressor.c): CCACHE_EXTRAFILES=$(objcbfs)/bootblock.lz4 @@ -83,7 +89,7 @@ romstage-y += memrange.c romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c -romstage-y += ramtest.c +romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c ramstage-y += region_file.c romstage-y += region_file.c diff --git a/src/lib/kasan.c b/src/lib/kasan.c new file mode 100644 index 0000000..3f482e9 --- /dev/null +++ b/src/lib/kasan.c @@ -0,0 +1,29 @@ +#include <stddef.h> + +/* + *Empty stubs for required by gcc to add compiler code + */ +void __asan_handle_no_return(void); +void __asan_load1_noabort(unsigned long addr); +void __asan_store1_noabort(unsigned long addr); +void __asan_load2_noabort(unsigned long addr); +void __asan_store2_noabort(unsigned long addr); +void __asan_load4_noabort(unsigned long addr); +void __asan_store4_noabort(unsigned long addr); +void __asan_load8_noabort(unsigned long addr); +void __asan_store8_noabort(unsigned long addr); +void __asan_loadN_noabort(unsigned long addr, size_t x); +void __asan_storeN_noabort(unsigned long addr, size_t x); + + +void __asan_handle_no_return(void) { } +void __asan_load1_noabort(unsigned long addr) { } +void __asan_store1_noabort(unsigned long addr) { } +void __asan_load2_noabort(unsigned long addr) { } +void __asan_store2_noabort(unsigned long addr) { } +void __asan_load4_noabort(unsigned long addr) { } +void __asan_store4_noabort(unsigned long addr) { } +void __asan_store8_noabort(unsigned long addr) { } +void __asan_load8_noabort(unsigned long addr) { } +void __asan_loadN_noabort(unsigned long addr, size_t i) { } +void __asan_storeN_noabort(unsigned long addr, size_t i) { } -- To view, visit https://review.coreboot.org/c/coreboot/+/32231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id13970514e37dfffb751391fb3e7e6b53ccc7577 Gerrit-Change-Number: 32231 Gerrit-PatchSet: 1 Gerrit-Owner: Abdullah Zafar <abdullahzafar4876(a)yahoo.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST]3rdparty/vboot: Vboot version update
by Wonkyu Kim (Code Review) 03 Jun '21

03 Jun '21

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39447 ) Change subject: [TEST]3rdparty/vboot: Vboot version update ...................................................................... [TEST]3rdparty/vboot: Vboot version update Update Vboot version to bb6c23472a0f to fix depthcharge build Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: Ibe5d13fff9730229818cd2201c55b794ba69c5ea --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/39447/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index 5059062..bb6c234 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 5059062dd352e3864fb68f8a061e87bd7055d12a +Subproject commit bb6c23472a0fd0565b3991331b63a4ed319d7872 -- To view, visit https://review.coreboot.org/c/coreboot/+/39447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe5d13fff9730229818cd2201c55b794ba69c5ea Gerrit-Change-Number: 39447 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Make changes to support S3
by Duncan Laurie (Code Review) 03 Jun '21

03 Jun '21

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48682 ) Change subject: soc/intel/common/block/pcie/rtd3: Make changes to support S3 ...................................................................... soc/intel/common/block/pcie/rtd3: Make changes to support S3 The RTD3 ACPI _ON method will unconditionally attempt to re-initialize the device, setting up GPIOs, clocks, and the L23 ready exit flow. When using S3 instead of S0ix this work is not needed and instead results in the device disappearing and the resume failing in the OS. BUG=b:174776411 TEST=test S3 and S0ix on volteer device with both NVMe and SD using the RTD3 driver to ensure suspend/resume works in both cases. Change-Id: I6bd7d001890939850381858fe663366472aacefc --- M src/soc/intel/common/block/pcie/rtd3/rtd3.c 1 file changed, 36 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/48682/1 diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index be412e7..52a7d03 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -74,12 +74,46 @@ acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_SAVE_STATE); } +static void pcie_rtd3_check_gpio(const struct soc_intel_common_block_pcie_rtd3_config *config) +{ + const struct acpi_gpio *gpio; + + /* Use enable GPIO for status if provided, otherwise use reset GPIO. */ + if (config->enable_gpio.pin_count) + gpio = &config->enable_gpio; + else + gpio = &config->reset_gpio; + + /* Read current GPIO value into Local0. */ + acpigen_get_tx_gpio(gpio); + + /* Ensure check works for both active low and active high GPIOs. */ + acpigen_write_store_int_to_op(gpio->active_low, LOCAL1_OP); + + acpigen_write_if_lequal_op_op(LOCAL0_OP, LOCAL1_OP); + acpigen_write_store_int_to_op(0, LOCAL0_OP); + acpigen_pop_len(); /* If */ + acpigen_write_else(); + acpigen_write_store_int_to_op(1, LOCAL0_OP); + acpigen_pop_len(); /* Else */ +} + static void pcie_rtd3_acpi_method_on(unsigned int pcie_rp, const struct soc_intel_common_block_pcie_rtd3_config *config) { acpigen_write_method_serialized("_ON", 0); + /* + * Exit early if device status GPIOs indicate device is already in the on/ready state. + * This will happen if S3 resume is used instead of S0ix resume where coreboot has + * already re-initalized the device and the ACPI code does not need to run. + */ + pcie_rtd3_check_gpio(config); + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + acpigen_write_return_op(ZERO_OP); + acpigen_pop_len(); /* If */ + /* Assert enable GPIO to turn on device power. */ if (config->enable_gpio.pin_count) { acpigen_enable_tx_gpio(&config->enable_gpio); @@ -140,28 +174,10 @@ pcie_rtd3_acpi_method_status(int pcie_rp, const struct soc_intel_common_block_pcie_rtd3_config *config) { - const struct acpi_gpio *gpio; - acpigen_write_method("_STA", 0); - /* Use enable GPIO for status if provided, otherwise use reset GPIO. */ - if (config->enable_gpio.pin_count) - gpio = &config->enable_gpio; - else - gpio = &config->reset_gpio; - - /* Read current GPIO value into Local0. */ - acpigen_get_tx_gpio(gpio); - - /* Ensure check works for both active low and active high GPIOs. */ - acpigen_write_store_int_to_op(gpio->active_low, LOCAL1_OP); - - acpigen_write_if_lequal_op_op(LOCAL0_OP, LOCAL1_OP); - acpigen_write_return_op(ZERO_OP); - acpigen_pop_len(); /* If */ - acpigen_write_else(); - acpigen_write_return_op(ONE_OP); - acpigen_pop_len(); /* Else */ + pcie_rtd3_check_gpio(config); + acpigen_write_return_op(LOCAL0_OP); acpigen_pop_len(); /* Method */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/48682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bd7d001890939850381858fe663366472aacefc Gerrit-Change-Number: 48682 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST]mb/emulation/qemu-q35: select X86_SMM_LOADER_VERSION2
by Arthur Heymans (Code Review) 02 Jun '21

02 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48301 ) Change subject: [TEST]mb/emulation/qemu-q35: select X86_SMM_LOADER_VERSION2 ...................................................................... [TEST]mb/emulation/qemu-q35: select X86_SMM_LOADER_VERSION2 SMM_LOADER_VERSION2 has some quirks that need to be ironed out first. Change-Id: I2f7420dae432ef1cb9554592ae334e17f8a7abc8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/emulation/qemu-q35/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/48301/1 diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index edd2b2c..ddf3479 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -15,6 +15,7 @@ select MAINBOARD_FORCE_NATIVE_VGA_INIT if !CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_CHROMEOS + select X86_SMM_LOADER_VERSION2 config VBOOT select VBOOT_MUST_REQUEST_DISPLAY -- To view, visit https://review.coreboot.org/c/coreboot/+/48301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f7420dae432ef1cb9554592ae334e17f8a7abc8 Gerrit-Change-Number: 48301 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/emulation/qemu-q35: Add support for SMM_TSEG with parallel MP init
by Arthur Heymans (Code Review) 02 Jun '21

02 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48262 ) Change subject: mb/emulation/qemu-q35: Add support for SMM_TSEG with parallel MP init ...................................................................... mb/emulation/qemu-q35: Add support for SMM_TSEG with parallel MP init Change-Id: I612cebcd2ddef809434eb9bfae9d8681cda112ef Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/qemu-x86/Kconfig M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/emulation/qemu-q35/Makefile.inc A src/mainboard/emulation/qemu-q35/cpu.c M src/mainboard/emulation/qemu-q35/memmap.c 5 files changed, 92 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/48262/1 diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 641cea8..0f59b9c 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -36,9 +36,10 @@ depends on !PARALLEL_MP select SMM_ASEG -#config CPU_QEMU_X86_TSEG_SMM -# bool "SMM in TSEG" -# select SMM_TSEG +config CPU_QEMU_X86_TSEG_SMM + bool "SMM in TSEG" + select SMM_TSEG + depends on PARALLEL_MP endchoice diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index f49d47da..7ee38d3 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -249,9 +249,15 @@ .get_cpu_count = fw_cfg_max_cpus, }; +extern const struct mp_ops mp_ops_with_smm; + void mp_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops_no_smm)) + const struct mp_ops *ops = &mp_ops_no_smm; + if (CONFIG(SMM_TSEG)) + ops = &mp_ops_with_smm; + + if (mp_init_with_smm(cpu_bus, ops)) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index 4bd91f0..f717405 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -13,6 +13,7 @@ ramstage-y += ../qemu-i440fx/memmap.c ramstage-y += ../qemu-i440fx/northbridge.c ramstage-y += memmap.c +ramstage-y += cpu.c verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c diff --git a/src/mainboard/emulation/qemu-q35/cpu.c b/src/mainboard/emulation/qemu-q35/cpu.c new file mode 100644 index 0000000..c0f4ee5 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/cpu.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <cpu/x86/mp.h> +#include <stdint.h> +#include <cpu/intel/smm_reloc.h> +#include <cpu/amd/amd64_save_state.h> +#include <mainboard/emulation/qemu-i440fx/fw_cfg.h> + +static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) +{ + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + +// *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); + *smm_save_state_size = 0x400; + printk(BIOS_DEBUG, "Save state size: 0x%lx bytes\n", *smm_save_state_size); +} + +static void per_cpu_smm_trigger(void) +{ + /* Relocate SMM space. */ + smm_initiate_relocation(); +} + +/* The relocation work is actually performed in SMM context, but the code + * resides in the ramstage module. This occurs by trampolining from the default + * SMRAM entry point to here. */ +static void relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) +{ + /* The em64t101 save state is sufficiently compatible with older + save states with regards of smbase, smm_revision. */ + amd64_smm_state_save_area_t *save_state; + u32 smbase = staggered_smbase; + + save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state)); + save_state->smbase = smbase; + + printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); + printk(BIOS_SPEW, "SMM revision: 0x%08x\n", save_state->smm_revision); + printk(BIOS_DEBUG, "New SMBASE=0x%08x\n", smbase); +} + +static void post_mp_init(void) +{ + /* Now that all APs have been relocated as well as the BSP let SMIs + * start flowing. */ + global_smi_enable(); + + /* Lock down the SMRAM space. */ + smm_lock(); +} + +const struct mp_ops mp_ops_with_smm = { + .get_cpu_count = fw_cfg_max_cpus, + .get_smm_info = get_smm_info, + .pre_mp_smm_init = smm_southbridge_clear_state, + .per_cpu_smm_trigger = per_cpu_smm_trigger, + .relocation_handler = relocation_handler, + .post_mp_init = post_mp_init, +}; diff --git a/src/mainboard/emulation/qemu-q35/memmap.c b/src/mainboard/emulation/qemu-q35/memmap.c index c288680..04cf285 100644 --- a/src/mainboard/emulation/qemu-q35/memmap.c +++ b/src/mainboard/emulation/qemu-q35/memmap.c @@ -2,14 +2,17 @@ #define __SIMPLE_DEVICE__ +#include <console/console.h> #include <cpu/x86/smm.h> #include <device/pci_ops.h> #include <mainboard/emulation/qemu-i440fx/memory.h> #include <mainboard/emulation/qemu-i440fx/fw_cfg.h> +#include <cpu/intel/smm_reloc.h> #define EXT_TSEG_MBYTES 0x50 #define SMRAMC 0x9d +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) #define G_SMRAME (1 << 3) #define D_LCK (1 << 4) #define D_CLS (1 << 5) @@ -40,3 +43,16 @@ *start = qemu_get_memory_size() * KiB - *size; printk(BIOS_SPEW, "SMM_BASE: 0x%08lx, SMM_SIZE: %ld MiB\n", *start, *size / MiB); } + +void smm_lock(void) +{ + /* LOCK the SMM memory window and enable normal SMM. + * After running this function, only a full reset can + * make the SMM registers writable again. + */ + printk(BIOS_DEBUG, "Locking SMM.\n"); + + pci_or_config8(PCI_DEV(0, 0, 0), ESMRAMC, T_EN); + pci_write_config8(PCI_DEV(0, 0, 0), SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/48262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I612cebcd2ddef809434eb9bfae9d8681cda112ef Gerrit-Change-Number: 48262 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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