coreboot-gerrit April 2021

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Change in coreboot[master]: cpu/x86: Introduce `CPU_X86_MTRR`
by Angel Pons (Code Review) 26 Oct '21

26 Oct '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44230 ) Change subject: cpu/x86: Introduce `CPU_X86_MTRR` ...................................................................... cpu/x86: Introduce `CPU_X86_MTRR` There's no need for relative paths with Kconfig options. Change-Id: I743eaac99a85a5c712241ba48a320243c5a51f76 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/amd/agesa/family14/Kconfig M src/cpu/amd/agesa/family14/Makefile.inc M src/cpu/amd/agesa/family15tn/Kconfig M src/cpu/amd/agesa/family15tn/Makefile.inc M src/cpu/amd/agesa/family16kb/Kconfig M src/cpu/amd/agesa/family16kb/Makefile.inc M src/cpu/amd/pi/00630F01/Kconfig M src/cpu/amd/pi/00630F01/Makefile.inc M src/cpu/amd/pi/00660F01/Kconfig M src/cpu/amd/pi/00660F01/Makefile.inc M src/cpu/amd/pi/00730F01/Kconfig M src/cpu/amd/pi/00730F01/Makefile.inc M src/cpu/intel/haswell/Kconfig M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/slot_1/Kconfig M src/cpu/intel/slot_1/Makefile.inc M src/cpu/intel/socket_441/Kconfig M src/cpu/intel/socket_441/Makefile.inc M src/cpu/intel/socket_BGA956/Kconfig M src/cpu/intel/socket_BGA956/Makefile.inc M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_FCBGA559/Makefile.inc M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_LGA775/Makefile.inc M src/cpu/intel/socket_m/Kconfig M src/cpu/intel/socket_m/Makefile.inc M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/intel/socket_mPGA604/Makefile.inc M src/cpu/intel/socket_p/Kconfig M src/cpu/intel/socket_p/Makefile.inc M src/cpu/qemu-x86/Kconfig M src/cpu/qemu-x86/Makefile.inc M src/cpu/x86/Kconfig M src/cpu/x86/Makefile.inc M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/Makefile.inc M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/Makefile.inc M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/quark/Kconfig M src/soc/intel/quark/Makefile.inc M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/skx/Makefile.inc 67 files changed, 37 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/44230/1 diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index b9354c1..ecf8175 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -4,6 +4,7 @@ bool select CPU_X86_CACHE select CPU_X86_LAPIC + select CPU_X86_MTRR select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY14 diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index fbde30e..7dbb065 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -8,6 +8,5 @@ subdirs-y += ../../mtrr subdirs-y += ../../../x86/tsc -subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 7b83c0c..525677c 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -4,6 +4,7 @@ bool select CPU_X86_CACHE select CPU_X86_LAPIC + select CPU_X86_MTRR select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY15_TN diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index abc8609..357e80b 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -11,6 +11,5 @@ subdirs-y += ../../mtrr subdirs-y += ../../smm subdirs-y += ../../../x86/tsc -subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index 0b31d7b..f87f241 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -4,6 +4,7 @@ bool select CPU_X86_CACHE select CPU_X86_LAPIC + select CPU_X86_MTRR select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY16_KB diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc index d22a6b7..b110dec 100644 --- a/src/cpu/amd/agesa/family16kb/Makefile.inc +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -8,6 +8,5 @@ subdirs-y += ../../mtrr subdirs-y += ../../../x86/tsc -subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index 1b7423f..66df66d 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -4,6 +4,7 @@ bool select CPU_X86_CACHE select CPU_X86_LAPIC + select CPU_X86_MTRR select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00630F01 diff --git a/src/cpu/amd/pi/00630F01/Makefile.inc b/src/cpu/amd/pi/00630F01/Makefile.inc index abc8609..357e80b 100644 --- a/src/cpu/amd/pi/00630F01/Makefile.inc +++ b/src/cpu/amd/pi/00630F01/Makefile.inc @@ -11,6 +11,5 @@ subdirs-y += ../../mtrr subdirs-y += ../../smm subdirs-y += ../../../x86/tsc -subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index 3f41e5a..dff7a44 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -4,6 +4,7 @@ bool select CPU_X86_CACHE select CPU_X86_LAPIC + select CPU_X86_MTRR select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00660F01 diff --git a/src/cpu/amd/pi/00660F01/Makefile.inc b/src/cpu/amd/pi/00660F01/Makefile.inc index a19ca89..6a2ab03 100644 --- a/src/cpu/amd/pi/00660F01/Makefile.inc +++ b/src/cpu/amd/pi/00660F01/Makefile.inc @@ -7,6 +7,5 @@ subdirs-y += ../../mtrr subdirs-y += ../../../x86/tsc -subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index f809f3f..25b72a7 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -4,6 +4,7 @@ bool select CPU_X86_CACHE select CPU_X86_LAPIC + select CPU_X86_MTRR select X86_AMD_FIXED_MTRRS select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_UNDISCLOSED diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index a95bb4b..ea06ced 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -9,6 +9,5 @@ subdirs-y += ../../mtrr subdirs-y += ../../../x86/tsc -subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae subdirs-y += ../../../x86/smm diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index a026108..8e40c73 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -11,6 +11,7 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select CPU_X86_LAPIC + select CPU_X86_MTRR select MMX select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index ddcc51d..247c266 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -15,7 +15,6 @@ subdirs-y += ../microcode subdirs-y += ../turbo -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/smm subdirs-y += ../../x86/tsc diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 0ed4338..289aa62 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -11,6 +11,7 @@ select ARCH_RAMSTAGE_X86_32 select CPU_X86_CACHE select CPU_X86_LAPIC + select CPU_X86_MTRR select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index e8c4924..99ef0ed 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -14,7 +14,6 @@ subdirs-y += ../microcode subdirs-y += ../smm/gen1 subdirs-y += ../turbo -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/name subdirs-y += ../../x86/smm subdirs-y += ../../x86/tsc diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 61c8da2..500a717 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -11,6 +11,7 @@ select ARCH_RAMSTAGE_X86_32 select CPU_X86_CACHE select CPU_X86_LAPIC + select CPU_X86_MTRR select MMX select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index 8488a8f..5d44eef 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -18,7 +18,6 @@ subdirs-y += ../microcode subdirs-y += ../smm/gen1 subdirs-y += ../turbo -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/name subdirs-y += ../../x86/smm subdirs-y += ../../x86/tsc diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 689def0..8d0804e 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -13,6 +13,7 @@ select CPU_INTEL_MODEL_6BX select CPU_INTEL_MODEL_6XX select CPU_X86_LAPIC + select CPU_X86_MTRR select NO_SMM select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index f44757a..de4dae6 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -8,7 +8,6 @@ subdirs-y += ../model_68x subdirs-y += ../model_6bx subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/smm subdirs-y += ../microcode diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index bf16db7..5852a10 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -7,6 +7,7 @@ def_bool y select CPU_INTEL_MODEL_106CX select CPU_X86_LAPIC + select CPU_X86_MTRR select MMX select SSE select SETUP_XIP_CACHE diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc index e69ef26..c5b3223 100644 --- a/src/cpu/intel/socket_441/Makefile.inc +++ b/src/cpu/intel/socket_441/Makefile.inc @@ -10,6 +10,5 @@ subdirs-y += ../hyperthreading subdirs-y += ../microcode subdirs-y += ../speedstep -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/smm subdirs-y += ../../x86/tsc diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index b986c4c..9862038 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -2,6 +2,7 @@ bool select CPU_INTEL_MODEL_1067X select CPU_X86_LAPIC + select CPU_X86_MTRR select MMX select SSE diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc index 17aa3d1..de3c201 100644 --- a/src/cpu/intel/socket_BGA956/Makefile.inc +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -10,6 +10,5 @@ subdirs-y += ../hyperthreading subdirs-y += ../microcode subdirs-y += ../speedstep -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/smm subdirs-y += ../../x86/tsc diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index ff258e7..b79427e 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -9,6 +9,7 @@ def_bool y select CPU_INTEL_MODEL_106CX select CPU_X86_LAPIC + select CPU_X86_MTRR select MMX select SSE select CPU_HAS_L2_ENABLE_MSR diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 26e58b1..47dd01d 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -10,6 +10,5 @@ subdirs-y += ../hyperthreading subdirs-y += ../microcode subdirs-y += ../speedstep -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/smm subdirs-y += ../../x86/tsc diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 4ac9060..9b039fc 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -10,6 +10,7 @@ select CPU_INTEL_MODEL_F4X select CPU_INTEL_MODEL_1067X select CPU_X86_LAPIC + select CPU_X86_MTRR select MMX select SSE select SIPI_VECTOR_IN_ROM diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index cb69052..cfe19d1 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -14,6 +14,5 @@ subdirs-y += ../hyperthreading subdirs-y += ../microcode subdirs-y += ../speedstep -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/smm subdirs-y += ../../x86/tsc diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index ad9c473..1860ff1 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -8,6 +8,7 @@ select CPU_INTEL_MODEL_6EX select CPU_INTEL_MODEL_6FX select CPU_X86_LAPIC + select CPU_X86_MTRR select MMX select SSE diff --git a/src/cpu/intel/socket_m/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc index a77514e..7f814cc 100644 --- a/src/cpu/intel/socket_m/Makefile.inc +++ b/src/cpu/intel/socket_m/Makefile.inc @@ -11,6 +11,5 @@ subdirs-y += ../hyperthreading subdirs-y += ../microcode subdirs-y += ../speedstep -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/smm subdirs-y += ../../x86/tsc diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 03e910a..bc3f5ba 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -7,6 +7,7 @@ def_bool y select CPU_INTEL_MODEL_F2X select CPU_X86_LAPIC + select CPU_X86_MTRR select MMX select SSE select UDELAY_TSC diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 1e160d0..6d8b838 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -1,6 +1,5 @@ subdirs-y += ../model_f2x subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig index 5755d6b..506fbeb 100644 --- a/src/cpu/intel/socket_p/Kconfig +++ b/src/cpu/intel/socket_p/Kconfig @@ -3,6 +3,7 @@ select CPU_INTEL_MODEL_1067X select CPU_INTEL_MODEL_6FX select CPU_X86_LAPIC + select CPU_X86_MTRR select MMX select SSE diff --git a/src/cpu/intel/socket_p/Makefile.inc b/src/cpu/intel/socket_p/Makefile.inc index 7692987..3974e1c 100644 --- a/src/cpu/intel/socket_p/Makefile.inc +++ b/src/cpu/intel/socket_p/Makefile.inc @@ -11,6 +11,5 @@ subdirs-y += ../hyperthreading subdirs-y += ../microcode subdirs-y += ../speedstep -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/smm subdirs-y += ../../x86/tsc diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index bf5bac3..ad130f2 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -7,6 +7,7 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select CPU_X86_LAPIC + select CPU_X86_MTRR select SMP select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index 5f54262..c3d0aad 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -7,6 +7,5 @@ ramstage-y += qemu.c -subdirs-y += ../x86/mtrr subdirs-y += ../x86/smm subdirs-y += ../x86/tsc diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 334fd95..617e093 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -6,6 +6,10 @@ bool default n +config CPU_X86_MTRR + bool + default n + # TODO These two options look too similar config PARALLEL_CPU_INIT bool diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 8b4f522..0dccdff 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1,6 +1,7 @@ subdirs-y += pae subdirs-$(CONFIG_CPU_X86_CACHE) += cache subdirs-$(CONFIG_CPU_X86_LAPIC) += lapic +subdirs-$(CONFIG_CPU_X86_MTRR) += lapic subdirs-$(CONFIG_PARALLEL_MP) += name ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-y += backup_default_smm.c diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index bee9ec6..3d3968b 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -14,6 +14,7 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select CPU_X86_LAPIC + select CPU_X86_MTRR select RESET_VECTOR_IN_RAM select X86_AMD_FIXED_MTRRS select X86_AMD_INIT_SIPI diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index c4a0f54..3b2b497 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../../../cpu/amd/mtrr/ subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/pae subdirs-y += ../../../cpu/x86/smm subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index b88d031..ac629fd 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -14,6 +14,7 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select CPU_X86_LAPIC + select CPU_X86_MTRR select X86_AMD_FIXED_MTRRS select ACPI_AMD_HARDWARE_SLEEP_VALUES select COLLECT_TIMESTAMPS_NO_TSC diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 4c9ea38..2019fb0 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../../../cpu/amd/mtrr/ subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/pae subdirs-y += ../../../cpu/x86/smm diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 62b984a..2421d26 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -30,6 +30,7 @@ # CPU specific options select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_X86_LAPIC + select CPU_X86_MTRR select IOAPIC select PCR_COMMON_IOSF_1_0 select SMP diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index fe62311..5e58538 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 39da73d..3ac33cf 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -15,6 +15,7 @@ select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_X86_LAPIC + select CPU_X86_MTRR select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 17cc9cf..a2e4340 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -1,7 +1,6 @@ ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 65f5b62..b02f4f3 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -15,6 +15,7 @@ select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_X86_LAPIC + select CPU_X86_MTRR select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select HAVE_SMI_HANDLER diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index b8f5abe..701424b 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -1,7 +1,6 @@ ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 69ab95b..515026b 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -18,6 +18,7 @@ select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_X86_LAPIC + select CPU_X86_MTRR select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 3a18110..da42f35 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,7 +1,6 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index ac7b87d..a77a8a1 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -68,6 +68,7 @@ select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_X86_LAPIC + select CPU_X86_MTRR select FSP_COMPRESS_FSP_S_LZMA select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 979dccc..ec4e82b 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/common diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index e8a68d1..7532ccb 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -16,6 +16,7 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CPU_X86_LAPIC + select CPU_X86_MTRR select DEBUG_GPIO select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index 9e3e1a8..3bd2106 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 02300a8..b2cf82d 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -17,6 +17,7 @@ select CACHE_MRC_SETTINGS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_X86_LAPIC + select CPU_X86_MTRR select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 8ecb332..8ae39f7 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index eed1b02..eb34598 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -18,6 +18,7 @@ select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_X86_LAPIC + select CPU_X86_MTRR select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 0b27e2c..f87d0fd 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 6571eb2..fa6861e 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -13,6 +13,7 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select CPU_X86_MTRR select NO_MMCONF_SUPPORT select REG_SCRIPT select PLATFORM_USES_FSP2_0 diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 387884a..5800e04 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_QUARK),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/esram_init.S diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 13e52cd..37ae68d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -30,6 +30,7 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_COMMON_HYPERTHREADING select CPU_X86_LAPIC + select CPU_X86_MTRR select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 62dbf7d..c858d1e 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 25ee119..8c73d76 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -18,6 +18,7 @@ select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_X86_LAPIC + select CPU_X86_MTRR select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 23af5fe..27b62a0 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 5aa058d..540212c 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -31,6 +31,7 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CPU_X86_LAPIC + select CPU_X86_MTRR select POSTCAR_CONSOLE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index 04972ee..59ca104 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y) subdirs-y += ../../../../cpu/intel/turbo -subdirs-y += ../../../../cpu/x86/mtrr subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/intel/microcode diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc index 657136f..db29e1c 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.inc +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../../../../cpu/intel/microcode subdirs-y += ../../../../cpu/intel/turbo -subdirs-y += ../../../../cpu/x86/mtrr subdirs-y += ../../../../cpu/x86/tsc subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm -- To view, visit https://review.coreboot.org/c/coreboot/+/44230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I743eaac99a85a5c712241ba48a320243c5a51f76 Gerrit-Change-Number: 44230 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: cpu/x86: Introduce `CPU_X86_SMM`
by Angel Pons (Code Review) 25 Oct '21

25 Oct '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44231 ) Change subject: cpu/x86: Introduce `CPU_X86_SMM` ...................................................................... cpu/x86: Introduce `CPU_X86_SMM` There's no need for relative paths with Kconfig options. Change-Id: I478d3fd37d9f9c0daa4a704fdf5ba92b2028bf43 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/amd/agesa/family14/Kconfig M src/cpu/amd/agesa/family14/Makefile.inc M src/cpu/amd/agesa/family15tn/Kconfig M src/cpu/amd/agesa/family15tn/Makefile.inc M src/cpu/amd/agesa/family16kb/Kconfig M src/cpu/amd/agesa/family16kb/Makefile.inc M src/cpu/amd/pi/00630F01/Kconfig M src/cpu/amd/pi/00630F01/Makefile.inc M src/cpu/amd/pi/00660F01/Kconfig M src/cpu/amd/pi/00660F01/Makefile.inc M src/cpu/amd/pi/00730F01/Kconfig M src/cpu/amd/pi/00730F01/Makefile.inc M src/cpu/intel/haswell/Kconfig M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/slot_1/Kconfig M src/cpu/intel/slot_1/Makefile.inc M src/cpu/intel/socket_441/Kconfig M src/cpu/intel/socket_441/Makefile.inc M src/cpu/intel/socket_BGA956/Kconfig M src/cpu/intel/socket_BGA956/Makefile.inc M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_FCBGA559/Makefile.inc M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_LGA775/Makefile.inc M src/cpu/intel/socket_m/Kconfig M src/cpu/intel/socket_m/Makefile.inc M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/intel/socket_mPGA604/Makefile.inc M src/cpu/intel/socket_p/Kconfig M src/cpu/intel/socket_p/Makefile.inc M src/cpu/qemu-x86/Kconfig M src/cpu/qemu-x86/Makefile.inc M src/cpu/x86/Kconfig M src/cpu/x86/Makefile.inc M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/Makefile.inc M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/Makefile.inc M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.inc 64 files changed, 36 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/44231/1 diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index ecf8175..de8e326 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -5,6 +5,7 @@ select CPU_X86_CACHE select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY14 diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 7dbb065..9576708 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -9,4 +9,3 @@ subdirs-y += ../../mtrr subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/pae -subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 525677c..df7ac26 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -5,6 +5,7 @@ select CPU_X86_CACHE select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY15_TN diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 357e80b..1d5779d 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -12,4 +12,3 @@ subdirs-y += ../../smm subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/pae -subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index f87f241..0cafdf5 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -5,6 +5,7 @@ select CPU_X86_CACHE select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY16_KB diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc index b110dec..d775c54 100644 --- a/src/cpu/amd/agesa/family16kb/Makefile.inc +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -9,4 +9,3 @@ subdirs-y += ../../mtrr subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/pae -subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index 66df66d..65f66df 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -5,6 +5,7 @@ select CPU_X86_CACHE select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00630F01 diff --git a/src/cpu/amd/pi/00630F01/Makefile.inc b/src/cpu/amd/pi/00630F01/Makefile.inc index 357e80b..1d5779d 100644 --- a/src/cpu/amd/pi/00630F01/Makefile.inc +++ b/src/cpu/amd/pi/00630F01/Makefile.inc @@ -12,4 +12,3 @@ subdirs-y += ../../smm subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/pae -subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index dff7a44..4b7a665 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -5,6 +5,7 @@ select CPU_X86_CACHE select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00660F01 diff --git a/src/cpu/amd/pi/00660F01/Makefile.inc b/src/cpu/amd/pi/00660F01/Makefile.inc index 6a2ab03..bcbc7fe 100644 --- a/src/cpu/amd/pi/00660F01/Makefile.inc +++ b/src/cpu/amd/pi/00660F01/Makefile.inc @@ -8,4 +8,3 @@ subdirs-y += ../../mtrr subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/pae -subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index 25b72a7..4247189 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -5,6 +5,7 @@ select CPU_X86_CACHE select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select X86_AMD_FIXED_MTRRS select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_UNDISCLOSED diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index ea06ced..c33c642 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -10,4 +10,3 @@ subdirs-y += ../../mtrr subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/pae -subdirs-y += ../../../x86/smm diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 8e40c73..e234cab 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -12,6 +12,7 @@ select ARCH_RAMSTAGE_X86_32 select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select MMX select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 247c266..2f2c128 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -15,7 +15,6 @@ subdirs-y += ../microcode subdirs-y += ../turbo -subdirs-y += ../../x86/smm subdirs-y += ../../x86/tsc cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3c-*) diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 289aa62..9a7f6bb 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -12,6 +12,7 @@ select CPU_X86_CACHE select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 99ef0ed..08b6191 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -15,7 +15,6 @@ subdirs-y += ../smm/gen1 subdirs-y += ../turbo subdirs-y += ../../x86/name -subdirs-y += ../../x86/smm subdirs-y += ../../x86/tsc cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*) diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 500a717..cfb12d9 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,6 +12,7 @@ select CPU_X86_CACHE select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select MMX select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index 5d44eef..00802fc 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -19,7 +19,6 @@ subdirs-y += ../smm/gen1 subdirs-y += ../turbo subdirs-y += ../../x86/name -subdirs-y += ../../x86/smm subdirs-y += ../../x86/tsc cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*) diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 8d0804e..ae48885 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -14,6 +14,7 @@ select CPU_INTEL_MODEL_6XX select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select NO_SMM select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index de4dae6..c071ec8 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -8,7 +8,6 @@ subdirs-y += ../model_68x subdirs-y += ../model_6bx subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/smm subdirs-y += ../microcode bootblock-y += ../car/p3/cache_as_ram.S diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index 5852a10..c66e463 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -8,6 +8,7 @@ select CPU_INTEL_MODEL_106CX select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select MMX select SSE select SETUP_XIP_CACHE diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc index c5b3223..a502290 100644 --- a/src/cpu/intel/socket_441/Makefile.inc +++ b/src/cpu/intel/socket_441/Makefile.inc @@ -10,5 +10,4 @@ subdirs-y += ../hyperthreading subdirs-y += ../microcode subdirs-y += ../speedstep -subdirs-y += ../../x86/smm subdirs-y += ../../x86/tsc diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index 9862038..8b92d36 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -3,6 +3,7 @@ select CPU_INTEL_MODEL_1067X select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select MMX select SSE diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc index de3c201..7c7149d 100644 --- a/src/cpu/intel/socket_BGA956/Makefile.inc +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -10,5 +10,4 @@ subdirs-y += ../hyperthreading subdirs-y += ../microcode subdirs-y += ../speedstep -subdirs-y += ../../x86/smm subdirs-y += ../../x86/tsc diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index b79427e..bb1e1a6 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -10,6 +10,7 @@ select CPU_INTEL_MODEL_106CX select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select MMX select SSE select CPU_HAS_L2_ENABLE_MSR diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 47dd01d..8f360f1 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -10,5 +10,4 @@ subdirs-y += ../hyperthreading subdirs-y += ../microcode subdirs-y += ../speedstep -subdirs-y += ../../x86/smm subdirs-y += ../../x86/tsc diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 9b039fc..ca0a513 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -11,6 +11,7 @@ select CPU_INTEL_MODEL_1067X select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select MMX select SSE select SIPI_VECTOR_IN_ROM diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index cfe19d1..5f3ef15 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -14,5 +14,4 @@ subdirs-y += ../hyperthreading subdirs-y += ../microcode subdirs-y += ../speedstep -subdirs-y += ../../x86/smm subdirs-y += ../../x86/tsc diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index 1860ff1..e13e1d0 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -9,6 +9,7 @@ select CPU_INTEL_MODEL_6FX select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select MMX select SSE diff --git a/src/cpu/intel/socket_m/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc index 7f814cc..6d28bab 100644 --- a/src/cpu/intel/socket_m/Makefile.inc +++ b/src/cpu/intel/socket_m/Makefile.inc @@ -11,5 +11,4 @@ subdirs-y += ../hyperthreading subdirs-y += ../microcode subdirs-y += ../speedstep -subdirs-y += ../../x86/smm subdirs-y += ../../x86/tsc diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index bc3f5ba..02145d5 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -8,6 +8,7 @@ select CPU_INTEL_MODEL_F2X select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select MMX select SSE select UDELAY_TSC diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 6d8b838..5e17ab8 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -1,6 +1,5 @@ subdirs-y += ../model_f2x subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig index 506fbeb..6c8c3f7 100644 --- a/src/cpu/intel/socket_p/Kconfig +++ b/src/cpu/intel/socket_p/Kconfig @@ -4,6 +4,7 @@ select CPU_INTEL_MODEL_6FX select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select MMX select SSE diff --git a/src/cpu/intel/socket_p/Makefile.inc b/src/cpu/intel/socket_p/Makefile.inc index 3974e1c..5d5f520 100644 --- a/src/cpu/intel/socket_p/Makefile.inc +++ b/src/cpu/intel/socket_p/Makefile.inc @@ -11,5 +11,4 @@ subdirs-y += ../hyperthreading subdirs-y += ../microcode subdirs-y += ../speedstep -subdirs-y += ../../x86/smm subdirs-y += ../../x86/tsc diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index ad130f2..6ab327f 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -8,6 +8,7 @@ select ARCH_RAMSTAGE_X86_32 select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select SMP select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index c3d0aad..d2738cf 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -7,5 +7,4 @@ ramstage-y += qemu.c -subdirs-y += ../x86/smm subdirs-y += ../x86/tsc diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 617e093..dddd911 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -10,6 +10,10 @@ bool default n +config CPU_X86_SMM + bool + default n + # TODO These two options look too similar config PARALLEL_CPU_INIT bool diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index ac30700..9616bb4 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -2,6 +2,7 @@ subdirs-$(CONFIG_CPU_X86_CACHE) += cache subdirs-$(CONFIG_CPU_X86_LAPIC) += lapic subdirs-$(CONFIG_CPU_X86_MTRR) += mtrr +subdirs-$(CONFIG_CPU_X86_SMM) += smm subdirs-$(CONFIG_PARALLEL_MP) += name ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-y += backup_default_smm.c diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 3d3968b..e6ed611 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -15,6 +15,7 @@ select ARCH_RAMSTAGE_X86_32 select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select RESET_VECTOR_IN_RAM select X86_AMD_FIXED_MTRRS select X86_AMD_INIT_SIPI diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 3b2b497..b293eb6 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/amd/mtrr/ subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/pae -subdirs-y += ../../../cpu/x86/smm subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage bootblock-y += bootblock/pre_c.S diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index ac629fd..59d2be5 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -15,6 +15,7 @@ select ARCH_RAMSTAGE_X86_32 select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select X86_AMD_FIXED_MTRRS select ACPI_AMD_HARDWARE_SLEEP_VALUES select COLLECT_TIMESTAMPS_NO_TSC diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 2019fb0..231f0d9 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/amd/mtrr/ subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/pae -subdirs-y += ../../../cpu/x86/smm bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c bootblock-y += BiosCallOuts.c diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 2421d26..1b2337f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -31,6 +31,7 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select IOAPIC select PCR_COMMON_IOSF_1_0 select SMP diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 5e58538..1058cf2 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 3ac33cf..1f7a804 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -16,6 +16,7 @@ select CACHE_MRC_SETTINGS select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index a2e4340..fa8519e 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -1,7 +1,6 @@ ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index b02f4f3..c5ff0fa 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -16,6 +16,7 @@ select CACHE_MRC_SETTINGS select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select HAVE_SMI_HANDLER diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 701424b..df52b7f 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -1,7 +1,6 @@ ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 515026b..bd810ad 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -19,6 +19,7 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index da42f35..1a361e5 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,7 +1,6 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index a77a8a1..9c7bad9 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -69,6 +69,7 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select FSP_COMPRESS_FSP_S_LZMA select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index ec4e82b..c4ef987 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/common diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 7532ccb..18dba59 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -17,6 +17,7 @@ select BOOT_DEVICE_SUPPORTS_WRITES select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select DEBUG_GPIO select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index 3bd2106..84dc846 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index b2cf82d..b6453cd 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -18,6 +18,7 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 8ae39f7..4d744bc 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc # all (bootblock, verstage, romstage, postcar, ramstage) diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index eb34598..a3a673d 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -19,6 +19,7 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index f87d0fd..8262c32 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc # all (bootblock, verstage, romstage, postcar, ramstage) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 37ae68d..a753db8 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -31,6 +31,7 @@ select CPU_INTEL_COMMON_HYPERTHREADING select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index c858d1e..9dbfa26 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 8c73d76..c3105c8 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -19,6 +19,7 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_SMM select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 27b62a0..848a5b0 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc # all (bootblock, verstage, romstage, postcar, ramstage) diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 540212c..7ab0ed0 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -8,6 +8,7 @@ config SOC_INTEL_SKYLAKE_SP bool + select CPU_X86_SMM if HAVE_SMI_HANDLER select XEON_SP_COMMON_BASE select PLATFORM_USES_FSP2_0 help diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc index db29e1c..7d4ece7 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.inc +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../../../cpu/intel/microcode subdirs-y += ../../../../cpu/intel/turbo subdirs-y += ../../../../cpu/x86/tsc -subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm postcar-y += soc_util.c -- To view, visit https://review.coreboot.org/c/coreboot/+/44231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I478d3fd37d9f9c0daa4a704fdf5ba92b2028bf43 Gerrit-Change-Number: 44231 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: [WIP] inteltool: Also print LynxPoint IOBP for WildcatPoint-LP
by Iru Cai (vimacs) (Code Review) 25 Oct '21

25 Oct '21

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46831 to review the following change. Change subject: [WIP] inteltool: Also print LynxPoint IOBP for WildcatPoint-LP ...................................................................... [WIP] inteltool: Also print LynxPoint IOBP for WildcatPoint-LP Change-Id: I85892bfaf278a4a973e7e54c66b212b528840f60 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/inteltool/iobp.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46831/1 diff --git a/util/inteltool/iobp.c b/util/inteltool/iobp.c index 831443b..4d6e04b 100644 --- a/util/inteltool/iobp.c +++ b/util/inteltool/iobp.c @@ -177,6 +177,8 @@ case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: + case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM: + case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP: iobp_registers = lynxpoint_iobp_registers; iobp_size = ARRAY_SIZE(lynxpoint_iobp_registers); break; -- To view, visit https://review.coreboot.org/c/coreboot/+/46831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85892bfaf278a4a973e7e54c66b212b528840f60 Gerrit-Change-Number: 46831 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: inteltool: Add Intel 200 and Z370 series chipset
by Iru Cai (vimacs) (Code Review) 25 Oct '21

25 Oct '21

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35909 to review the following change. Change subject: inteltool: Add Intel 200 and Z370 series chipset ...................................................................... inteltool: Add Intel 200 and Z370 series chipset These chipsets are in the "Intel 200 (including X299) and Intel Z370 Series Chipset Families Platform Controller Hub (PCH)" datasheet (document number 335192). Change-Id: I4bad85eebab3991048907e5bd4783ad4e6ffa641 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 5 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/35909/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index efeab56..97e1419 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1070,6 +1070,13 @@ case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: + case PCI_DEVICE_ID_INTEL_Z270: + case PCI_DEVICE_ID_INTEL_H270: + case PCI_DEVICE_ID_INTEL_B250: + case PCI_DEVICE_ID_INTEL_Q250: + case PCI_DEVICE_ID_INTEL_Q270: + case PCI_DEVICE_ID_INTEL_X299: + case PCI_DEVICE_ID_INTEL_Z370: print_gpio_groups(sb); return 0; case PCI_DEVICE_ID_INTEL_82371XX: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 321cf97..d43983d 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -2239,6 +2239,13 @@ case PCI_DEVICE_ID_INTEL_QM170: case PCI_DEVICE_ID_INTEL_HM170: case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_Z270: + case PCI_DEVICE_ID_INTEL_H270: + case PCI_DEVICE_ID_INTEL_B250: + case PCI_DEVICE_ID_INTEL_Q250: + case PCI_DEVICE_ID_INTEL_Q270: + case PCI_DEVICE_ID_INTEL_X299: + case PCI_DEVICE_ID_INTEL_Z370: community_count = ARRAY_SIZE(sunrise_communities); communities = sunrise_communities; pcr_init(sb); diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index db80bd2..8fef3b4 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -275,6 +275,13 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C621_SUPER, "C621 Super SKU" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C627_SUPER_2, "C627 Super SKU" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C628_SUPER, "C628 Super SKU" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z270, "Z270" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H270, "H270" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B250, "B250" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q250, "Q250" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q270, "Q270" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X299, "X299" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z370, "Z370" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H310, "H310" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H370, "H370" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z390, "Z390" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fc6dc4b..def78c6 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -184,6 +184,14 @@ #define PCI_DEVICE_ID_INTEL_C627_SUPER_2 0xa245 #define PCI_DEVICE_ID_INTEL_C628_SUPER 0xa246 +#define PCI_DEVICE_ID_INTEL_Z270 0xa2c5 +#define PCI_DEVICE_ID_INTEL_H270 0xa2c4 +#define PCI_DEVICE_ID_INTEL_B250 0xa2c8 +#define PCI_DEVICE_ID_INTEL_Q250 0xa2c7 +#define PCI_DEVICE_ID_INTEL_Q270 0xa2c6 +#define PCI_DEVICE_ID_INTEL_X299 0xa2d2 +#define PCI_DEVICE_ID_INTEL_Z370 0xa2c9 + #define PCI_DEVICE_ID_INTEL_H310 0xa303 #define PCI_DEVICE_ID_INTEL_H370 0xa304 #define PCI_DEVICE_ID_INTEL_Z390 0xa305 diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index ef6bb39..b6dc5e8 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -117,6 +117,13 @@ case PCI_DEVICE_ID_INTEL_C627_SUPER_2: case PCI_DEVICE_ID_INTEL_C628_SUPER: case PCI_DEVICE_ID_INTEL_DNV_LPC: + case PCI_DEVICE_ID_INTEL_Z270: + case PCI_DEVICE_ID_INTEL_H270: + case PCI_DEVICE_ID_INTEL_B250: + case PCI_DEVICE_ID_INTEL_Q250: + case PCI_DEVICE_ID_INTEL_Q270: + case PCI_DEVICE_ID_INTEL_X299: + case PCI_DEVICE_ID_INTEL_Z370: p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1); break; case PCI_DEVICE_ID_INTEL_APL_LPC: -- To view, visit https://review.coreboot.org/c/coreboot/+/35909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bad85eebab3991048907e5bd4783ad4e6ffa641 Gerrit-Change-Number: 35909 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in gerrit-avatars[master]: [TESTONLY, DONOTMERGE] Change someone else's profile picture
by Angel Pons (Code Review) 23 Oct '21

23 Oct '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/gerrit-avatars/+/42290 ) Change subject: [TESTONLY, DONOTMERGE] Change someone else's profile picture ...................................................................... [TESTONLY, DONOTMERGE] Change someone else's profile picture CB:39926 added an extra southbridge to test things, so we respond by doing the same kind of thing but with a northbridge instead :-P Change-Id: I34f127e1653194b51573f6a929cb4aeab6b03a9f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A 1000145.jpg 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/gerrit-avatars refs/changes/90/42290/1 diff --git a/1000145.jpg b/1000145.jpg new file mode 100644 index 0000000..958accd --- /dev/null +++ b/1000145.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/gerrit-avatars/+/42290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: gerrit-avatars Gerrit-Branch: master Gerrit-Change-Id: I34f127e1653194b51573f6a929cb4aeab6b03a9f Gerrit-Change-Number: 42290 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 6

Change in coreboot[master]: coreboot-id: Add coreboot id based on FMAP entries
by Furquan Shaikh (Code Review) 22 Oct '21

22 Oct '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40377 ) Change subject: coreboot-id: Add coreboot id based on FMAP entries ...................................................................... coreboot-id: Add coreboot id based on FMAP entries This change replaces the coreboot id added to bootblock/decompressor stages with a ID region in FMAP that can be used across platforms. Following changes are made as part of this: 1. Adds new Kconfig options for COREBOOT_ID_FMAP_NAME and COREBOOT_ID_SIZE which provide the details of the fmap region name used for storing coreboot ID and the size of this region. Chrome OS does not use any of the coreboot build details filled in ID region. So, they are skipped for all Chrome OS boards. 2. Adds ##COREBOOT_ID_ENTRY## to default fmd files that can be used as a marker to insert the fmap entries for coreboot ID. 3. Replaces ##COREBOOT_ID_ENTRY## marker in the default fmd files using Makefile and the newly added FMAP_CURRENT_BASE. 4. Adds coreboot build details (version, vendor, part number) to this newly added FMAP region using cbfstool add-id command. 5. Removes id.ld and id.S from all architectures using it. 6. Adds COREBOOT_ID region to all non-Chrome OS fmd files. Because of this change, following difference would be observed: 1. Non-Chrome OS boards: coreboot build details will move from near the reset vector in bootblock/decompressor to a separate FMAP region. coreboot does not rely on these details at runtime. So, there should not be any impact. I am unsure if any tools used this at runtime. If yes, then those tools will have to be updated to use FMAP instead to find the location of ID. 2. Chrome OS boards: No coreboot details added to ROM image. TEST=Verified that build details are correctly added to the ID region in FMAP. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: Ibe1aaf36bec00b4cffc46a3640a5a0d1e4bb8067 --- M Documentation/Intel/SoC/soc.html M Makefile.inc M src/Kconfig M src/arch/arm/Makefile.inc D src/arch/arm/id.S M src/arch/arm64/Makefile.inc D src/arch/arm64/id.S M src/arch/x86/Makefile.inc D src/arch/x86/id.S D src/arch/x86/id.ld M src/arch/x86/memlayout.ld M src/mainboard/51nb/x210/board.fmd M src/mainboard/cavium/cn8100_sff_evb/board.fmd M src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd M src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd M src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd M src/mainboard/facebook/monolith/vboot-ro.fmd M src/mainboard/facebook/monolith/vboot-rw.fmd M src/mainboard/intel/cedarisland_crb/board.fmd M src/mainboard/intel/galileo/vboot.fmd M src/mainboard/intel/leafhill/leafhill.16384.fmd M src/mainboard/intel/leafhill/leafhill.8192.fmd M src/mainboard/intel/minnow3/minnow3.fmd M src/mainboard/lenovo/t400/vboot-rwa.fmd M src/mainboard/lenovo/t410/vboot-rwa.fmd M src/mainboard/lenovo/t420/vboot-rwa.fmd M src/mainboard/lenovo/t420s/vboot-rwa.fmd M src/mainboard/lenovo/t430/vboot-rwab.fmd M src/mainboard/lenovo/t430s/vboot-rwab.fmd M src/mainboard/lenovo/t440p/vboot-rwab.fmd M src/mainboard/lenovo/t520/vboot-rwa.fmd M src/mainboard/lenovo/t530/vboot-rwab.fmd M src/mainboard/lenovo/x131e/vboot-rwab.fmd M src/mainboard/lenovo/x1_carbon_gen1/vboot-rwab.fmd M src/mainboard/lenovo/x200/vboot-rwa.fmd M src/mainboard/lenovo/x201/vboot-rwa.fmd M src/mainboard/lenovo/x220/vboot-rwa.fmd M src/mainboard/lenovo/x230/vboot-rwab.fmd M src/mainboard/ocp/tiogapass/board.fmd M src/mainboard/opencellular/elgon/board.fmd M src/mainboard/opencellular/elgon/vboot.fmd M src/mainboard/siemens/mc_apl1/mc_apl1.fmd M src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd M src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd M src/mainboard/up/squared/upsquared.fmd M src/mainboard/up/squared/vboot-ro.fmd M src/mainboard/up/squared/vboot-roa.fmd M src/mainboard/up/squared/vboot-roab.fmd M util/cbfstool/default-x86.fmd M util/cbfstool/default.fmd 50 files changed, 113 insertions(+), 133 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/40377/1 diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 6b1bb30..9e4d62e 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -199,9 +199,6 @@ </li> </ul> </li> - <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/id.S">src/arch/x86/id.S</a> - added by <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Mak…">src/arch/x86/Makefile.inc</a> - </li> <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fi…">src/cpu/intel/fit/fit.S</a> added by <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fi…">src/cpu/intel/fit/Makefile.inc</a> </li> diff --git a/Makefile.inc b/Makefile.inc index ac430f7..19f018c 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -926,6 +926,15 @@ FMAP_SMMSTORE_ENTRY := endif +ifneq ($(CONFIG_COREBOOT_ID_SIZE),0) +FMAP_COREBOOT_ID_BASE := $(FMAP_CURRENT_BASE) +FMAP_COREBOOT_ID_SIZE := $(CONFIG_COREBOOT_ID_SIZE) +FMAP_COREBOOT_ID_ENTRY := COREBOOT_ID@$(FMAP_COREBOOT_ID_BASE) $(FMAP_COREBOOT_ID_SIZE) +FMAP_CURRENT_BASE := $(call int-add, $(FMAP_COREBOOT_ID_BASE) $(FMAP_COREBOOT_ID_SIZE)) +else +FMAP_COREBOOT_ID_ENTRY := +endif + # # X86 FMAP region # @@ -983,6 +992,15 @@ FMAP_MRC_CACHE_ENTRY := endif +ifneq ($(CONFIG_COREBOOT_ID_SIZE),0) +FMAP_COREBOOT_ID_BASE := $(FMAP_CURRENT_BASE) +FMAP_COREBOOT_ID_SIZE := $(CONFIG_COREBOOT_ID_SIZE) +FMAP_COREBOOT_ID_ENTRY := COREBOOT_ID@$(FMAP_COREBOOT_ID_BASE) $(FMAP_COREBOOT_ID_SIZE) +FMAP_CURRENT_BASE := $(call int-add, $(FMAP_COREBOOT_ID_BASE) $(FMAP_COREBOOT_ID_SIZE)) +else +FMAP_COREBOOT_ID_ENTRY := +endif + # # NON-X86 COREBOOT default cbfs FMAP region # @@ -1002,6 +1020,7 @@ -e "s,##CONSOLE_ENTRY##,$(FMAP_CONSOLE_ENTRY)," \ -e "s,##MRC_CACHE_ENTRY##,$(FMAP_MRC_CACHE_ENTRY)," \ -e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \ + -e "s,##COREBOOT_ID_ENTRY##,$(FMAP_COREBOOT_ID_ENTRY)," \ -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \ -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \ $(DEFAULT_FLASHMAP) > $@.tmp @@ -1028,6 +1047,11 @@ ifneq ($(CONFIG_UPDATE_IMAGE),y) $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(IFITTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap $(obj)/fmap.desc $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc) +ifneq ($(CONFIG_COREBOOT_ID_FMAP_NAME),"") + $(CBFSTOOL) $@.tmp add-id -r $(CONFIG_COREBOOT_ID_FMAP_NAME) --id-version $(KERNELVERSION) \ + --id-vendor $(CONFIG_MAINBOARD_VENDOR) \ + --id-part-num $(CONFIG_MAINBOARD_PART_NUMBER) +endif ifeq ($(CONFIG_ARCH_X86),y) $(CBFSTOOL) $@.tmp add \ -f $(objcbfs)/bootblock.bin \ diff --git a/src/Kconfig b/src/Kconfig index da21af1..378f302 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -422,6 +422,22 @@ binaries. This symbol should only be used to generate a default FMAP and is unused when a non-default fmd file is provided via CONFIG_FMDFILE. +config COREBOOT_ID_FMAP_NAME + string "Name of FMAP region storing coreboot build details" + default "" if CHROMEOS + default "COREBOOT_ID" + help + This is the name of the FMAP region where coreboot build details like + version, vendor name and part number are stored by the build system. + +config COREBOOT_ID_SIZE + hex "Size of FMAP region storing coreboot build details" + default 0 if CHROMEOS + default 0x40 + help + This is the size of the FMAP region where coreboot build details like + version, vendor name and part number are stored by the build system. + endmenu # load site-local kconfig to allow user specific defaults and overrides diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index a8abfaf..998ef8e 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -31,11 +31,6 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM),y) -decompressor-y += id.S -bootblock-y += id.S -$(call src-to-obj,decompressor,$(dir)/id.S): $(obj)/build.h -$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h - decompressor-y += boot.c bootblock-y += boot.c decompressor-y += div0.c diff --git a/src/arch/arm/id.S b/src/arch/arm/id.S deleted file mode 100644 index 3cdd013..0000000 --- a/src/arch/arm/id.S +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <build.h> - - .section ".id", "a", %progbits - - .globl __id_start -__id_start: -ver: - .asciz COREBOOT_VERSION -vendor: - .asciz CONFIG_MAINBOARD_VENDOR -part: - .asciz CONFIG_MAINBOARD_PART_NUMBER -.long __id_end - ver /* Reverse offset to the vendor id */ -.long __id_end - vendor /* Reverse offset to the vendor id */ -.long __id_end - part /* Reverse offset to the part number */ -.long CONFIG_ROM_SIZE /* Size of this romimage */ - .globl __id_end - -__id_end: -.previous diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index c3d1fe5..3e4b28d 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -31,10 +31,6 @@ bootblock-y += div0.c decompressor-y += eabi_compat.c bootblock-y += eabi_compat.c -decompressor-y += id.S -bootblock-y += id.S -$(call src-to-obj,decompressor,$(dir)/id.S): $(obj)/build.h -$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h bootblock-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c bootblock-y += transition.c transition_asm.S diff --git a/src/arch/arm64/id.S b/src/arch/arm64/id.S deleted file mode 100644 index 3cdd013..0000000 --- a/src/arch/arm64/id.S +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <build.h> - - .section ".id", "a", %progbits - - .globl __id_start -__id_start: -ver: - .asciz COREBOOT_VERSION -vendor: - .asciz CONFIG_MAINBOARD_VENDOR -part: - .asciz CONFIG_MAINBOARD_PART_NUMBER -.long __id_end - ver /* Reverse offset to the vendor id */ -.long __id_end - vendor /* Reverse offset to the vendor id */ -.long __id_end - part /* Reverse offset to the part number */ -.long CONFIG_ROM_SIZE /* Size of this romimage */ - .globl __id_end - -__id_end: -.previous diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index b28ef78..d22e203 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -111,8 +111,6 @@ bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c bootblock-$(CONFIG_BOOTBLOCK_NORMAL) += bootblock_normal.c -bootblock-y += id.S -$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h bootblock-y += bootblock_crt0.S diff --git a/src/arch/x86/id.S b/src/arch/x86/id.S deleted file mode 100644 index dd447e6..0000000 --- a/src/arch/x86/id.S +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <build.h> - - .section ".id", "a", @progbits - - .globl __id_start -__id_start: -ver: - .asciz COREBOOT_VERSION -vendor: - .asciz CONFIG_MAINBOARD_VENDOR -part: - .asciz CONFIG_MAINBOARD_PART_NUMBER -.long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the - *vendor id - */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the - * vendor id - */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the - * part number - */ -.long CONFIG_ROM_SIZE /* Size of this romimage */ - .globl __id_end - -__id_end: -.previous diff --git a/src/arch/x86/id.ld b/src/arch/x86/id.ld deleted file mode 100644 index 31d5738..0000000 --- a/src/arch/x86/id.ld +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -SECTIONS { - . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; - .id (.): { - KEEP(*(.id)) - } -} diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 05efac6..ed1dbb2 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -53,7 +53,6 @@ /* Bootblock specific scripts which provide more SECTION directives. */ #include <cpu/x86/16bit/entry16.ld> #include <cpu/x86/16bit/reset16.ld> -#include <arch/x86/id.ld> #if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) #include <cpu/intel/fit/fit.ld> #endif diff --git a/src/mainboard/51nb/x210/board.fmd b/src/mainboard/51nb/x210/board.fmd index 1955a05..4e506fa 100644 --- a/src/mainboard/51nb/x210/board.fmd +++ b/src/mainboard/51nb/x210/board.fmd @@ -8,7 +8,8 @@ EC@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 SMMSTORE@0x20000 0x40000 - CONSOLE@0x60000 0x20000 + CONSOLE@0x60000 0x1ffc0 + COREBOOT_ID@0x7ffc0 0x40 FMAP@0x80000 0x200 COREBOOT(CBFS) } diff --git a/src/mainboard/cavium/cn8100_sff_evb/board.fmd b/src/mainboard/cavium/cn8100_sff_evb/board.fmd index 34f3161..7ac0d9f 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/board.fmd +++ b/src/mainboard/cavium/cn8100_sff_evb/board.fmd @@ -4,6 +4,7 @@ # 0 - 0x10000 is free for firmware usage. # bootblock starts at 0x20000 FMAP@0x0 0x1000 + COREBOOT_ID@0x1000 0x40 # bootblock includes trusted/non-trusted CLIB, CSIB, # and BL1FWs packaged in # src/soc/cavium/common/Makefile.inc. diff --git a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd index 0d2c9da..dd06a23 100644 --- a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd +++ b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd @@ -10,7 +10,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd index 0d2c9da..dd06a23 100644 --- a/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd +++ b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd @@ -10,7 +10,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd index fcbfa95..94899f0 100644 --- a/src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd +++ b/src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd @@ -19,7 +19,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/facebook/monolith/vboot-ro.fmd b/src/mainboard/facebook/monolith/vboot-ro.fmd index 569971a..3efe768 100644 --- a/src/mainboard/facebook/monolith/vboot-ro.fmd +++ b/src/mainboard/facebook/monolith/vboot-ro.fmd @@ -17,7 +17,8 @@ RO_SECTION@0x1000 0x8DF000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + COREBOOT_ID@0x840 0x40 + RO_FRID_PAD@0x880 0x780 GBB@0x1000 0x4000 COREBOOT(CBFS)@0x5000 0x8DA000 } diff --git a/src/mainboard/facebook/monolith/vboot-rw.fmd b/src/mainboard/facebook/monolith/vboot-rw.fmd index dc2dadf..d8636ca 100644 --- a/src/mainboard/facebook/monolith/vboot-rw.fmd +++ b/src/mainboard/facebook/monolith/vboot-rw.fmd @@ -22,7 +22,8 @@ RO_SECTION@0x1000 0x7F000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + COREBOOT_ID@0x840 0x40 + RO_FRID_PAD@0x880 0x780 GBB@0x1000 0x4000 COREBOOT(CBFS)@0x5000 0x07A000 } diff --git a/src/mainboard/intel/cedarisland_crb/board.fmd b/src/mainboard/intel/cedarisland_crb/board.fmd index 2002f6e..e63fda3 100644 --- a/src/mainboard/intel/cedarisland_crb/board.fmd +++ b/src/mainboard/intel/cedarisland_crb/board.fmd @@ -5,7 +5,8 @@ SI_ME@0x3000 0x2fd5000 SI_PT@0x2fd8000 0x10000 } - FMAP@0x03000000 0x800 + FMAP@0x03000000 0x700 + COREBOOT_ID@0x3000700 0x100 RW_MRC_CACHE@0x3000800 0x10000 COREBOOT(CBFS)@0x3010800 } diff --git a/src/mainboard/intel/galileo/vboot.fmd b/src/mainboard/intel/galileo/vboot.fmd index 4d349bd..e7f3d1c 100644 --- a/src/mainboard/intel/galileo/vboot.fmd +++ b/src/mainboard/intel/galileo/vboot.fmd @@ -44,7 +44,8 @@ RO_SECTION@0x10000 0x1f0000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + COREBOOT_ID@0x840 0x40 + RO_FRID_PAD@0x880 0x780 GBB@0x1000 0x7f000 COREBOOT(CBFS)@0x80000 0x170000 } diff --git a/src/mainboard/intel/leafhill/leafhill.16384.fmd b/src/mainboard/intel/leafhill/leafhill.16384.fmd index a91ba9a..3ae4d81 100644 --- a/src/mainboard/intel/leafhill/leafhill.16384.fmd +++ b/src/mainboard/intel/leafhill/leafhill.16384.fmd @@ -1,7 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x2ff000 - FMAP@0x300000 0x800 + FMAP@0x300000 0x700 + COREBOOT_ID@0x300700 0x100 COREBOOT(CBFS)@0x300800 0xc1d800 UNIFIED_MRC_CACHE@0xf1e000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 diff --git a/src/mainboard/intel/leafhill/leafhill.8192.fmd b/src/mainboard/intel/leafhill/leafhill.8192.fmd index 3f4d21b..f754d82 100644 --- a/src/mainboard/intel/leafhill/leafhill.8192.fmd +++ b/src/mainboard/intel/leafhill/leafhill.8192.fmd @@ -1,7 +1,8 @@ FLASH 8M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x300000 - FMAP@0x321000 0x800 + FMAP@0x321000 0x700 + COREBOOT_ID@0x321700 0x100 COREBOOT(CBFS)@0x321800 0x300000 UNIFIED_MRC_CACHE@0x621800 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 diff --git a/src/mainboard/intel/minnow3/minnow3.fmd b/src/mainboard/intel/minnow3/minnow3.fmd index d51b5ee..b3ee60a 100644 --- a/src/mainboard/intel/minnow3/minnow3.fmd +++ b/src/mainboard/intel/minnow3/minnow3.fmd @@ -1,7 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x300000 - FMAP@0x301000 0x800 + FMAP@0x301000 0x700 + COREBOOT_ID@0x301700 0x100 COREBOOT(CBFS)@0x301800 0x3dc800 UNIFIED_MRC_CACHE@0x6de000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 diff --git a/src/mainboard/lenovo/t400/vboot-rwa.fmd b/src/mainboard/lenovo/t400/vboot-rwa.fmd index 4af3fcd..7fff352 100644 --- a/src/mainboard/lenovo/t400/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t400/vboot-rwa.fmd @@ -17,7 +17,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/t410/vboot-rwa.fmd b/src/mainboard/lenovo/t410/vboot-rwa.fmd index 8f50d33..6aa8bf4 100644 --- a/src/mainboard/lenovo/t410/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t410/vboot-rwa.fmd @@ -22,7 +22,8 @@ RO_SECTION 0x11e000 { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 GBB 0x1e000 COREBOOT(CBFS) } diff --git a/src/mainboard/lenovo/t420/vboot-rwa.fmd b/src/mainboard/lenovo/t420/vboot-rwa.fmd index 8a4cd3b..ac157c6 100644 --- a/src/mainboard/lenovo/t420/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t420/vboot-rwa.fmd @@ -20,7 +20,8 @@ WP_RO@0x1e1000 0x11f000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + COREBOOT_ID@0x840 0x40 + RO_PADDING@0x880 0x780 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/t420s/vboot-rwa.fmd b/src/mainboard/lenovo/t420s/vboot-rwa.fmd index 8a4cd3b..ac157c6 100644 --- a/src/mainboard/lenovo/t420s/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t420s/vboot-rwa.fmd @@ -20,7 +20,8 @@ WP_RO@0x1e1000 0x11f000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + COREBOOT_ID@0x840 0x40 + RO_PADDING@0x880 0x780 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/t430/vboot-rwab.fmd b/src/mainboard/lenovo/t430/vboot-rwab.fmd index 1747c0e..df60275 100644 --- a/src/mainboard/lenovo/t430/vboot-rwab.fmd +++ b/src/mainboard/lenovo/t430/vboot-rwab.fmd @@ -25,7 +25,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/t430s/vboot-rwab.fmd b/src/mainboard/lenovo/t430s/vboot-rwab.fmd index 1747c0e..df60275 100644 --- a/src/mainboard/lenovo/t430s/vboot-rwab.fmd +++ b/src/mainboard/lenovo/t430s/vboot-rwab.fmd @@ -25,7 +25,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/t440p/vboot-rwab.fmd b/src/mainboard/lenovo/t440p/vboot-rwab.fmd index 1747c0e..df60275 100644 --- a/src/mainboard/lenovo/t440p/vboot-rwab.fmd +++ b/src/mainboard/lenovo/t440p/vboot-rwab.fmd @@ -25,7 +25,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/t520/vboot-rwa.fmd b/src/mainboard/lenovo/t520/vboot-rwa.fmd index 8a4cd3b..ac157c6 100644 --- a/src/mainboard/lenovo/t520/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t520/vboot-rwa.fmd @@ -20,7 +20,8 @@ WP_RO@0x1e1000 0x11f000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + COREBOOT_ID@0x840 0x40 + RO_PADDING@0x880 0x780 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/t530/vboot-rwab.fmd b/src/mainboard/lenovo/t530/vboot-rwab.fmd index 1747c0e..df60275 100644 --- a/src/mainboard/lenovo/t530/vboot-rwab.fmd +++ b/src/mainboard/lenovo/t530/vboot-rwab.fmd @@ -25,7 +25,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/x131e/vboot-rwab.fmd b/src/mainboard/lenovo/x131e/vboot-rwab.fmd index 1747c0e..df60275 100644 --- a/src/mainboard/lenovo/x131e/vboot-rwab.fmd +++ b/src/mainboard/lenovo/x131e/vboot-rwab.fmd @@ -25,7 +25,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwab.fmd b/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwab.fmd index 1747c0e..df60275 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwab.fmd +++ b/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwab.fmd @@ -25,7 +25,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/x200/vboot-rwa.fmd b/src/mainboard/lenovo/x200/vboot-rwa.fmd index 4af3fcd..7fff352 100644 --- a/src/mainboard/lenovo/x200/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x200/vboot-rwa.fmd @@ -17,7 +17,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/x201/vboot-rwa.fmd b/src/mainboard/lenovo/x201/vboot-rwa.fmd index 0d1aa5d..78aaeb1 100644 --- a/src/mainboard/lenovo/x201/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x201/vboot-rwa.fmd @@ -21,7 +21,8 @@ RO_SECTION { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 GBB 0x1e000 COREBOOT(CBFS) } diff --git a/src/mainboard/lenovo/x220/vboot-rwa.fmd b/src/mainboard/lenovo/x220/vboot-rwa.fmd index 8a4cd3b..ac157c6 100644 --- a/src/mainboard/lenovo/x220/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x220/vboot-rwa.fmd @@ -20,7 +20,8 @@ WP_RO@0x1e1000 0x11f000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + COREBOOT_ID@0x840 0x40 + RO_PADDING@0x880 0x780 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/x230/vboot-rwab.fmd b/src/mainboard/lenovo/x230/vboot-rwab.fmd index 1747c0e..df60275 100644 --- a/src/mainboard/lenovo/x230/vboot-rwab.fmd +++ b/src/mainboard/lenovo/x230/vboot-rwab.fmd @@ -25,7 +25,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/ocp/tiogapass/board.fmd b/src/mainboard/ocp/tiogapass/board.fmd index 1e3fda7..53f848b 100644 --- a/src/mainboard/ocp/tiogapass/board.fmd +++ b/src/mainboard/ocp/tiogapass/board.fmd @@ -5,7 +5,8 @@ PLATFORM_DATA@0xa26000 0x10000 } SI_BIOS@0x1000000 0x1000000 { - FMAP@0x0 0x800 + FMAP@0x0 0x700 + COREBOOT_ID@0x700 0x100 COREBOOT(CBFS)@0x800 0xfff800 } } diff --git a/src/mainboard/opencellular/elgon/board.fmd b/src/mainboard/opencellular/elgon/board.fmd index 784f3b0..e5ea8cb 100644 --- a/src/mainboard/opencellular/elgon/board.fmd +++ b/src/mainboard/opencellular/elgon/board.fmd @@ -4,6 +4,7 @@ # 0 - 0x10000 is free for firmware usage. # bootblock starts at 0x20000 FMAP@0x0 0x1000 + COREBOOT_ID@0x1000 0x40 # bootblock includes trusted/non-trusted CLIB, CSIB, # and BL1FWs packaged in # src/soc/cavium/common/Makefile.inc. diff --git a/src/mainboard/opencellular/elgon/vboot.fmd b/src/mainboard/opencellular/elgon/vboot.fmd index 0d6af2d..909e8de 100644 --- a/src/mainboard/opencellular/elgon/vboot.fmd +++ b/src/mainboard/opencellular/elgon/vboot.fmd @@ -6,6 +6,7 @@ # bootblock starts at 0x20000 FMAP@0x0 0x1000 RO_FRID@0x1000 0x100 + COREBOOT_ID@0x1100 0x40 # bootblock includes trusted/non-trusted CLIB, CSIB, # and BL1FWs packaged in # src/soc/cavium/common/Makefile.inc. diff --git a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd index 36772d6..fdeb65c 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd @@ -1,7 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI 0x2ff000 - FMAP 0x800 + FMAP 0x700 + COREBOOT_ID 0x100 COREBOOT(CBFS) 0xb9d800 UNIFIED_MRC_CACHE 0x21000 { RECOVERY_MRC_CACHE 0x10000 diff --git a/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd b/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd index 8af2e9a..d165d71 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd @@ -6,7 +6,8 @@ RO_SECTION 0xb8f000 { FMAP 0x800 RO_FRID 0x40 - RO_FRID_PAD 0x7c0 + COREBOOT_ID 0x40 + RO_FRID_PAD 0x780 COREBOOT(CBFS) 0xb4e000 GBB 0x40000 } diff --git a/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd index a295680..aa38f37 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd +++ b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd @@ -27,7 +27,8 @@ RO_SECTION@0x4000 0x41d000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + COREBOOT_ID@0x840 0x40 + RO_FRID_PAD@0x880 0x780 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x32d000 } diff --git a/src/mainboard/up/squared/upsquared.fmd b/src/mainboard/up/squared/upsquared.fmd index 891138e..86c7cea 100644 --- a/src/mainboard/up/squared/upsquared.fmd +++ b/src/mainboard/up/squared/upsquared.fmd @@ -9,7 +9,8 @@ RW_MRC_CACHE@0x10000 0x10000 RW_VAR_MRC_CACHE@0x20000 0x1000 } - CONSOLE@0x22000 0x20000 + CONSOLE@0x22000 0x1ffc0 + COREBOOT_ID@0x41fc0 0x40 COREBOOT(CBFS)@0x42000 0xb7d000 BIOS_UNUSABLE@0xbbf000 0x40000 } diff --git a/src/mainboard/up/squared/vboot-ro.fmd b/src/mainboard/up/squared/vboot-ro.fmd index 72f92fe..8c71f53 100644 --- a/src/mainboard/up/squared/vboot-ro.fmd +++ b/src/mainboard/up/squared/vboot-ro.fmd @@ -7,7 +7,8 @@ RO_VPD(PRESERVE)@0x2ff800 0x4000 RO_SECTION@0x303800 0xb8d800 { RO_FRID@0x0 0x40 - RO_FRID_PAD@0x40 0x7c0 + COREBOOT_ID@0x40 0x40 + RO_FRID_PAD@0x80 0x780 GBB@0x800 0x40000 COREBOOT(CBFS)@0x40800 0xb4d000 } diff --git a/src/mainboard/up/squared/vboot-roa.fmd b/src/mainboard/up/squared/vboot-roa.fmd index 330ce03..118cde9 100644 --- a/src/mainboard/up/squared/vboot-roa.fmd +++ b/src/mainboard/up/squared/vboot-roa.fmd @@ -7,7 +7,8 @@ RO_VPD(PRESERVE)@0x2ff800 0x4000 RO_SECTION@0x303800 0x1fe800 { RO_FRID@0x0 0x40 - RO_FRID_PAD@0x40 0x7c0 + COREBOOT_ID@0x40 0x40 + RO_FRID_PAD@0x80 0x780 GBB@0x800 0x40000 COREBOOT(CBFS)@0x40800 0x1be000 } diff --git a/src/mainboard/up/squared/vboot-roab.fmd b/src/mainboard/up/squared/vboot-roab.fmd index 4ddcbc0..512355d 100644 --- a/src/mainboard/up/squared/vboot-roab.fmd +++ b/src/mainboard/up/squared/vboot-roab.fmd @@ -7,7 +7,8 @@ RO_VPD(PRESERVE)@0x2ff800 0x4000 RO_SECTION@0x303800 0x1ff800 { RO_FRID@0x0 0x40 - RO_FRID_PAD@0x40 0x7c0 + COREBOOT_ID@0x40 0x40 + RO_FRID_PAD@0x80 0x780 GBB@0x800 0x40000 COREBOOT(CBFS)@0x40800 0x1bf000 } diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd index f0143e9..ac958b4 100644 --- a/util/cbfstool/default-x86.fmd +++ b/util/cbfstool/default-x86.fmd @@ -12,6 +12,7 @@ ##CONSOLE_ENTRY## ##MRC_CACHE_ENTRY## ##SMMSTORE_ENTRY## + ##COREBOOT_ID_ENTRY## FMAP@##FMAP_BASE## ##FMAP_SIZE## COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## } diff --git a/util/cbfstool/default.fmd b/util/cbfstool/default.fmd index 8f4819e..7c8fc2c 100644 --- a/util/cbfstool/default.fmd +++ b/util/cbfstool/default.fmd @@ -15,6 +15,7 @@ FMAP@##FMAP_BASE## ##FMAP_SIZE## ##CONSOLE_ENTRY## ##MRC_CACHE_ENTRY## + ##COREBOOT_ID_ENTRY## COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## } } -- To view, visit https://review.coreboot.org/c/coreboot/+/40377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe1aaf36bec00b4cffc46a3640a5a0d1e4bb8067 Gerrit-Change-Number: 40377 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

7 21

Change in coreboot[master]: util/cbfstool: Add support for filling ID region using FMAP
by Furquan Shaikh (Code Review) 22 Oct '21

22 Oct '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40376 ) Change subject: util/cbfstool: Add support for filling ID region using FMAP ...................................................................... util/cbfstool: Add support for filling ID region using FMAP This change adds a new command add-id which takes as input the following parameters: 1. ID_FMAP_REGION: Name of the FMAP region used for storing ID (coreboot build details) 2. VERSION: Coreboot version provided by the build system. 3. VENDOR: Vendor name provided by the build system. 4. PART_NUM: Part number provided by the build system. Using the above parameters, this new command finds the fmap region using ID_FMAP_REGION and copies version, vendor and part number strings into the ID region. This allows us to get rid of all the id.ld and id.S files that are currently added in coreboot to supply build details into the bootblock or decompressor binary. This command makes use of non-ASCII longopts since we are running out of good opt characters to use. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: Ic5c55a49025508ff1f27c6f48d8e420f19d88ec2 --- M util/cbfstool/cbfstool.c 1 file changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/40376/1 diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index f15c65b..224672c 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -93,6 +93,9 @@ char *initrd; char *cmdline; int force; + const char *id_version; + const char *id_vendor; + const char *id_part_num; } param = { /* All variables not listed are initialized as zero. */ .arch = CBFS_ARCHITECTURE_UNKNOWN, @@ -1270,6 +1273,44 @@ return result; } +static int id_str_write(struct buffer *buff, const char *str) +{ + size_t len = strlen(str) + 1; + if (buffer_size(buff) < len) { + ERROR("Not enough space for string in %s\n", param.region_name); + return 1; + } + + strcpy(buffer_get(buff), str); + buffer_seek(buff, len); + return 0; +} + +static int cbfs_add_id(void) +{ + if (!param.id_version || !param.id_vendor || !param.id_part_num) { + ERROR("All ID params (version, vendor and part_num) are mandatory\n"); + return 1; + } + + printf("FUR: %s %s %s\n", param.id_version, param.id_vendor, param.id_part_num); + + struct buffer id_buffer; + + buffer_clone(&id_buffer, param.image_region); + + if (id_str_write(&id_buffer, param.id_version)) + return 1; + + if (id_str_write(&id_buffer, param.id_vendor)) + return 1; + + if (id_str_write(&id_buffer, param.id_part_num)) + return 1; + + return 0; +} + static const struct command commands[] = { {"add", "H:r:f:n:t:c:b:a:p:yvA:j:gh?", cbfs_add, true, true}, {"add-flat-binary", "H:r:f:n:l:e:c:b:p:vA:gh?", cbfs_add_flat_binary, @@ -1280,6 +1321,7 @@ true, true}, {"add-int", "H:r:i:n:b:vgh?", cbfs_add_integer, true, true}, {"add-master-header", "H:r:vh?j:", cbfs_add_master_header, true, true}, + {"add-id", "r:h?", cbfs_add_id, true, true}, {"compact", "r:h?", cbfs_compact, true, true}, {"copy", "r:R:h?", cbfs_copy, true, true}, {"create", "M:r:s:B:b:H:o:m:vh?", cbfs_create, true, true}, @@ -1297,6 +1339,9 @@ /* begin after ASCII characters */ LONGOPT_START = 256, LONGOPT_IBB = LONGOPT_START, + LONGOPT_ID_VERSION, + LONGOPT_ID_VENDOR, + LONGOPT_ID_PART_NUM, LONGOPT_END, }; @@ -1339,6 +1384,9 @@ {"mach-parseable",no_argument, 0, 'k' }, {"unprocessed", no_argument, 0, 'U' }, {"ibb", no_argument, 0, LONGOPT_IBB }, + {"id-version", required_argument, 0, LONGOPT_ID_VERSION }, + {"id-vendor", required_argument, 0, LONGOPT_ID_VENDOR }, + {"id-part-num", required_argument, 0, LONGOPT_ID_PART_NUM }, {NULL, 0, 0, 0 } }; @@ -1433,6 +1481,9 @@ " add-master-header [-r image,regions] \\ \n" " [-j topswap-size] (Intel CPUs only) " "Add a legacy CBFS master header\n" + " add-id -r ID_FMAP_REGION --id-version VERSION \\\n" + " --id-vendor VENDOR --id-part-num PART_NUM " + "Add build details to ID FMAP region\n" " remove [-r image,regions] -n NAME " "Remove a component\n" " compact -r image,regions " @@ -1752,6 +1803,15 @@ case LONGOPT_IBB: param.ibb = true; break; + case LONGOPT_ID_VERSION: + param.id_version = optarg; + break; + case LONGOPT_ID_VENDOR: + param.id_vendor = optarg; + break; + case LONGOPT_ID_PART_NUM: + param.id_part_num = optarg; + break; case 'h': case '?': usage(argv[0]); -- To view, visit https://review.coreboot.org/c/coreboot/+/40376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5c55a49025508ff1f27c6f48d8e420f19d88ec2 Gerrit-Change-Number: 40376 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

3 8

Change in gerrit-avatars[master]: My avatar.
by Bao Zheng (Code Review) 22 Oct '21

22 Oct '21

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/gerrit-avatars/+/42273 to review the following change. Change subject: My avatar. ...................................................................... My avatar. Change-Id: If3b7be405d6f8e49177ece19ef8641b8dffd8604 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> --- M 1000034.jpg 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/gerrit-avatars refs/changes/73/42273/1 diff --git a/1000034.jpg b/1000034.jpg index 1c7d0dd..a9662ce 100644 --- a/1000034.jpg +++ b/1000034.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/gerrit-avatars/+/42273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: gerrit-avatars Gerrit-Branch: master Gerrit-Change-Id: If3b7be405d6f8e49177ece19ef8641b8dffd8604 Gerrit-Change-Number: 42273 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao <zheng.bao(a)amd.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: soc/amd/picasso: Add speed measurement for spi
by Eric Peers (Code Review) 21 Oct '21

21 Oct '21

Eric Peers has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44229 ) Change subject: soc/amd/picasso: Add speed measurement for spi ...................................................................... soc/amd/picasso: Add speed measurement for spi * Still a WIP and likely not merge-worthy * Adds speed measurement for spi prior and after espi enablmenet including DMA. BUG=b:149014878 TEST=Compile & Run on Trembyle Signed-off-by: Eric PEers <epeers(a)google.com> Change-Id: I6a27c2153e6f258ef2f6a2f6c7de4f6965d535f5 --- M src/soc/amd/picasso/southbridge.c 1 file changed, 122 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/44229/1 diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 54d7640..86cf9e1 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -28,6 +28,7 @@ #include <soc/pci_devs.h> #include <soc/nvs.h> #include <types.h> +#include <timestamp.h> #include "chip.h" /* @@ -132,6 +133,118 @@ lpc_enable_port80(); } +#if !defined(__SIMPLE_DEVICE__) +#define _LPCB_DEV pcidev_on_root(0x14, 0x3) +#else +#define _LPCB_DEV PCI_DEV(0, 0x14, 0x3) +#endif + +static void measure_spi(void) +{ + //set timer + uint8_t byte; + uint32_t dword; + uint64_t qword; + uint64_t total; + uint32_t *ptr; + uint64_t *qword_ptr; + uint8_t *byte_ptr; + uint32_t start, finish, diff; + int i; + + printk(BIOS_DEBUG, "Measuring SPI\n"); + if (0) { + printk(BIOS_DEBUG, "8b writes\n"); + //-------------- 8b writes + start = get_us_since_boot(); + byte = 0; + //we get 0x14000 worth of space. + for (byte_ptr=(uint8_t *)0xff76c000;byte_ptr<(uint8_t *)0xff76d000;byte_ptr++) { + *byte_ptr = byte; + byte++; + } + finish = get_us_since_boot(); + diff = finish-start; + printk(BIOS_DEBUG, "0x1000 bytes, in %d usec\n", diff); + } + + //--------------- 8b reads + printk(BIOS_DEBUG, "8b reads\n"); + start = get_us_since_boot(); + total = 0; + for (byte_ptr = (uint8_t *)0xff76c000; byte_ptr < (uint8_t *)0xff76d000; byte_ptr++) { + byte = *byte_ptr; + total+=byte; + } + finish = get_us_since_boot(); + diff = finish-start; + printk(BIOS_DEBUG, "0x1000 bytes, in %d usec\n", diff); + printk(BIOS_DEBUG, "TOTAL: %lld\n", total); + + + if (0) { + printk(BIOS_DEBUG, "32b writes\n"); + //---------------- 32b writes + start = get_us_since_boot(); + dword = 0; + for (ptr=(uint32_t *)0xff76d000;ptr<(uint32_t *)0xff76e000;ptr+=4) { + *ptr = dword; + dword++; + } + finish = get_us_since_boot(); + diff = finish-start; + printk(BIOS_DEBUG, "0x1000 bytes, in %d usec\n", diff); + } + + //--------------- 32b reads + printk(BIOS_DEBUG, "32b reads\n"); + start = get_us_since_boot(); + total = 0; + for (ptr=(uint32_t *)0xff76d000;ptr<(uint32_t *)0xff76e000;ptr+=4) { + dword = *ptr; + total+=dword; + } + finish = get_us_since_boot(); + diff = finish-start; + printk(BIOS_DEBUG, "0x1000 bytes, in %d usec\n", diff); + printk(BIOS_DEBUG, "TOTAL: %lld\n", total); + + //------------- 64b reads. Should prefetch + printk(BIOS_DEBUG, "64b reads\n"); + start = get_us_since_boot(); + total = 0; + for (qword_ptr=(uint64_t *)0xff76e000;qword_ptr<(uint64_t *)0xff76f000;qword_ptr+=8) { + qword = *qword_ptr; + total+=qword; + } + finish = get_us_since_boot(); + diff = finish-start; + printk(BIOS_DEBUG, "0x1000 bytes, in %d usec\n", diff); + printk(BIOS_DEBUG, "TOTAL: %lld\n", total); + + //------------ burst read + printk(BIOS_DEBUG, "burst read\n"); + start = 0; + pci_write_config32(_LPCB_DEV, 0xb0, 0xff76f000); //src addr for DMA + pci_write_config32(_LPCB_DEV, 0xb4, 0x40000000); //dest addr - put it at 1GB + dword = pci_read_config32(_LPCB_DEV, LPC_ROM_DMA_EC_HOST_CONTROL); + dword |= 0x1; //tell it GO GO GO + dword |= 0x0FC0; //pull this many cachelines+1 pf 64B which... should be be 0x1000. [15:6] 0x1000 + pci_write_config32(_LPCB_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, dword); + for (i=0;i<1000;i++) { + dword = pci_read_config32(_LPCB_DEV, LPC_ROM_DMA_EC_HOST_CONTROL); + if ((dword & 0x1) == 0) break; + udelay(10); + } + if (i>=100) { + printk(BIOS_ERR, "Took too long to run DMA\n"); + } + finish = get_us_since_boot(); + diff = finish-start; + printk(BIOS_DEBUG, "0x1000 bytes, in %d usec\n", diff); + +} + /* Before console init */ void fch_pre_init(void) { @@ -141,6 +254,8 @@ lpc_configure_decodes(); fch_spi_early_init(); + + enable_acpimmio_decode_pm04(); fch_smbus_init(); sb_enable_cf9_io(); @@ -156,6 +271,7 @@ if (CONFIG(PICASSO_CONSOLE_UART)) set_uart_config(CONFIG_UART_FOR_CONSOLE); + } static void print_num_status_bits(int num_bits, uint32_t status, @@ -216,6 +332,9 @@ sb_print_pmxc0_status(); i2c_soc_early_init(); + printk(BIOS_DEBUG, "Measure spi before espi setup\n"); + measure_spi(); + if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) lpc_disable_spi_rom_sharing(); @@ -223,6 +342,9 @@ espi_setup(); espi_configure_decodes(); } + + printk(BIOS_DEBUG, "Measure spi after espi setup\n"); + measure_spi(); } void sb_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/44229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a27c2153e6f258ef2f6a2f6c7de4f6965d535f5 Gerrit-Change-Number: 44229 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Peers <epeers(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio: nuvoton: add a driver for nct668xd
by Michael Niewöhner (Code Review) 19 Oct '21

19 Oct '21

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34948 ) Change subject: superio: nuvoton: add a driver for nct668xd ...................................................................... superio: nuvoton: add a driver for nct668xd Change-Id: I78eca4ba2948c36a386306887f62773580f6e444 --- A src/superio/nuvoton/nct668xd/Kconfig A src/superio/nuvoton/nct668xd/Makefile.inc A src/superio/nuvoton/nct668xd/nct668Xd.h A src/superio/nuvoton/nct668xd/superio.c 4 files changed, 218 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34948/1 diff --git a/src/superio/nuvoton/nct668xd/Kconfig b/src/superio/nuvoton/nct668xd/Kconfig new file mode 100644 index 0000000..ac31463 --- /dev/null +++ b/src/superio/nuvoton/nct668xd/Kconfig @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com> +## Copyright (C) 2019 Michael Niewöhner <foss(a)mniewoehner.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_NUVOTON_NCT668XD + bool + select SUPERIO_NUVOTON_COMMON_PRE_RAM + +config SUPERIO_NUVOTON_NCT668XD_COM_A + bool + depends on SUPERIO_NUVOTON_NCT668XD + default n diff --git a/src/superio/nuvoton/nct668xd/Makefile.inc b/src/superio/nuvoton/nct668xd/Makefile.inc new file mode 100644 index 0000000..5ab05c6 --- /dev/null +++ b/src/superio/nuvoton/nct668xd/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com> +## Copyright (C) 2019 Michael Niewöhner <foss(a)mniewoehner.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT668XD) += superio.c diff --git a/src/superio/nuvoton/nct668xd/nct668Xd.h b/src/superio/nuvoton/nct668xd/nct668Xd.h new file mode 100644 index 0000000..6b74b2d --- /dev/null +++ b/src/superio/nuvoton/nct668xd/nct668Xd.h @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com> + * Copyright (C) 2019 Michael Niewöhner <foss(a)mniewoehner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_NUVOTON_NCT668XD_H +#define SUPERIO_NUVOTON_NCT668XD_H + +/* WARNING! + * NCT668XD is a "new generation" SuperIO, which implements parts of its + * functionality in firmware. That means one should check if the desired + * function/register is mentioned in the EC Space datasheet before trying + * to modify any registers in HW. + * Both datasheets (HW and EC Space) are available on request from Nuvoton. + * + * These are the warnings from the datasheet: + * 1. All GPIO pin functions should always be customized by firmware. BIOS / + * Driver should not touch all configuration registers here and related IO + * ports unless firmware opens them. + * 2. Under any situations, CR30h should always be controlled by EC and never + * be opened for BIOS / Drivers !! + * 3. Some GPIO pin functions were configured when related SW functions of EC + * Space were enabled. For such situations BIOS or application programs + * should not alter these setting to avoid abnormal function of underlying + * firmware. Please refer to EC Space Specification before going to change + * any configuration setting of GPIO pins. + */ + +/* Logical Device Numbers (LDN) */ +#define NCT668XD_PP 0x01 /* Parallel Port */ +#define NCT668XD_SP1 0x02 /* UART A */ +#define NCT668XD_SP2 0x03 /* UART B, IR */ +#define NCT668XD_KBC 0x05 /* Keyboard Controller */ +#define NCT668XD_CIR 0x06 /* Consumer IR */ +#define NCT668XD_GPIO01234567 0x07 /* GPIO 0-7 */ +#define NCT668XD_PORT80 0x08 /* Port 80 UART */ +#define NCT668XD_GPIO89 0x09 /* GPIO 8-9, GPIO 1-8 Alternate \ + * Func., GPIO 0-1 Enhance Group \ + */ +#define NCT668XD_ACPI 0x0A /* ACPI */ +#define NCT668XD_EC 0x0B /* EC Space */ +#define NCT668XD_DSLP_PWRFAULT 0x0D /* Deep Sleep, Power Fault */ +#define NCT668XD_FAN_ASSIGN 0x0E /* Fan Assignment */ + +/* Virtual LDNs */ +#define NCT668XD_WDT1 ((0 << 8) | NCT668XD_WDT1_WDTMEM_GPIO01) +#define NCT668XD_WDTMEM ((4 << 8) | NCT668XD_WDT1_WDTMEM_GPIO01) +#define NCT668XD_GPIO0 ((0 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO1 ((1 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO2 ((2 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO3 ((3 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO4 ((4 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO5 ((5 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO6 ((6 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO7 ((7 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO8 ((0 << 8) | NCT668XD_GPIO89) +#define NCT668XD_GPIO9 ((1 << 8) | NCT668XD_GPIO89) +#define NCT668XD_DS5 ((0 << 8) | NCT668XD_DS) +#define NCT668XD_DS3 ((1 << 8) | NCT668XD_DS) +#define NCT668XD_PCHDSW ((3 << 8) | NCT668XD_DS) +#define NCT668XD_DSWWOPT ((4 << 8) | NCT668XD_DS) +#define NCT668XD_DS3OPT ((5 << 8) | NCT668XD_DS) +#define NCT668XD_DSDSS ((6 << 8) | NCT668XD_DS) +#define NCT668XD_DSPU ((7 << 8) | NCT668XD_DS) + + +#endif /* SUPERIO_NUVOTON_NCT668XD_H */ diff --git a/src/superio/nuvoton/nct668xd/superio.c b/src/superio/nuvoton/nct668xd/superio.c new file mode 100644 index 0000000..99d448d --- /dev/null +++ b/src/superio/nuvoton/nct668xd/superio.c @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2015 Matt DeVillier <matt.devillier(a)gmail.com> + * Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com> + * Copyright (C) 2019 Michael Niewöhner <foss(a)mniewoehner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include <superio/conf_mode.h> + +#include "nct668Xd.h" + + +static void nct668Xd_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case NCT668XD_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct668Xd_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, NCT668XD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, + 0x0ff8, }, + { NULL, NCT668XD_SP1, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT668XD_SP2, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT668XD_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, + 0x0fff, 0x0fff, }, + { NULL, NCT668XD_CIR, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT668XD_PORT80}, + { NULL, NCT668XD_ACPI}, + { NULL, NCT668XD_EC, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT668XD_DSLP_PWRFAULT}, + { NULL, NCT668XD_FAN_ASSIGN}, + { NULL, NCT668XD_WDT1}, + { NULL, NCT668XD_WDTMEM}, + { NULL, NCT668XD_GPIO0}, + { NULL, NCT668XD_GPIO1}, + { NULL, NCT668XD_GPIO2}, + { NULL, NCT668XD_GPIO3}, + { NULL, NCT668XD_GPIO4}, + { NULL, NCT668XD_GPIO5}, + { NULL, NCT668XD_GPIO6}, + { NULL, NCT668XD_GPIO7}, + { NULL, NCT668XD_GPIO8}, + { NULL, NCT668XD_GPIO9}, + { NULL, NCT668XD_DS5}, + { NULL, NCT668XD_DS3}, + { NULL, NCT668XD_PCHDSW}, + { NULL, NCT668XD_DSWWOPT}, + { NULL, NCT668XD_DS3OPT}, + { NULL, NCT668XD_DSDSS}, + { NULL, NCT668XD_DSPU}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct668Xd_ops = { + CHIP_NAME("NUVOTON NCT668XD Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/34948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78eca4ba2948c36a386306887f62773580f6e444 Gerrit-Change-Number: 34948 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

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