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Hello Hung-Te Lin, Xi Chen, build bot (Jenkins), Patrick Georgi, Martin Roth, Yu-Ping Wu, Yidi Lin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51966
to look at the new patch set (#5).
Change subject: soc/mediatek: add new driver 'msdc' for eMMC
......................................................................
soc/mediatek: add new driver 'msdc' for eMMC
Add MTK host mmc driver support.
MTK host controller support eMMC5.1 spec.
BUG=b:177389446
TEST=emerge-asurada coreboot
BRANCH=asurada
Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com>
Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725
---
M src/commonlib/include/commonlib/sd_mmc_ctrlr.h
A src/soc/mediatek/common/include/soc/msdc.h
A src/soc/mediatek/common/msdc.c
M src/soc/mediatek/mt8192/Makefile.inc
4 files changed, 685 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/51966/5
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: mb/google/asurada: early-init eMMC
......................................................................
mb/google/asurada: early-init eMMC
Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to
access eMMC in the very early stage (for example, Depthcharge needs it
20ms after started) so we have to start initialization in coreboot.
On Hayato Chromebook this can save ~100ms in total.
BUG=b:177389446
TEST=emerge-asurada coreboot
BRANCH=asurada
Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com>
Change-Id: I2f58d203e969dc1a13a479d7dc63b1b162a9ae3f
---
M src/mainboard/google/asurada/mainboard.c
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/51973/3
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Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51973 )
Change subject: mb/google/asurada: early-init eMMC
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/asurada/mainboard.c:
https://review.coreboot.org/c/coreboot/+/51973/comment/cb6ff41a_260d06ca
PS2, Line 29:
Use tabs for alignment
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Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52018 )
Change subject: mb/facebook/monolith: Remove disabled devices from devicetree
......................................................................
mb/facebook/monolith: Remove disabled devices from devicetree
All known on-chip PCI devices are disabled in the chipset devicetree.
So they are removed from the mainboard devicetree.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: Ie67cd8afc9ea92e9fd7caed4338cb25a68d94cb1
Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com>
---
M src/mainboard/facebook/monolith/devicetree.cb
1 file changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/52018/1
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index 974d00e..13b3abc 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -225,12 +225,10 @@
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # Thermal Subsystem
- device pci 05.0 off end # SA IMGU
device pci 08.0 on end # Gaussian Mixture Model
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
- device pci 14.3 off end # Camera
device pci 17.0 on end # SATA
device pci 1c.2 on end # PCI Express Port 3 x1 baseboard WWAN
device pci 1c.5 on end # PCI Express Port 6 x1 baseboard i210
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Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52017 )
Change subject: mb/google/guybrush: Enable camera power GPIO
......................................................................
mb/google/guybrush: Enable camera power GPIO
Configure camera power GPIO to high
BUG=b:182207799
TEST=Build and boot to OS then checked camera device existence with lsusb
Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com>
Change-Id: Ie894167e3c4f8efdb3710599c6ff3a9fc975adb6
---
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/52017/1
diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
index e386658..1921411 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c
+++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
@@ -87,7 +87,7 @@
/* RAM_ID_2 / DEV_BEEP_LRCLK */
PAD_GPI(GPIO_75, PULL_NONE),
/* EN_PP3300_CAM */
- PAD_GPO(GPIO_76, LOW),
+ PAD_GPO(GPIO_76, HIGH),
/* GPIO_77 - GPIO_83: Not available */
/* EC_SOC_INT_ODL */
PAD_GPI(GPIO_84, PULL_NONE),
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Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51918 )
Change subject: mb/google/kukui: katsu: update the EDID and initial code
......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51918/comment/73941346_8cc1da0d
PS1, Line 7: intial
> Yes!it is~
Ack
https://review.coreboot.org/c/coreboot/+/51918/comment/b6f9bf4c_40a110d0
PS1, Line 11: None
> ok, i will create an issue tracker and add vendor in it.
Done
https://review.coreboot.org/c/coreboot/+/51918/comment/03e25936_98cd0746
PS1, Line 12: TEST=Boots on Chromebook Katsu and displayed developer firmware screen successfully.
> YES,but the vendor update the EDID information and initial code to fix the mipi test fail issue.
Ack
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