coreboot-gerrit April 2021

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Change in coreboot[master]: mb/ocp/tiogapass: correct "POST complete" pad initial value
by Tim Wawrzynczak (Code Review) 05 Apr '21

05 Apr '21

Attention is currently required from: Michael Niewöhner. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48670 ) Change subject: mb/ocp/tiogapass: correct "POST complete" pad initial value ...................................................................... Patch Set 20: Code-Review+2 (1 comment) Patchset: PS20: That is one heck of a schematic at 270 pages... -- To view, visit https://review.coreboot.org/c/coreboot/+/48670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82fbda1caba9163ba3b2e38f494a0cefa27e657f Gerrit-Change-Number: 48670 Gerrit-PatchSet: 20 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Mon, 05 Apr 2021 18:33:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Enable camera power GPIO
by Martin Roth (Code Review) 05 Apr '21

05 Apr '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52017 ) Change subject: mb/google/guybrush: Enable camera power GPIO ...................................................................... mb/google/guybrush: Enable camera power GPIO Configure camera power GPIO to high BUG=b:182207799 TEST=Build and boot to OS then checked camera device existence with lsusb Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Change-Id: Ie894167e3c4f8efdb3710599c6ff3a9fc975adb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52017 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Bhanu Prakash Maiya: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 761335c..05b57fc 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -88,7 +88,7 @@ /* RAM_ID_2 / DEV_BEEP_LRCLK */ PAD_GPI(GPIO_75, PULL_NONE), /* EN_PP3300_CAM */ - PAD_GPO(GPIO_76, LOW), + PAD_GPO(GPIO_76, HIGH), /* GPIO_77 - GPIO_83: Not available */ /* EC_SOC_INT_ODL */ PAD_GPI(GPIO_84, PULL_NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/52017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie894167e3c4f8efdb3710599c6ff3a9fc975adb6 Gerrit-Change-Number: 52017 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Enable camera power GPIO
by Martin Roth (Code Review) 05 Apr '21

05 Apr '21

Attention is currently required from: Ivy Jian, Karthik Ramasubramanian. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52017 ) Change subject: mb/google/guybrush: Enable camera power GPIO ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie894167e3c4f8efdb3710599c6ff3a9fc975adb6 Gerrit-Change-Number: 52017 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 05 Apr 2021 18:30:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Update GPIO configuration
by Martin Roth (Code Review) 05 Apr '21

05 Apr '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51675 ) Change subject: mb/google/guybrush: Update GPIO configuration ...................................................................... mb/google/guybrush: Update GPIO configuration Initialize all eSPI signals including PCIE_RST0_L early for EC communication. - Set PCIE_RST0_L to a GPIO and set it high to release the bus. This is a temporary workaround until PCIE_RST_L comes up on its own. - Make sure all GPIO muxes initialized early are re-initialized. BUG=b:183340503 TEST=Boot Guybrush Change-Id: I512cb8b435dc8412cd46189e741ad94e5a24699e Signed-off-by: Martin Roth <martinroth(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51675 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c 1 file changed, 11 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index ba392b4..761335c 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -54,7 +54,8 @@ PAD_GPO(GPIO_24, LOW), /* GPIO_25: Not available */ /* PCIE_RST0_L */ - PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* TODO: change back to PCIE_RST_L when we figure out why PCIE_RST doesn't go high. */ + PAD_GPO(GPIO_26, HIGH), /* PCIE_RST1_L */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* GPIO_28: Not available */ @@ -93,7 +94,7 @@ PAD_GPI(GPIO_84, PULL_NONE), /* WWAN_DISABLE */ PAD_GPO(GPIO_85, HIGH), - /* SPI_CLK2 */ + /* ESPI_SOC_CLK */ PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), /* RAM_ID_1 / DEV_BEEP_DATA */ PAD_GPI(GPIO_87, PULL_NONE), @@ -116,6 +117,8 @@ PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE), /* ESPI1_DATA3 */ PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), /* RAM_ID_0 / DEV_BEEP_EN */ PAD_GPI(GPIO_109, PULL_NONE), /* GPIO_110 - GPIO_112: Not available */ @@ -169,6 +172,12 @@ PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), /* I2C3_SDA */ PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* PCIE_RST0_L */ + PAD_GPO(GPIO_26, HIGH), + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_SOC_CLK */ + PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), /* ESPI1_DATA0 */ PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE), /* ESPI1_DATA1 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/51675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I512cb8b435dc8412cd46189e741ad94e5a24699e Gerrit-Change-Number: 51675 Gerrit-PatchSet: 12 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Mathew King <mathewk(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Enable Camera in ADL-M RVP
by Rizwan Qureshi (Code Review) 05 Apr '21

05 Apr '21

Attention is currently required from: Varshit B Pandya, Subrata Banik. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50265 ) Change subject: mb/intel/adlrvp: Enable Camera in ADL-M RVP ...................................................................... Patch Set 22: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70636eaa8d9bdf23d649e811b3ff4f33b1bc604e Gerrit-Change-Number: 50265 Gerrit-PatchSet: 22 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-CC: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Mon, 05 Apr 2021 18:11:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: chromeec: Rewrite google_chromeec_status_check
by Martin Roth (Code Review) 05 Apr '21

05 Apr '21

Attention is currently required from: Paul Menzel, Rob Barnes. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51775 ) Change subject: chromeec: Rewrite google_chromeec_status_check ...................................................................... Patch Set 4: (3 comments) File src/ec/google/chromeec/ec_lpc.c: https://review.coreboot.org/c/coreboot/+/51775/comment/43cbeca7_db100a32 PS4, Line 100: 1 > > I'm playing with this value right now, but I think this is the source of our problems. […] Issue has been fixed. https://review.coreboot.org/c/coreboot/+/51775/comment/0bc9ce90_cc9ca961 PS4, Line 105: return 0; > Print the stopwatch value in a spew message? This call happens pretty frequently. I'm not sure that's really useful. https://review.coreboot.org/c/coreboot/+/51775/comment/ab16a2e0_0f01dcf4 PS4, Line 108: > Please print a warning/error with the timeout value. As mentioned above, I don't think that it's particularly useful, except during board bringup. -- To view, visit https://review.coreboot.org/c/coreboot/+/51775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I363ff7453bcf81581884f92797629a6f96d42580 Gerrit-Change-Number: 51775 Gerrit-PatchSet: 4 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Mon, 05 Apr 2021 17:45:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: DNS: Give Guybrush's EC time to breathe
by Martin Roth (Code Review) 05 Apr '21

05 Apr '21

Martin Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/51913 ) Change subject: DNS: Give Guybrush's EC time to breathe ...................................................................... Abandoned No longer needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/51913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I101a63c6133900183192fc45fabf9fc09cb892be Gerrit-Change-Number: 51913 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/amd/common: Add some ESPI register definitions
by Martin Roth (Code Review) 05 Apr '21

05 Apr '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51747 ) Change subject: soc/amd/common: Add some ESPI register definitions ...................................................................... soc/amd/common: Add some ESPI register definitions Use definitions instead of magic numbers clean up some whitespace while I'm here. BUG=b:183207262 TEST=Build Change-Id: Ieae53b12e5303641fb3f180c47468aaa6906e9af Signed-off-by: Martin Roth <martinroth(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51747 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/espi.h 1 file changed, 15 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index 435b81f..82bfcbe 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -13,13 +13,23 @@ #define ESPI_DECODE_MMIO_RANGE_EN(range) (1 << (((range) & 3) + 12)) #define ESPI_DECODE_IO_RANGE_EN(range) (1 << (((range) & 3) + 8)) #define ESPI_DECODE_IO_0x80_EN (1 << 2) -#define ESPI_DECODE_IO_0X60_0X64_EN (1 << 1) +#define ESPI_DECODE_IO_0X60_0X64_EN (1 << 1) #define ESPI_DECODE_IO_0X2E_0X2F_EN (1 << 0) -#define ESPI_IO_RANGE_BASE(range) (0x44 + ((range) & 3) * 2) -#define ESPI_IO_RANGE_SIZE(range) (0x4c + ((range) & 3)) -#define ESPI_MMIO_RANGE_BASE(range) (0x50 + ((range) & 3) * 4) -#define ESPI_MMIO_RANGE_SIZE(range) (0x60 + ((range) & 3) * 2) +#define ESPI_IO_BASE_OFFSET_REG0 0x44 +#define ESPI_IO_BASE_OFFSET_REG1 0x48 +#define ESPI_IO_RANGE_SIZE_OFFSET 0x4c +#define ESPI_MMIO_BASE_OFFSET_REG0 0x50 +#define ESPI_MMIO_BASE_OFFSET_REG1 0x54 +#define ESPI_MMIO_BASE_OFFSET_REG2 0x58 +#define ESPI_MMIO_BASE_OFFSET_REG3 0x5C +#define ESPI_MMIO_OFFSET_SIZE_REG0 0x60 +#define ESPI_MMIO_OFFSET_SIZE_REG1 0x64 + +#define ESPI_IO_RANGE_BASE(range) (ESPI_IO_BASE_OFFSET_REG0 + ((range) & 3) * 2) +#define ESPI_IO_RANGE_SIZE(range) (ESPI_IO_RANGE_SIZE_OFFSET + ((range) & 3)) +#define ESPI_MMIO_RANGE_BASE(range) (ESPI_MMIO_BASE_OFFSET_REG0 + ((range) & 3) * 4) +#define ESPI_MMIO_RANGE_SIZE(range) (ESPI_MMIO_OFFSET_SIZE_REG0 + ((range) & 3) * 2) #define ESPI_GENERIC_IO_WIN_COUNT 4 #define ESPI_GENERIC_IO_MAX_WIN_SIZE 0x100 -- To view, visit https://review.coreboot.org/c/coreboot/+/51747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieae53b12e5303641fb3f180c47468aaa6906e9af Gerrit-Change-Number: 51747 Gerrit-PatchSet: 7 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: add add_chipset_state_cbmem()
by Martin Roth (Code Review) 05 Apr '21

05 Apr '21

Martin Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/51751 ) Change subject: soc/amd/cezanne: add add_chipset_state_cbmem() ...................................................................... Abandoned Letting felix handle this as part of the chipset code. -- To view, visit https://review.coreboot.org/c/coreboot/+/51751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3de3764c99fe89b962db88065575463b365ddaf5 Gerrit-Change-Number: 51751 Gerrit-PatchSet: 5 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: util/bincfg/Makefile: change ./bincfg to $(abspath $(TARGET))
by Martin Roth (Code Review) 05 Apr '21

05 Apr '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52111 ) Change subject: util/bincfg/Makefile: change ./bincfg to $(abspath $(TARGET)) ...................................................................... util/bincfg/Makefile: change ./bincfg to $(abspath $(TARGET)) This change was promised as a follow-up in change ID: Ic0302f663cbc931325334d0cce93d3b0bf937cc6 Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I9a41b46cc90684746e2b240c8ee442df1b3d7cf5 --- M util/bincfg/Makefile 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/52111/1 diff --git a/util/bincfg/Makefile b/util/bincfg/Makefile index 2dc5073..ca375a5 100644 --- a/util/bincfg/Makefile +++ b/util/bincfg/Makefile @@ -20,21 +20,21 @@ # Use this target to generate GbE for X200 gen-gbe-ich9m: $(TARGET) - ./bincfg gbe-ich9m.spec gbe-ich9m.set gbe1.bin + $(abspath $(TARGET)) gbe-ich9m.spec gbe-ich9m.set gbe1.bin # duplicate binary as per spec cat gbe1.bin gbe1.bin > flashregion_3_gbe.bin rm -f gbe1.bin # Use this target to generate GbE for X220/x230 gen-gbe-82579LM: $(TARGET) - ./bincfg gbe-82579LM.spec gbe-82579LM.set gbe1.bin + $(abspath $(TARGET)) gbe-82579LM.spec gbe-82579LM.set gbe1.bin # duplicate binary as per spec cat gbe1.bin gbe1.bin > flashregion_3_gbe.bin rm -f gbe1.bin # Use this target to generate IFD for X200 gen-ifd-x200: $(TARGET) - ./bincfg ifd-x200.spec ifd-x200.set flashregion_0_fd.bin + $(abspath $(TARGET)) ifd-x200.spec ifd-x200.set flashregion_0_fd.bin clean: rm -f *.lex.c *.tab.c *.tab.h *.o bincfg flashregion_0_fd.bin flashregion_3_gbe.bin -- To view, visit https://review.coreboot.org/c/coreboot/+/52111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a41b46cc90684746e2b240c8ee442df1b3d7cf5 Gerrit-Change-Number: 52111 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2021