coreboot-gerrit April 2021

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Change in coreboot[master]: vc/amd/agesa/[...]/Proc/Mem: Fix uninitialized scalar variable
by Name of user not set (Code Review) 03 Aug '23

03 Aug '23

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38495 ) Change subject: vc/amd/agesa/[...]/Proc/Mem: Fix uninitialized scalar variable ...................................................................... vc/amd/agesa/[...]/Proc/Mem: Fix uninitialized scalar variable FinalRxEnCycle[ByteLane] does not get set in mtthrcSeedTrain.c if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && \ ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) evaluates FALSE. According to Coverity, this could result in cases where RxEnDlyTargetValue[ByteLane] = FinalRxEnCycle[ByteLane] is used with an uninitialized value. Move the FinalRxEnCycle[ByteLane] initial assignment up a line so it gets initialized regardless. Tested on Lenovo G505s. Change-Id: Id1d3580c8915ba31e87059851fec2ae4b8b0e1da Signed-off-by: Joe Moore <awokd(a)danwin1210.me> Found-by: Coverity CID 1370599 --- M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/38495/1 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c index 991667b..d21c246 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c @@ -504,8 +504,8 @@ for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { if (RxEnDlyTargetFound[ByteLane] == FALSE) { MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); + FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE : (TechPtr->ByteLaneError[ByteLane] && DlyWrittenToReg[ByteLane])) { - FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) { // Since FailTestRxEnDly, we can set FinalRxEnCycle MemTRdPosRxEnSeedSetDly3 (TechPtr, (UINT16) FinalRxEnCycle[ByteLane], ByteLane); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c index 1446f3e..7ea7c56 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c @@ -505,8 +505,8 @@ for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { if (RxEnDlyTargetFound[ByteLane] == FALSE) { MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); + FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE : (TechPtr->ByteLaneError[ByteLane] && DlyWrittenToReg[ByteLane])) { - FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) { // Since FailTestRxEnDly, we can set FinalRxEnCycle MemTRdPosRxEnSeedSetDly3 (TechPtr, (UINT16) FinalRxEnCycle[ByteLane], ByteLane); -- To view, visit https://review.coreboot.org/c/coreboot/+/38495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1d3580c8915ba31e87059851fec2ae4b8b0e1da Gerrit-Change-Number: 38495 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

3 9

Change in ...coreboot[master]: mb/pcengines/apu2: describe serial ports in ACPI
by Michał Żygowski (Code Review) 03 Aug '23

03 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32989 Change subject: mb/pcengines/apu2: describe serial ports in ACPI ...................................................................... mb/pcengines/apu2: describe serial ports in ACPI FreeBSD users had to manually configure serial ports on their installations. Defining serial ports in ACPI save that effort. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0de4172a1884abbe9d625060a9045c9d71469e27 --- A src/mainboard/pcengines/apu2/acpi/superio.asl M src/mainboard/pcengines/apu2/dsdt.asl 2 files changed, 68 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/32989/1 diff --git a/src/mainboard/pcengines/apu2/acpi/superio.asl b/src/mainboard/pcengines/apu2/acpi/superio.asl new file mode 100644 index 0000000..c61e3d7 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/superio.asl @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 PC Engines Gmbh + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.LIBR) { + + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + } + EndDependentFn () + }) + } + + Device (COM2) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 2) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x02F8, 0x2F8, 0x08, 0x08) + IRQNoFlags () {3} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, 0x02F8, 0x2F8, 0x08, 0x08) + IRQNoFlags () {3} + } + EndDependentFn () + }) + } +} \ No newline at end of file diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl index 3bf0ed6..409f03d 100644 --- a/src/mainboard/pcengines/apu2/dsdt.asl +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -81,5 +81,8 @@ /* Define the System Indicators for the platform */ #include "acpi/si.asl" + + /* Super IO devices (COM ports) */ + #include "acpi/superio.asl" } /* End of ASL file */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0de4172a1884abbe9d625060a9045c9d71469e27 Gerrit-Change-Number: 32989 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

6 12

Change in coreboot[master]: soc/intel/common: Extend criteria to determine CSE fimrware update
by Sridhar Siricilla (Code Review) 03 Aug '23

03 Aug '23

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46553 ) Change subject: soc/intel/common: Extend criteria to determine CSE fimrware update ...................................................................... soc/intel/common: Extend criteria to determine CSE fimrware update The patch extends criteria to determine the CSE Firmware Update. As part of exended criteria, coreboot checks for IFWI Build Version field besides CSE RW partition signature corruption and CSE RW version. Having this additional check to help coreboot to trigger CSE Fimrware update when there is no change in CSE firmware but in other components like TCSS etc. TEST=Verified on hatch. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I129a6461e2f53259560c0e5d7d3b2fb85c8b3238 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 38 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/46553/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index a7bb757..77a8d5f 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -173,7 +173,7 @@ /* CSE CBFS RW version */ struct fw_version fw_ver; - uint8_t reserved1[4]; + uint32_t ifwi_build_ver; /* * CSE RW blob needs to be moved outside of FW_MAIN_A and FW_MAIN_B to reduce the boot * time. When the RW blob is placed outside of FW_MAIN_A and FW_MAIN_B, coreboot needs @@ -186,6 +186,22 @@ uint8_t reserved2[4]; }; +/* CSE Boot Partition Descriptor Table Header */ +struct cse_bpdt { + + /* Signature:0x000055AA is expected for a valid BP */ + uint32_t signature; + + /* reserved field */ + uint8_t reserved[8]; + + /* ifwi build version */ + uint32_t ifwi_build_ver; + + /* FIT tool version */ + struct fw_version fit_tool_ver; +}; + static void cse_log_status_registers(void) { printk(BIOS_DEBUG, "cse_lite: CSE status registers: HFSTS1: 0x%x, HFSTS2: 0x%x " @@ -592,6 +608,9 @@ source_info->fw_ver.hotfix, source_info->fw_ver.build); + printk(BIOS_SPEW, "cse_lite: IFWI build version: %u\n", + source_info->ifwi_build_ver); + printk(BIOS_SPEW, "cse_lite: CSE CBFS RW's hash: "); for (uint8_t i = 0; i < VB2_SHA256_DIGEST_SIZE; i++) @@ -630,6 +649,22 @@ return source_info->fw_ver.build - cse_rw_ver->build; } +static bool cse_is_ifwi_build_version_latest(const struct cse_cbfs_rw_info *source_info, + const struct region_device *target_dev) +{ + uint32_t ifwi_build_ver; + uint8_t ifwi_build_ver_offset = offsetof(struct cse_bpdt, ifwi_build_ver); + + if (rdev_readat(target_dev, &ifwi_build_ver, ifwi_build_ver_offset, + sizeof(ifwi_build_ver)) != sizeof(ifwi_build_ver)) { + printk(BIOS_ERR, "cse_lite: Failed to read IFWI build version from" + "CSE RW partition\n"); + return false; + } + + return (ifwi_build_ver == source_info->ifwi_build_ver); +} + /* The function calculates SHA-256 of CSE RW blob and compares it with the provided SHA value */ static bool cse_verify_cbfs_rw_sha256(const uint8_t *expected_rw_blob_sha, const void *rw_blob, const size_t rw_blob_sz) @@ -719,7 +754,8 @@ const struct cse_cbfs_rw_info *source_info, struct region_device *target_rdev) { return (!cse_is_rw_bp_sign_valid(target_rdev) || - !cse_is_rw_version_latest(cse_bp_info, source_info)); + !cse_is_rw_version_latest(cse_bp_info, source_info) || + !cse_is_ifwi_build_version_latest(source_info, target_rdev)); } static bool cse_write_rw_region(const struct region_device *target_rdev, -- To view, visit https://review.coreboot.org/c/coreboot/+/46553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I129a6461e2f53259560c0e5d7d3b2fb85c8b3238 Gerrit-Change-Number: 46553 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in ...libgfxinit[master]: [WIP] gma: Add Gemini Lake support
by Nico Huber (Code Review) 02 Aug '23

02 Aug '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/31611 Change subject: [WIP] gma: Add Gemini Lake support ...................................................................... [WIP] gma: Add Gemini Lake support Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M common/Makefile.inc M common/broxton/hw-gfx-gma-ddi_phy.ads M common/broxton/hw-gfx-gma-plls.adb M common/broxton/hw-gfx-gma-power_and_clocks.adb M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.ads R configs/apollolake C configs/geminilake 9 files changed, 109 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/11/31611/1 diff --git a/common/Makefile.inc b/common/Makefile.inc index 61955eb..cfb2dfa 100644 --- a/common/Makefile.inc +++ b/common/Makefile.inc @@ -68,7 +68,7 @@ subdirs-y += ironlake else ifneq ($(filter Haswell Broadwell,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared haswell -else ifneq ($(filter Broxton,$(CONFIG_GFX_GMA_CPU)),) +else ifneq ($(filter Apollolake Geminilake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared broxton else ifneq ($(filter Skylake Kabylake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared skylake diff --git a/common/broxton/hw-gfx-gma-ddi_phy.ads b/common/broxton/hw-gfx-gma-ddi_phy.ads index fc6cacf..e6301bf 100644 --- a/common/broxton/hw-gfx-gma-ddi_phy.ads +++ b/common/broxton/hw-gfx-gma-ddi_phy.ads @@ -16,7 +16,7 @@ private package HW.GFX.GMA.DDI_Phy is - type T is (BC, A); + type T is (BC, A, C); procedure Power_On (Phy : T); procedure Power_Off (Phy : T); diff --git a/common/broxton/hw-gfx-gma-plls.adb b/common/broxton/hw-gfx-gma-plls.adb index 087ff12..f7ecc05 100644 --- a/common/broxton/hw-gfx-gma-plls.adb +++ b/common/broxton/hw-gfx-gma-plls.adb @@ -170,6 +170,8 @@ PLL_10 : Registers_Index; PCS_DW12_LN01 : Registers_Index; PCS_DW12_GRP : Registers_Index; + TX_DW5_LN0 : Registers_Index; + TX_DW5_GRP : Registers_Index; end record; type Port_PLL_Array is array (Valid_PLLs) of Port_PLL_Regs; @@ -187,7 +189,9 @@ PLL_9 => BXT_PORT_PLL_9_A, PLL_10 => BXT_PORT_PLL_10_A, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_A, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_A, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_A), DPLL_B => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_B, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_B, @@ -201,7 +205,9 @@ PLL_9 => BXT_PORT_PLL_9_B, PLL_10 => BXT_PORT_PLL_10_B, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_B, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_B, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_B), DPLL_C => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_C, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_C, @@ -215,11 +221,15 @@ PLL_9 => BXT_PORT_PLL_9_C, PLL_10 => BXT_PORT_PLL_10_C, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_C, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C)); + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_C, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_C)); PORT_PLL_ENABLE : constant := 1 * 2 ** 31; PORT_PLL_ENABLE_LOCK : constant := 1 * 2 ** 30; PORT_PLL_ENABLE_REF_SEL : constant := 1 * 2 ** 27; + PORT_PLL_POWER_ENABLE : constant := 1 * 2 ** 26; + PORT_PLL_POWER_STATE : constant := 1 * 2 ** 25; PORT_PLL_EBB0_P1_SHIFT : constant := 13; PORT_PLL_EBB0_P1_MASK : constant := 16#07# * 2 ** 13; @@ -336,8 +346,17 @@ begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); - Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref - Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref + + if Config.Has_Port_PLL_Pwr_En then + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Set_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; + + Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); Unset_And_Set_Mask (Register => PORT (P).PLL_EBB_0, @@ -388,7 +407,16 @@ Wait_Set_Mask (Register => PORT (P).PLL_ENABLE, Mask => PORT_PLL_ENABLE_LOCK, - TOut_MS => 1); -- 100us + TOut_MS => 1); -- 200us + + if (Config.Has_DCC_Delay_Range) then + declare + Delay_Range : Word32; + begin + Read (PORT (P).DW5_LN0, Delay_Range); + Delay_Range := Delay_Range or PORT_TX_DW5_DCC_DELAY_RANGE_2; + Write (PORT (P).DW5_GRP, Delay_Range); + end if; Read (PORT (P).PCS_DW12_LN01, PCS); PCS := PCS and not PORT_PCS_LANE_STAGGER_MASK; @@ -471,6 +499,13 @@ begin if PLL in Valid_PLLs then Unset_Mask (PORT (PLL).PLL_ENABLE, PORT_PLL_ENABLE); + if Config.Has_Port_PLL_Pwr_En then + Unset_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Unset_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; end if; end Free; diff --git a/common/broxton/hw-gfx-gma-power_and_clocks.adb b/common/broxton/hw-gfx-gma-power_and_clocks.adb index 8aa9a21..4e3fbc3 100644 --- a/common/broxton/hw-gfx-gma-power_and_clocks.adb +++ b/common/broxton/hw-gfx-gma-power_and_clocks.adb @@ -214,22 +214,12 @@ ---------------------------------------------------------------------------- - CDClk_Ref : constant := 19_200_000; - procedure Set_CDClk (Freq : Frequency_Type) with - Pre => - Freq = CDClk_Ref or Freq = 144_000_000 or Freq = 288_000_000 or - Freq = 384_000_000 or Freq = 576_000_000 or Freq = 624_000_000 + Pre => Config.Valid_CDClk (Freq) is VCO : constant Int64 := - CDClk_Ref * - (if Freq = CDClk_Ref then - 0 - elsif Freq = 624_000_000 then - 65 - else - 60); + Config.Broxton_CDClk_Ref * Config.CDClk_Ratio (Freq); CDCLK_CD2X_Div_Sel : constant Word32 := (case VCO / Freq is -- CDClk = VCO / 2 / Div when 2 => CDCLK_CD2X_DIV_SEL_1, @@ -255,7 +245,8 @@ Unset_And_Set_Mask (Register => BXT_DE_PLL_CTL, Mask_Unset => BXT_DE_PLL_RATIO_MASK, - Mask_Set => Word32 (VCO / CDClk_Ref)); + Mask_Set => (if Freq = Config.Broxton_CDClk_Ref then 0 else + Word32 (VCO / Config.Broxton_CDClk_Ref))); Write (Register => BXT_DE_PLL_ENABLE, Value => BXT_DE_PLL_PLL_ENABLE); @@ -297,7 +288,7 @@ -- Linux' i915 never keeps the PLL disabled but runs it -- at a "ratio" of 0 with CDClk at its reference clock. - Set_CDClk (CDClk_Ref); + Set_CDClk (Config.Broxton_CDClk_Ref); PW_Off (PW1); end Post_All_Off; diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 4653ae9..972cfa8 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -40,7 +40,8 @@ Has_Internal_Display : constant Boolean := Internal_Display /= None; Internal_Is_EDP : constant Boolean := Internal_Display = DP; Have_DVI_I : constant Boolean := Analog_I2C_Port /= PCH_DAC; - Has_Presence_Straps : constant Boolean := CPU /= Broxton; + Is_Broxton : constant Boolean := CPU in Apollolake..Geminilake; + Has_Presence_Straps : constant Boolean := not Is_Broxton; Is_ULT : constant Boolean := CPU_Var = ULT; Is_ULX : constant Boolean := CPU_Var = ULX; Is_LP : constant Boolean := Is_ULT or Is_ULX; @@ -57,7 +58,7 @@ Has_Pipe_MSA_Misc : constant Boolean := CPU >= Haswell; Has_Pipeconf_Misc : constant Boolean := CPU >= Broadwell; Has_Pipeconf_BPC : constant Boolean := CPU /= Haswell; - Has_Plane_Control : constant Boolean := CPU >= Broxton; + Has_Plane_Control : constant Boolean := CPU >= Apollolake; Has_DSP_Linoff : constant Boolean := CPU <= Ivybridge; Has_PF_Pipe_Select : constant Boolean := CPU in Ivybridge .. Haswell; Has_Cursor_FBC_Control : constant Boolean := CPU >= Ivybridge; @@ -73,7 +74,7 @@ Has_PCH_Panel_Power : constant Boolean := CPU >= Ironlake; ----- PCH/FDI: --------- - Has_PCH : constant Boolean := CPU /= Broxton and CPU /= G45; + Has_PCH : constant Boolean := not Is_Broxton and CPU /= G45; Has_PCH_DAC : constant Boolean := CPU in Ironlake .. Ivybridge or (CPU in Haswell .. Broadwell and not Is_LP); @@ -103,7 +104,9 @@ and Is_LP) or CPU >= Skylake; - Has_DDI_PHYs : constant Boolean := CPU = Broxton; + Has_DDI_PHYs : constant Boolean := Is_Broxton; + Has_Dual_DDI_Phy_BC : constant Boolean := CPU = Apollolake; + Has_Port_PLL_Pwr_En : constant Boolean := CPU = Geminilake; Has_DDI_D : constant Boolean := CPU >= Haswell and not Is_LP and @@ -112,8 +115,8 @@ Has_DDI_D; Has_DDI_Buffer_Trans : constant Boolean := CPU >= Haswell and - CPU /= Broxton; - Has_Low_Voltage_Swing : constant Boolean := CPU >= Broxton; + not Is_Broxton; + Has_Low_Voltage_Swing : constant Boolean := CPU >= Apollolake; Has_Iboost_Config : constant Boolean := CPU >= Skylake; Use_KBL_DDI_Buf_Trans : constant Boolean := CPU = Kabylake; @@ -126,7 +129,7 @@ ----- GMBUS: ----------- Ungate_GMBUS_Unit_Level : constant Boolean := CPU >= Skylake; - GMBUS_Alternative_Pins : constant Boolean := CPU = Broxton; + GMBUS_Alternative_Pins : constant Boolean := Is_Broxton; Has_PCH_GMBUS : constant Boolean := CPU >= Ironlake; ----- Power: ----------- @@ -178,7 +181,8 @@ DP3 => CPU_Var = Normal, Analog => CPU_Var = Normal, others => True), - Broxton => + Apollolake | + Geminilake => (Internal => Config.Internal_Display = DP, DP1 => True, DP2 => True, @@ -234,11 +238,12 @@ Default_DDI_HDMI_Buffer_Translation : constant DDI_HDMI_Buf_Trans_Range := (case CPU is - when Haswell => 6, - when Broadwell => 7, - when Broxton => 8, - when Skylake => 8, - when others => 0); + when Haswell => 6, + when Broadwell => 7, + when Apollolake | + Geminilake => 8, + when Skylake => 8, + when others => 0); ---------------------------------------------------------------------------- @@ -250,7 +255,8 @@ Ivybridge => 400_000_000, when Haswell | Broadwell => (if Is_ULX then 337_500_000 else 450_000_000), - when Broxton => 288_000_000, + when Apollolake => 288_000_000, + when Geminilake => 158_400_000, when Skylake | Kabylake => 337_500_000); @@ -262,13 +268,34 @@ Ivybridge => 125_000_000, when Haswell | Broadwell => (if Is_LP then 24_000_000 else 125_000_000), - when Broxton => Frequency_Type'First, -- none needed + when Apollolake | + Geminilake => Frequency_Type'First, -- none needed when Skylake | Kabylake => 24_000_000); Raw_Clock : Frequency_Type := Default_RawClk_Freq with Part_Of => GMA.Config_State; + Broxton_CDClk_Ref : constant := 19_200_000; + + function Valid_CDClk (Freq : Frequency_Type) return Boolean is + (case CPU is + when Geminilake => + Freq = Broxton_CDClk_Ref or Freq = 79_200_000 or + Freq = 158_400_000 or Freq = 316_800_000, + when Apollolake => + Freq = Broxton_CDClk_Ref or Freq = 144_000_000 or + Freq = 288_000_000 or Freq = 384_000_000 or + Freq = 576_000_000 or Freq = 624_000_000, + when others => + True); + + function CDClk_Ratio (Freq : Frequency_Type) return Int64 is + (case CPU is + when Geminilake => 33, + when Apollolake => if Freq = 624_000_000 then 65 else 60, + when others => 1); + ---------------------------------------------------------------------------- -- Maximum source width with enabled scaler. This only accounts @@ -414,7 +441,8 @@ when Normal => Is_Broadwell (Device_Id), when ULT => Is_Broadwell_U (Device_Id), when ULX => Is_Broadwell_Y (Device_Id)), - when Broxton => (Device_Id and 16#fffe#) = 16#5a84#, + when Apollolake => (Device_Id and 16#fffe#) = 16#5a84#, + when Geminilake => (Device_Id and 16#fffe#) = 16#3184#, when Skylake => (case CPU_Var is when Normal => Is_Skylake (Device_Id), when ULT => Is_Skylake_U (Device_Id), diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index 1220d1a..b14194b 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -413,6 +413,7 @@ BXT_PORT_TX_DW2_LN0_B, BXT_PORT_TX_DW3_LN0_B, BXT_PORT_TX_DW4_LN0_B, + BXT_PORT_TX_DW5_LN0_B, BXT_PORT_TX_DW14_LN0_B, BXT_PORT_TX_DW14_LN1_B, BXT_PORT_TX_DW14_LN2_B, @@ -422,6 +423,7 @@ BXT_PORT_TX_DW2_LN0_C, BXT_PORT_TX_DW3_LN0_C, BXT_PORT_TX_DW4_LN0_C, + BXT_PORT_TX_DW5_LN0_C, BXT_PORT_TX_DW14_LN0_C, BXT_PORT_TX_DW14_LN1_C, BXT_PORT_TX_DW14_LN2_C, @@ -431,11 +433,13 @@ BXT_PORT_TX_DW2_GRP_B, BXT_PORT_TX_DW3_GRP_B, BXT_PORT_TX_DW4_GRP_B, + BXT_PORT_TX_DW5_GRP_B, BXT_PORT_PCS_DW10_GRP_C, BXT_PORT_PCS_DW12_GRP_C, BXT_PORT_TX_DW2_GRP_C, BXT_PORT_TX_DW3_GRP_C, BXT_PORT_TX_DW4_GRP_C, + BXT_PORT_TX_DW5_GRP_C, BXT_DE_PLL_CTL, HTOTAL_EDP, HBLANK_EDP, @@ -722,6 +726,7 @@ BXT_PORT_TX_DW2_LN0_A, BXT_PORT_TX_DW3_LN0_A, BXT_PORT_TX_DW4_LN0_A, + BXT_PORT_TX_DW5_LN0_A, BXT_PORT_TX_DW14_LN0_A, BXT_PORT_TX_DW14_LN1_A, BXT_PORT_TX_DW14_LN2_A, @@ -730,7 +735,8 @@ BXT_PORT_PCS_DW12_GRP_A, BXT_PORT_TX_DW2_GRP_A, BXT_PORT_TX_DW3_GRP_A, - BXT_PORT_TX_DW4_GRP_A); + BXT_PORT_TX_DW4_GRP_A, + BXT_PORT_TX_DW5_GRP_A); pragma Warnings (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)", @@ -1351,6 +1357,7 @@ BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width, BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width, BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width, + BXT_PORT_TX_DW5_LN0_A => 16#16_2514# / Register_Width, BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width, BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width, BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width, @@ -1358,9 +1365,11 @@ BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width, BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width, BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width, + BXT_PORT_TX_DW5_GRP_A => 16#16_2d14# / Register_Width, BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width, BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width, BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width, + BXT_PORT_TX_DW5_LN0_B => 16#06_c514# / Register_Width, BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width, BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width, BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width, @@ -1368,9 +1377,11 @@ BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width, BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width, BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width, + BXT_PORT_TX_DW5_GRP_B => 16#06_cd14# / Register_Width, BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width, BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width, BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width, + BXT_PORT_TX_DW5_LN0_C => 16#06_c914# / Register_Width, BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width, BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width, BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width, @@ -1378,6 +1389,7 @@ BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width, BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width, BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width, + BXT_PORT_TX_DW5_GRP_C => 16#06_cf14# / Register_Width, -- Broxton DDI PHY ref registers BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width, diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 7ca0ca1..c282935 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -41,7 +41,8 @@ Ivybridge, Haswell, Broadwell, - Broxton, + Apollolake, + Geminilake, Skylake, Kabylake); diff --git a/configs/broxton b/configs/apollolake similarity index 83% rename from configs/broxton rename to configs/apollolake index b5f1f9a..24e0847 100644 --- a/configs/broxton +++ b/configs/apollolake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Apollolake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A diff --git a/configs/broxton b/configs/geminilake similarity index 83% copy from configs/broxton copy to configs/geminilake index b5f1f9a..be34de7 100644 --- a/configs/broxton +++ b/configs/geminilake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Geminilake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A -- To view, visit https://review.coreboot.org/c/libgfxinit/+/31611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Gerrit-Change-Number: 31611 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: mb/system76/lemp9: enable c6dram
by Jeremy Soller (Code Review) 02 Aug '23

02 Aug '23

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43625 ) Change subject: mb/system76/lemp9: enable c6dram ...................................................................... mb/system76/lemp9: enable c6dram Tested on lemp9 Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Change-Id: I9b19ad704096571f2a62f4e39051e52a720f393b --- M src/mainboard/system76/lemp9/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/43625/1 diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 3a158ed..8d77aa9 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -37,7 +37,7 @@ # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" - #register "enable_c6dram" = "1" + register "enable_c6dram" = "1" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O -- To view, visit https://review.coreboot.org/c/coreboot/+/43625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b19ad704096571f2a62f4e39051e52a720f393b Gerrit-Change-Number: 43625 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

3 16

Change in coreboot[master]: mb/asus: Add ASUS H110T mainboard
by Marvin Drees (Code Review) 10 Jul '23

10 Jul '23

Marvin Drees has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48648 ) Change subject: mb/asus: Add ASUS H110T mainboard ...................................................................... mb/asus: Add ASUS H110T mainboard This initial commit isn't yet fully working but in order to get it sorted it is pushed already. As the IGD and serial line aren't fully working yet, it is hard to tell what parts of the hardware already work and which don't. Tested payloads so far: coreinfo and tianocore. Signed-off-by: Marvin Drees <marvin(a)ceres-sys.de> Change-Id: Iab30596f2a12931679687c9f56427712b65f9363 --- A src/mainboard/asus/h110t/Kconfig A src/mainboard/asus/h110t/Kconfig.name A src/mainboard/asus/h110t/Makefile.inc A src/mainboard/asus/h110t/acpi/dptf.asl A src/mainboard/asus/h110t/acpi/ec.asl A src/mainboard/asus/h110t/acpi/mainboard.asl A src/mainboard/asus/h110t/acpi/superio.asl A src/mainboard/asus/h110t/board_info.txt A src/mainboard/asus/h110t/bootblock.c A src/mainboard/asus/h110t/cmos.default A src/mainboard/asus/h110t/cmos.layout A src/mainboard/asus/h110t/data.vbt A src/mainboard/asus/h110t/devicetree.cb A src/mainboard/asus/h110t/dsdt.asl A src/mainboard/asus/h110t/gma-mainboard.ads A src/mainboard/asus/h110t/hda_verb.c A src/mainboard/asus/h110t/include/gpio.h A src/mainboard/asus/h110t/mainboard.c A src/mainboard/asus/h110t/ramstage.c A src/mainboard/asus/h110t/romstage.c 20 files changed, 1,218 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48648/1 diff --git a/src/mainboard/asus/h110t/Kconfig b/src/mainboard/asus/h110t/Kconfig new file mode 100644 index 0000000..676ecad --- /dev/null +++ b/src/mainboard/asus/h110t/Kconfig @@ -0,0 +1,51 @@ +if BOARD_ASUS_H110T + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select SOC_INTEL_KABYLAKE + select SKYLAKE_SOC_PCH_H + select SUPERIO_NUVOTON_COMMON_COM_A + select SUPERIO_NUVOTON_NCT5539D + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + select MAINBOARD_USES_IFD_GBE_REGION + select DRIVER_INTEL_I210 + select MAINBOARD_HAS_LPC_TPM + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "asus/h110t" + +config MAINBOARD_PART_NUMBER + string + default "H110T" + +config MAX_CPUS + int + default 8 + +config DEVICETREE + string + default "devicetree.cb" + +config DIMM_SPD_SIZE + int + default 512 # DDR4 + +# This is overridden if CMOS is used for configuration values. +config MAINBOARD_POWER_ON_AFTER_POWER_FAIL + bool + default n + +endif diff --git a/src/mainboard/asus/h110t/Kconfig.name b/src/mainboard/asus/h110t/Kconfig.name new file mode 100644 index 0000000..f9d5c9c --- /dev/null +++ b/src/mainboard/asus/h110t/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_H110T + bool "H110T" diff --git a/src/mainboard/asus/h110t/Makefile.inc b/src/mainboard/asus/h110t/Makefile.inc new file mode 100644 index 0000000..ef44a4c --- /dev/null +++ b/src/mainboard/asus/h110t/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/h110t/acpi/dptf.asl b/src/mainboard/asus/h110t/acpi/dptf.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/h110t/acpi/dptf.asl diff --git a/src/mainboard/asus/h110t/acpi/ec.asl b/src/mainboard/asus/h110t/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/h110t/acpi/ec.asl diff --git a/src/mainboard/asus/h110t/acpi/mainboard.asl b/src/mainboard/asus/h110t/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/h110t/acpi/mainboard.asl diff --git a/src/mainboard/asus/h110t/acpi/superio.asl b/src/mainboard/asus/h110t/acpi/superio.asl new file mode 100644 index 0000000..800e80a --- /dev/null +++ b/src/mainboard/asus/h110t/acpi/superio.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT5539D_SHOW_SP1 +#define NCT5539D_SHOW_KBC +#define NCT5539D_SHOW_HWM + +#undef NCT5539D_SHOW_GPIO diff --git a/src/mainboard/asus/h110t/board_info.txt b/src/mainboard/asus/h110t/board_info.txt new file mode 100644 index 0000000..37aa41c --- /dev/null +++ b/src/mainboard/asus/h110t/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/H110T/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2016 diff --git a/src/mainboard/asus/h110t/bootblock.c b/src/mainboard/asus/h110t/bootblock.c new file mode 100644 index 0000000..d3f9ef3 --- /dev/null +++ b/src/mainboard/asus/h110t/bootblock.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5539d/nct5539d.h> +#include "include/gpio.h" + +static void early_config_superio(void) +{ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT5539D_SP1); + nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} + +void bootblock_mainboard_early_init(void) +{ + early_config_superio(); +} diff --git a/src/mainboard/asus/h110t/cmos.default b/src/mainboard/asus/h110t/cmos.default new file mode 100644 index 0000000..f4dbc7e --- /dev/null +++ b/src/mainboard/asus/h110t/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +hyper_threading=Enable diff --git a/src/mainboard/asus/h110t/cmos.layout b/src/mainboard/asus/h110t/cmos.layout new file mode 100644 index 0000000..81dd48b --- /dev/null +++ b/src/mainboard/asus/h110t/cmos.layout @@ -0,0 +1,111 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +#416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +#896 32 r 0 mrc_scrambler_seed +#928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/asus/h110t/data.vbt b/src/mainboard/asus/h110t/data.vbt new file mode 100644 index 0000000..0061c69 --- /dev/null +++ b/src/mainboard/asus/h110t/data.vbt Binary files differ diff --git a/src/mainboard/asus/h110t/devicetree.cb b/src/mainboard/asus/h110t/devicetree.cb new file mode 100644 index 0000000..82f8968 --- /dev/null +++ b/src/mainboard/asus/h110t/devicetree.cb @@ -0,0 +1,196 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # FSP Configuration + register "PrimaryDisplay" = "Display_iGFX" + register "SaGv" = "SaGv_Enabled" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + subsystemid 0x1043 0x8694 inherit # Asus specific + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on # USB xHCI + # TODO get these values right + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # Thermal Subsystem + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on # SATA + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + }" + end + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1c.0 on # PCI Express Port 5 + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + end + device pci 1d.0 on # PCI Express Port 9 + register "PcieRpEnable[8]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + end + device pci 1d.1 on # PCI Express Port 10 - Realtek onboard LAN + register "PcieRpEnable[9]" = "1" + register "PcieRpAdvancedErrorReporting[9]" = "1" + register "PcieRpLtrEnable[9]" = "1" + # Disable CLKREQ#, since onboard LAN is always present + register "PcieRpClkReqSupport[9]" = "0" + end + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on # LPC bridge # TODO the superio config probably needs improvement + + # Set LPC Serial IRQ mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + chip superio/common + device pnp 2e.ff on # passes SIO base addr to SSDT gen + chip superio/nuvoton/nct5539d + device pnp 2e.1 on + irq 0x13 = 0xff + irq 0x14 = 0xff + irq 0x1a = 0x00 + irq 0x24 = 0x00 + irq 0x26 = 0x00 + irq 0x27 = 0x01 + irq 0x28 = 0x10 + irq 0x2a = 0x00 + irq 0x2c = 0x00 + irq 0x2d = 0x02 + irq 0x2f = 0x00 + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO7 + device pnp 2e.107 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO BASE + device pnp 2e.408 off end # WDTMEM + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.a on # ACPI + irq 0xe6 = 0x0a + irq 0xe7 = 0x11 + irq 0xec = 0x80 + irq 0xf2 = 0x5d + end + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + irq 0xf0 = 0x7e + end + device pnp 2e.d off end # BCLK/WDT2/WDT_MEM + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID/PORT 80 + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 off end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end # superio/nuvoton/nct5539d + end # SSDT gen + end # superio/common + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on # Intel HDA + register "PchHdaVcType" = "Vc1" + end + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/asus/h110t/dsdt.asl b/src/mainboard/asus/h110t/dsdt.asl new file mode 100644 index 0000000..32e22b3 --- /dev/null +++ b/src/mainboard/asus/h110t/dsdt.asl @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + #include <soc/intel/common/acpi/platform.asl> + #include <soc/intel/skylake/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + /* Image processing unit */ + #include <soc/intel/skylake/acpi/ipu.asl> + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + // Dynamic Platform Thermal Framework + #include "acpi/dptf.asl" + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/asus/h110t/gma-mainboard.ads b/src/mainboard/asus/h110t/gma-mainboard.ads new file mode 100644 index 0000000..7bf6d97 --- /dev/null +++ b/src/mainboard/asus/h110t/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + DP1, + LVDS, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/h110t/hda_verb.c b/src/mainboard/asus/h110t/hda_verb.c new file mode 100644 index 0000000..136c60a --- /dev/null +++ b/src/mainboard/asus/h110t/hda_verb.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek ALC887 */ + 0x10438445, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x10438445), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014020), + AZALIA_PIN_CFG(0, 0x15, 0x90170110), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214030), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4026c629), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/h110t/include/gpio.h b/src/mainboard/asus/h110t/include/gpio.h new file mode 100644 index 0000000..ee33999 --- /dev/null +++ b/src/mainboard/asus/h110t/include/gpio.h @@ -0,0 +1,637 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <gpio.h> + +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + _PAD_CFG_STRUCT(GPP_A0, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* RCIN# */ + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), + PAD_PULL(UP_20K)), /* LAD0 */ + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), + PAD_PULL(UP_20K)), /* LAD1 */ + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), + PAD_PULL(UP_20K)), /* LAD2 */ + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), + PAD_PULL(UP_20K)), /* LAD3 */ + _PAD_CFG_STRUCT(GPP_A5, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* LFRAME# */ + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), + 0), /* SERIRQ */ + _PAD_CFG_STRUCT(GPP_A7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A8, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A9, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_PULL(DN_20K)), /* CLKOUT_LPC0 */ + _PAD_CFG_STRUCT(GPP_A10, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_PULL(DN_20K)), /* CLKOUT_LPC1 */ + _PAD_CFG_STRUCT(GPP_A11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + PAD_PULL(UP_20K)), /* PME# */ + _PAD_CFG_STRUCT(GPP_A12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* SUSWARN#/SUSPWRDNACK */ + _PAD_CFG_STRUCT(GPP_A14, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A15, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_PULL(UP_20K)), /* SUS_ACK# */ + _PAD_CFG_STRUCT(GPP_A16, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A17, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A18, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A19, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPO(GPP_A20, 0, PLTRST), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A21, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A22, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, PLTRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_B ------- */ + _PAD_CFG_STRUCT(GPP_B0, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B1, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B2, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B3, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B4, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B8, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B10, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B11, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* PLTRST# */ + _PAD_CFG_STRUCT(GPP_B14, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_PULL(DN_20K)), /* SPKR */ + _PAD_CFG_STRUCT(GPP_B15, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPO(GPP_B16, 0, PLTRST), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B17, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B18, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B19, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B20, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B21, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B22, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + _PAD_CFG_STRUCT(GPP_C0, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) + | (1 << 1), + 0), /* SMBCLK */ + _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), + 0), /* SMBDATA */ + _PAD_CFG_STRUCT(GPP_C2, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C3, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) + | (1 << 1), + 0), /* SML0CLK */ + _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), + 0), /* SML0DATA */ + _PAD_CFG_STRUCT(GPP_C5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C10, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C11, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C13, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C15, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C16, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C17, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C20, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C21, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C22, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) + | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) + | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), + 0), /* GPIO */ + + /* ------- GPIO Group GPP_D ------- */ + _PAD_CFG_STRUCT(GPP_D0, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D2, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D3, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D4, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) + | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D9, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D10, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D11, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D12, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + PAD_PULL(DN_20K)), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D15, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D16, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D18, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D19, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, PLTRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_E0, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E8, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* SATA_LED# */ + _PAD_CFG_STRUCT(GPP_E9, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* USB_OC0# */ + _PAD_CFG_STRUCT(GPP_E10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* USB_OC1# */ + _PAD_CFG_STRUCT(GPP_E11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* USB_OC2# */ + _PAD_CFG_STRUCT(GPP_E12, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* USB_OC3# */ + + /* ------- GPIO Group GPP_F ------- */ + _PAD_CFG_STRUCT(GPP_F0, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F1, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + PAD_PULL(UP_20K)), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F2, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + PAD_PULL(UP_20K)), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F15, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* USB_OC4# */ + _PAD_CFG_STRUCT(GPP_F16, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F17, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F18, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F19, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* eDP_VDDEN */ + _PAD_CFG_STRUCT(GPP_F20, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* eDP_BKLTEN */ + _PAD_CFG_STRUCT(GPP_F21, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* eDP_BKLTCTL */ + PAD_CFG_GPI_TRIG_OWN(GPP_F22, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + + /* ------- GPIO Group GPP_G ------- */ + _PAD_CFG_STRUCT(GPP_G0, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G2, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G3, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G4, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G9, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G10, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G15, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G17, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G18, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G19, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G20, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G22, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H1, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) + | (1 << 1), + 0), /* SRCCLKREQ7# */ + PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H3, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H4, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H9, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H10, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H11, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H13, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H16, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H17, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H20, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H21, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + + /* ------- GPIO Community 2 ------- */ + + /* -------- GPIO Group GPD -------- */ + _PAD_CFG_STRUCT(GPD0, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD1, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), + 0), /* LAN_WAKE# */ + _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), + PAD_PULL(UP_20K)), /* PWRBTN# */ + _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* SLP_S3# */ + _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* SLP_S4# */ + _PAD_CFG_STRUCT(GPD6, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1) | 1, + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD8, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD10, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD11, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* LANPHYPC */ + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + _PAD_CFG_STRUCT(GPP_I0, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* DDPB_HPD0 */ + _PAD_CFG_STRUCT(GPP_I1, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* DDPC_HPD1 */ + _PAD_CFG_STRUCT(GPP_I2, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* DDPD_HPD2 */ + _PAD_CFG_STRUCT(GPP_I3, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* DDPE_HPD3 */ + _PAD_CFG_STRUCT(GPP_I4, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* EDP_HPD */ + _PAD_CFG_STRUCT(GPP_I5, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* DDPB_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I6, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_PULL(DN_20K)), /* DDPB_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I7, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* DDPC_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I8, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_PULL(DN_20K)), /* DDPC_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I9, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* DDPD_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I10, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + PAD_PULL(DN_20K)), /* DDPD_CTRLDATA */ +}; + +static const struct pad_config early_gpio_table[] = { + + /* ------- GPIO Group GPP_A ------- */ + _PAD_CFG_STRUCT(GPP_A0, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* RCIN# */ + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), + PAD_PULL(UP_20K)), /* LAD0 */ + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), + PAD_PULL(UP_20K)), /* LAD1 */ + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), + PAD_PULL(UP_20K)), /* LAD2 */ + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), + PAD_PULL(UP_20K)), /* LAD3 */ + _PAD_CFG_STRUCT(GPP_A5, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* LFRAME# */ + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), + 0), /* SERIRQ */ + _PAD_CFG_STRUCT(GPP_A7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A8, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A9, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_PULL(DN_20K)), /* CLKOUT_LPC0 */ + _PAD_CFG_STRUCT(GPP_A10, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_PULL(DN_20K)), /* CLKOUT_LPC1 */ + _PAD_CFG_STRUCT(GPP_A11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + PAD_PULL(UP_20K)), /* PME# */ + _PAD_CFG_STRUCT(GPP_A12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* SUSWARN#/SUSPWRDNACK */ + _PAD_CFG_STRUCT(GPP_A14, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A15, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_PULL(UP_20K)), /* SUS_ACK# */ +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/asus/h110t/mainboard.c b/src/mainboard/asus/h110t/mainboard.c new file mode 100644 index 0000000..203c5e3 --- /dev/null +++ b/src/mainboard/asus/h110t/mainboard.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <drivers/intel/i210/i210.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + +enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6]) +{ + /* TODO */ + mac[0] = 0xFF; + mac[1] = 0xFF; + mac[2] = 0xFF; + mac[3] = 0xFF; + mac[4] = 0xFF; + mac[5] = 0xFF; + return CB_SUCCESS; +} diff --git a/src/mainboard/asus/h110t/ramstage.c b/src/mainboard/asus/h110t/ramstage.c new file mode 100644 index 0000000..9d3933c --- /dev/null +++ b/src/mainboard/asus/h110t/ramstage.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> +#include "include/gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/asus/h110t/romstage.c b/src/mainboard/asus/h110t/romstage.c new file mode 100644 index 0000000..7c532e4 --- /dev/null +++ b/src/mainboard/asus/h110t/romstage.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <soc/romstage.h> +#include <stdint.h> +#include <string.h> +#include <spd_bin.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const u16 rcomp_resistors[3] = {121, 75, 100}; + + const u16 rcomp_targets[5] = {50, 26, 20, 20, 26}; + + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + + struct spd_block blk = { + .addr_map = {0x50, 0x52}, + }; + + assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets)); + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; + dump_spd_info(&blk); + + memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget)); + + /* use virtual channel 1 for the dmi interface of the PCH */ + mupd->FspmTestConfig.DmiVc1 = 1; + + /* desktop type */ + mem_cfg->UserBd = BOARD_TYPE_DESKTOP; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab30596f2a12931679687c9f56427712b65f9363 Gerrit-Change-Number: 48648 Gerrit-PatchSet: 1 Gerrit-Owner: Marvin Drees Gerrit-MessageType: newchange

6 29

Change in coreboot[master]: [WIP] device/resource_allocator_v4.5: Directly recurse in pass 2 for ...
by Nico Huber (Code Review) 22 Jun '23

22 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41959 ) Change subject: [WIP] device/resource_allocator_v4.5: Directly recurse in pass 2 for each bridge resource ...................................................................... [WIP] device/resource_allocator_v4.5: Directly recurse in pass 2 for each bridge resource Change-Id: I9b31c7242f0cdf747db48203243f0e9ba6643bf4 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/resource_allocator_v4.5.c 1 file changed, 40 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/41959/1 diff --git a/src/device/resource_allocator_v4.5.c b/src/device/resource_allocator_v4.5.c index 34e9fdd..96a6503 100644 --- a/src/device/resource_allocator_v4.5.c +++ b/src/device/resource_allocator_v4.5.c @@ -394,6 +394,43 @@ } /* + * Pass 2 of the resource allocator at the bridge level loops through + * all the resources for the bridge and assigns all the base addresses + * of its children's resources of the same type. update_bridge_resource() + * of pass 1 pre-calculated the offsets of these bases inside the bridge + * resource. Now that the bridge resource is allocated, all we have to + * do is to add its final base to these offsets. + * + * Once allocation at the current bridge is complete, resource allocator + * continues walking down the downstream bridges until it hits the leaf + * devices. + */ +static void allocate_bridge_resources(const struct device *bridge, struct resource *bridge_res) +{ + void assign_resource_cb(void *param, struct device *dev, struct resource *res) + { + /* We have to filter the same resources as update_bridge_resource(). */ + if (!res->size || !res->limit) + return; + + assign_resource(res, *(const resource_t *)param + res->base, dev); + + if (res->flags & IORESOURCE_BRIDGE) + allocate_bridge_resources(dev, res); + } + + const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; + const unsigned long type = bridge_res->flags & type_mask; + struct bus *const bus = bridge->link_list; + + if (!bus) + return; + + /* Run assign_resource_cb() for all downstream resources of the same type. */ + search_bus_resources(bus, type_mask, type, assign_resource_cb, &bridge_res->base); +} + +/* * This is where the actual allocation of resources happens during * pass 2. We construct a list of memory ranges corresponding to the * resource of a given type, then look for the biggest unallocated @@ -433,63 +470,15 @@ } assign_resource(res, base, dev); + + if (res->flags & IORESOURCE_BRIDGE) + allocate_bridge_resources(dev, res); } cleanup_resource_ranges(domain, &ranges, domain_res); } /* - * Pass 2 of the resource allocator at the bridge level loops through - * all the resources for the bridge and assigns all the base addresses - * of its children's resources of the same type. update_bridge_resource() - * of pass 1 pre-calculated the offsets of these bases inside the bridge - * resource. Now that the bridge resource is allocated, all we have to - * do is to add its final base to these offsets. - * - * Once allocation at the current bridge is complete, resource allocator - * continues walking down the downstream bridges until it hits the leaf - * devices. - */ -static void allocate_bridge_resources(const struct device *bridge) -{ - void assign_resource_cb(void *param, struct device *dev, struct resource *res) - { - /* We have to filter the same resources as update_bridge_resource(). */ - if (!res->size || !res->limit) - return; - - assign_resource(res, *(const resource_t *)param + res->base, dev); - } - - const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; - struct bus *const bus = bridge->link_list; - struct resource *res; - struct device *child; - - for (res = bridge->resource_list; res != NULL; res = res->next) { - if (!res->size) - continue; - - if (!(res->flags & IORESOURCE_BRIDGE)) - continue; - - if (!(res->flags & IORESOURCE_ASSIGNED)) - continue; - - /* Run assign_resource_cb() for all downstream resources of the same type. */ - search_bus_resources(bus, type_mask, res->flags & type_mask, - assign_resource_cb, &res->base); - } - - for (child = bus->children; child != NULL; child = child->sibling) { - if (!dev_has_children(child)) - continue; - - allocate_bridge_resources(child); - } -} - -/* * Pass 2 of resource allocator begins at the domain level. Every domain * has two types of resources - io and mem. For each of these resources, * this function creates a list of memory ranges that can be used for @@ -504,8 +493,6 @@ */ static void allocate_domain_resources(const struct device *domain) { - struct device *child; - /* Resource type I/O */ allocate_toplevel_resources(domain, IORESOURCE_IO); @@ -516,14 +503,6 @@ * on the biggest resource requirement. */ allocate_toplevel_resources(domain, IORESOURCE_MEM); - - for (child = domain->link_list->children; child; child = child->sibling) { - if (!dev_has_children(child)) - continue; - - /* Continue allocation for all downstream bridges. */ - allocate_bridge_resources(child); - } } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/41959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b31c7242f0cdf747db48203243f0e9ba6643bf4 Gerrit-Change-Number: 41959 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: device: Introduce RESOURCE_ALLOCATION_COMPAT
by Nico Huber (Code Review) 22 Jun '23

22 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41958 ) Change subject: device: Introduce RESOURCE_ALLOCATION_COMPAT ...................................................................... device: Introduce RESOURCE_ALLOCATION_COMPAT Add a v3-compatibility mode to the v4.5 allocator. We avoid all space above 4G and then disable all remaining memranges but the biggest. It also forces top-down allocation. Change-Id: I1c8512e4b6264f1967cf7018debdf9cabf11d84f Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/Kconfig M src/device/resource_allocator_v4.5.c 2 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/41958/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index 35433b0..50e3857 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -825,4 +825,9 @@ bool "Allocate resources from top down" depends on RESOURCE_ALLOCATOR_V4 || RESOURCE_ALLOCATOR_V4_5 +config RESOURCE_ALLOCATION_COMPAT + bool "Resource allocator v3 compatibility mode" + depends on RESOURCE_ALLOCATOR_V4_5 + select RESOURCE_ALLOCATION_TOP_DOWN + endmenu diff --git a/src/device/resource_allocator_v4.5.c b/src/device/resource_allocator_v4.5.c index 4a03a23..34e9fdd 100644 --- a/src/device/resource_allocator_v4.5.c +++ b/src/device/resource_allocator_v4.5.c @@ -350,6 +350,28 @@ avoid_fixed_resources(ranges, domain, mask_match); + if (CONFIG(RESOURCE_ALLOCATION_COMPAT)) { + struct range_entry *r, *biggest = NULL; + + /* Don't allow allocations above 4G. */ + memranges_create_hole(ranges, POWER_OF_2(32), UINT64_MAX - POWER_OF_2(32) + 1); + + /* Set all but the biggest range's tag to 0. */ + memranges_each_entry(r, ranges) { + if (!biggest) { + biggest = r; + continue; + } + + if (range_entry_size(r) > range_entry_size(biggest)) { + range_entry_update_tag(biggest, 0); + biggest = r; + } else { + range_entry_update_tag(r, 0); + } + } + } + print_resource_ranges(domain, ranges); } -- To view, visit https://review.coreboot.org/c/coreboot/+/41958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c8512e4b6264f1967cf7018debdf9cabf11d84f Gerrit-Change-Number: 41958 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: device: Introduce v4.5 resource allocator
by Nico Huber (Code Review) 22 Jun '23

22 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41956 ) Change subject: device: Introduce v4.5 resource allocator ...................................................................... device: Introduce v4.5 resource allocator This is not a complete rewrite, more an adaptation of the v4 allocator. For the moment, I suggest this for experiments, until we have a better understanding what we require from the resource allocator. It differs mostly in pass 2. Instead of searching memranges for every bridge, we only do that for the top level and finish the calculations of pass 1 at the bridge level. And we don't handle above-4G resources separately. This implies that we need a top-down allocation at the top level to place things above 4G, which will be added in a later commit. Detailed list of functional differences --------------------------------------- Pass 1: * Completely ignore resources with 0 limit. * Don't propagate above-4G flag. Propagation makes it harder to effectively opt-out from 4G, e.g. for boot graphics / network devices. OTOH, this way resources can only be placed above 4G if all resources downstream of a bridge allow it. * Store the calculated `base` offset in the resources (like v3 did). This allows us to skip the largest_resource() walk at the bridge level in pass 2. Pass 2: * No separate handling for above-4G resources. They'll need a top-down mode. * No memranges at the bridge-level. Instead we simply add the offset that was pre-calculated in pass 1 to the allocated `base` of the bridge resource. This lowers the computational complexity of pass 2. But there's likely no measurable impact for our usual, shallow device trees. Beside that, there is some heavy refactoring: All the resource printing is factored out into separate functions. This results in one-liners in the actual program code which hopefully will distract less during reading. Some thin functions are manually inlined where it seems to improve readability, and comments are adapted and re-flown to 72 columns (counting from indentation level). TEST=None, so far. Change-Id: I1c27e89916e6e915d4dfe5435fac53fef768bf37 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/Kconfig M src/device/Makefile.inc A src/device/resource_allocator_v4.5.c M src/northbridge/amd/agesa/family14/Kconfig M src/northbridge/amd/agesa/family15tn/Kconfig M src/northbridge/amd/agesa/family16kb/Kconfig M src/northbridge/amd/pi/00630F01/Kconfig M src/northbridge/amd/pi/00660F01/Kconfig M src/northbridge/amd/pi/00730F01/Kconfig 9 files changed, 599 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/41956/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index 79ce77d..ee6fb21 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -793,9 +793,16 @@ I2C controller is not (yet) available. The platform code needs to provide bindings to manually toggle I2C lines. -config RESOURCE_ALLOCATOR_V3 +config DEFAULT_RESOURCE_ALLOCATOR_V3 bool - default n + +choice + prompt "Resource allocator" + default RESOURCE_ALLOCATOR_V3 if DEFAULT_RESOURCE_ALLOCATOR_V3 + default RESOURCE_ALLOCATOR_V4 + +config RESOURCE_ALLOCATOR_V3 + bool "v3 (deprecated)" help This config option enables resource allocator v3 which performs top down allocation of resources in a single MMIO window. This is the @@ -803,12 +810,15 @@ chipsets are fixed. DO NOT USE THIS FOR ANY NEW CHIPSETS! config RESOURCE_ALLOCATOR_V4 - bool - default n if RESOURCE_ALLOCATOR_V3 - default y if !RESOURCE_ALLOCATOR_V3 + bool "v4" help This config option enables resource allocator v4 which uses multiple ranges for allocating resources. This allows allocation of resources above 4G boundary as well. +config RESOURCE_ALLOCATOR_V4_5 + bool "v4.5 (experimental)" + +endchoice + endmenu diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 2e62d42..1a31c3c 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -62,3 +62,4 @@ ramstage-y += resource_allocator_common.c ramstage-$(CONFIG_RESOURCE_ALLOCATOR_V3) += resource_allocator_v3.c ramstage-$(CONFIG_RESOURCE_ALLOCATOR_V4) += resource_allocator_v4.c +ramstage-$(CONFIG_RESOURCE_ALLOCATOR_V4_5) += resource_allocator_v4.5.c diff --git a/src/device/resource_allocator_v4.5.c b/src/device/resource_allocator_v4.5.c new file mode 100644 index 0000000..6b9e712 --- /dev/null +++ b/src/device/resource_allocator_v4.5.c @@ -0,0 +1,577 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <device/device.h> +#include <memrange.h> +#include <post.h> + +static const char *resource2str(const struct resource *res) +{ + if (res->flags & IORESOURCE_IO) + return "io"; + if (res->flags & IORESOURCE_PREFETCH) + return "prefmem"; + if (res->flags & IORESOURCE_MEM) + return "mem"; + return "undefined"; +} + +static void print_domain_res(const struct device *dev, + const struct resource *res, const char *suffix) +{ + printk(BIOS_DEBUG, "%s %s: base: %llx size: %llx align: %d gran: %d limit: %llx%s\n", + dev_path(dev), resource2str(res), res->base, res->size, + res->align, res->gran, res->limit, suffix); +} + +#define res_printk(depth, str, ...) printk(BIOS_DEBUG, "%*c"str, depth, ' ', __VA_ARGS__) + +static void print_bridge_res(const struct device *dev, const struct resource *res, + int depth, const char *suffix) +{ + res_printk(depth, "%s %s: size: %llx align: %d gran: %d limit: %llx%s\n", dev_path(dev), + resource2str(res), res->size, res->align, res->gran, res->limit, suffix); +} + +static void print_child_res(const struct device *dev, const struct resource *res, int depth) +{ + res_printk(depth + 1, "%s %02lx * [0x%llx - 0x%llx] %s\n", dev_path(dev), + res->index, res->base, res->base + res->size - 1, resource2str(res)); +} + +static void print_fixed_res(const struct device *dev, + const struct resource *res, const char *prefix) +{ + printk(BIOS_DEBUG, " %s: %s %02lx base %08llx limit %08llx %s (fixed)\n", + prefix, dev_path(dev), res->index, res->base, res->base + res->size - 1, + resource2str(res)); +} + +static void print_assigned_res(const struct device *dev, const struct resource *res) +{ + printk(BIOS_DEBUG, " %s %02lx * [0x%llx - 0x%llx] limit: %llx %s\n", + dev_path(dev), res->index, res->base, res->limit, res->limit, resource2str(res)); +} + +static void print_failed_res(const struct device *dev, const struct resource *res) +{ + printk(BIOS_DEBUG, " %s %02lx * size: 0x%llx limit: %llx %s\n", + dev_path(dev), res->index, res->size, res->limit, resource2str(res)); +} + +static void print_resource_ranges(const struct device *dev, const struct memranges *ranges) +{ + const struct range_entry *r; + + printk(BIOS_INFO, " %s: Resource ranges:\n", dev_path(dev)); + + if (memranges_is_empty(ranges)) + printk(BIOS_INFO, " * EMPTY!!\n"); + + memranges_each_entry(r, ranges) { + printk(BIOS_INFO, " * Base: %llx, Size: %llx, Tag: %lx\n", + range_entry_base(r), range_entry_size(r), range_entry_tag(r)); + } +} + +static bool dev_has_children(const struct device *dev) +{ + const struct bus *bus = dev->link_list; + return bus && bus->children; +} + +static resource_t effective_limit(const struct resource *const res) +{ + /* Always allow bridge resources above 4G. */ + if (res->flags & IORESOURCE_BRIDGE) + return res->limit; + + const resource_t quirk_4g_limit = + res->flags & IORESOURCE_ABOVE_4G ? UINT64_MAX : UINT32_MAX; + return MIN(res->limit, quirk_4g_limit); +} + +/* + * During pass 1, once all the requirements for downstream devices of a + * bridge are gathered, this function calculates the overall resource + * requirement for the bridge. It starts by picking the largest resource + * requirement downstream for the given resource type and works by + * adding requirements in descending order. + * + * Additionally, it takes alignment and limits of the downstream devices + * into consideration and ensures that they get propagated to the bridge + * resource. This is required to guarantee that the upstream bridge/ + * domain honors the limit and alignment requirements for this bridge + * based on the tightest constraints downstream. + * + * Last but not least, it stores the offset inside the bridge resource + * for each child resource in its base field. This simplifies pass 2 + * for resources behind a bridge, as we only have to add offsets to the + * allocated base of the bridge resource. + */ +static void update_bridge_resource(const struct device *bridge, struct resource *bridge_res, + unsigned long type_match, int print_depth) +{ + const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; + struct bus *bus = bridge->link_list; + const struct device *child; + struct resource *child_res; + resource_t base; + + /* + * `base` keeps track of where the next allocation for child resources + * can take place from within the bridge resource window. Since the + * bridge resource window allocation is not performed yet, we start + * at 0. Base gets updated every time a resource requirement is + * accounted for in the loop below. After scanning all these resources, + * base will indicate the total size requirement for the current bridge + * resource window. + */ + base = 0; + + print_bridge_res(bridge, bridge_res, print_depth, ""); + + child_res = NULL; + while ((child = largest_resource(bus, &child_res, type_mask, type_match))) { + + /* Size 0 resources can be skipped. */ + if (!child_res->size) + continue; + + /* Resources with 0 limit can't be assigned anything. */ + if (!child_res->limit) + continue; + + /* + * Propagate the resource alignment to the bridge resource. The + * condition can only be true for the first (largest) resource. For all + * other child resources, alignment is taken care of by rounding base up. + */ + if (child_res->align > bridge_res->align) + bridge_res->align = child_res->align; + + /* + * Propagate the resource limit to the bridge resource. If a downstream + * device has stricter requirements w.r.t. limits for any resource, that + * constraint needs to be propagated back up to the downstream bridges of + * the domain. This way, the whole bridge resource fulfills the limit. + */ + if (effective_limit(child_res) < bridge_res->limit) + bridge_res->limit = effective_limit(child_res); + + /* + * Alignment value of 0 means that the child resource has no alignment + * requirements and so the base value remains unchanged here. + */ + base = ALIGN_UP(base, POWER_OF_2(child_res->align)); + + /* + * Store the relative offset inside the bridge resource for later + * consumption in allocate_child_resources(). + */ + child_res->base = base; + + print_child_res(child, child_res, print_depth); + + base += child_res->size; + } + + /* + * After all downstream device resources are scanned, `base` represents + * the total size requirement for the current bridge resource window. + * This size needs to be rounded up to the granularity requirement of + * the bridge to ensure that the upstream bridge/domain allocates big + * enough window. + */ + bridge_res->size = ALIGN_UP(base, POWER_OF_2(bridge_res->gran)); + + print_bridge_res(bridge, bridge_res, print_depth, " done"); +} + +/* + * During pass 1, at the bridge level, the resource allocator gathers + * requirements from downstream devices and updates its own resource + * windows for the provided resource type. + */ +static void compute_bridge_resources(const struct device *bridge, unsigned long type_match, + int print_depth) +{ + const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; + const struct bus *const bus = bridge->link_list; + const struct device *child; + struct resource *res; + + for (res = bridge->resource_list; res != NULL; res = res->next) { + if (!(res->flags & IORESOURCE_BRIDGE)) + continue; + + if ((res->flags & type_mask) != type_match) + continue; + + /* + * Ensure that the resource requirements for all downstream bridges are + * gathered before updating the window for current bridge resource. + */ + for (child = bus->children; child != NULL; child = child->sibling) { + if (!dev_has_children(child)) + continue; + compute_bridge_resources(child, type_match, print_depth + 1); + } + + /* + * Update the window for current bridge resource now that all downstream + * requirements are gathered. + */ + update_bridge_resource(bridge, res, type_match, print_depth); + } +} + +/* + * During pass 1, the resource allocator walks down the entire sub-tree + * of a domain. It gathers resource requirements for every downstream + * bridge by looking at the resource requests of its children. Thus, the + * requirement gathering begins at the leaf devices and is propagated + * back up to the downstream bridges of the domain. + * + * At the domain level, it identifies every downstream bridge and walks + * down that bridge to gather requirements for each resource type i.e. + * i/o, mem and prefmem. Since bridges have separate windows for mem and + * prefmem, requirements for each need to be collected separately. + * + * Domain resource windows are fixed ranges and hence requirement + * gathering does not result in any changes to these fixed ranges. + */ +static void compute_domain_resources(const struct device *domain) +{ + const struct device *child; + const int print_depth = 1; + + if (domain->link_list == NULL) + return; + + for (child = domain->link_list->children; child != NULL; child = child->sibling) { + /* Skip if this is not a bridge or has no children under it. */ + if (!dev_has_children(child)) + continue; + + compute_bridge_resources(child, IORESOURCE_IO, print_depth); + compute_bridge_resources(child, IORESOURCE_MEM, print_depth); + compute_bridge_resources(child, IORESOURCE_MEM | IORESOURCE_PREFETCH, + print_depth); + } +} + +static const struct resource *find_domain_resource(const struct device *domain, + unsigned long type) +{ + const struct resource *res; + + for (res = domain->resource_list; res != NULL; res = res->next) { + if (res->flags & IORESOURCE_FIXED) + continue; + + if ((res->flags & IORESOURCE_TYPE_MASK) == type) + return res; + } + + return NULL; +} + +/* + * Scan the entire tree to identify any fixed resources allocated by + * any device to ensure that the address map for domain resources are + * appropriately updated. + * + * Domains can typically provide a memrange for entire address space. + * So, this function punches holes in the address space for all fixed + * resources that are already defined. Both I/O and normal memory + * resources are added as fixed. Both need to be removed from address + * space where dynamic resource allocations are sourced. + */ +static void avoid_fixed_resources(struct memranges *ranges, const struct device *dev, + unsigned long mask_match) +{ + const struct resource *res; + const struct device *child; + + for (res = dev->resource_list; res != NULL; res = res->next) { + if ((res->flags & mask_match) != mask_match) + continue; + if (!res->size) + continue; + print_fixed_res(dev, res, __func__); + memranges_create_hole(ranges, res->base, res->size); + } + + if (!dev->link_list) + return; + + for (child = dev->link_list->children; child != NULL; child = child->sibling) + avoid_fixed_resources(ranges, child, mask_match); +} + +/* + * This function creates a list of memranges of given type using the + * resource that is provided. It applies additional constraints to + * ensure that the memranges do not overlap any of the fixed resources + * under the domain. The domain typically provides a memrange for the + * entire address space. Thus, it is up to the chipset to add DRAM and + * all other windows which cannot be used for resource allocation as + * fixed resources. + */ +static void setup_resource_ranges(const struct device *const domain, + const struct resource *const res, + const unsigned long type, + struct memranges *const ranges) +{ + const unsigned char alignment = type == IORESOURCE_MEM ? 12 : 0; + const unsigned long mask_match = type | IORESOURCE_FIXED; + + print_domain_res(domain, res, ""); + + memranges_init_empty_with_alignment(ranges, NULL, 0, alignment); + memranges_insert(ranges, res->base, res->limit - res->base + 1, type); + + if (type == IORESOURCE_IO) { + /* + * Don't allow allocations in the VGA I/O range. PCI has special + * cases for that. + */ + memranges_create_hole(ranges, 0x3b0, 0x30); + + /* + * Resource allocator no longer supports the legacy behavior where + * I/O resource allocation is guaranteed to avoid aliases over legacy + * PCI expansion card addresses. + */ + } + + avoid_fixed_resources(ranges, domain, mask_match); + + print_resource_ranges(domain, ranges); +} + +static void cleanup_resource_ranges(const struct device *dev, struct memranges *ranges, + const struct resource *res) +{ + memranges_teardown(ranges); + print_domain_res(dev, res, " done"); +} + +static void assign_resource(struct resource *const res, const resource_t base, + const struct device *const dev) +{ + res->base = base; + res->limit = res->base + res->size - 1; + res->flags |= IORESOURCE_ASSIGNED; + res->flags &= ~IORESOURCE_STORED; + + print_assigned_res(dev, res); +} + +/* + * This is where the actual allocation of resources happens during + * pass 2. We construct a list of memory ranges corresponding to the + * resource of a given type, then look for the biggest unallocated + * resource on the downstream bus. This continues in a descending order + * until all resources of a given type have space allocated within the + * domain's resource window. + */ +static void allocate_toplevel_resources(const struct device *const domain, + const unsigned long type) +{ + const unsigned long type_mask = IORESOURCE_TYPE_MASK; + const struct device *dev; + struct memranges ranges; + struct resource *res; + resource_t base; + + if (!dev_has_children(domain)) + return; + + const struct resource *const domain_res = find_domain_resource(domain, type); + if (!domain_res) + return; + + setup_resource_ranges(domain, domain_res, type, &ranges); + + res = NULL; + while ((dev = largest_resource(domain->link_list, &res, type_mask, type))) { + + if (!res->size) + continue; + + if (!memranges_steal(&ranges, res->limit, res->size, res->align, type, &base)) { + printk(BIOS_ERR, "ERROR: Resource didn't fit!!!\n"); + print_failed_res(dev, res); + continue; + } + + assign_resource(res, base, dev); + } + + cleanup_resource_ranges(domain, &ranges, domain_res); +} + +/* + * Pass 2 of the resource allocator at the bridge level loops through + * all the resources for the bridge and assigns all the base addresses + * of its children's resources of the same type. update_bridge_resource() + * of pass 1 pre-calculated the offsets of these bases inside the bridge + * resource. Now that the bridge resource is allocated, all we have to + * do is to add its final base to these offsets. + * + * Once allocation at the current bridge is complete, resource allocator + * continues walking down the downstream bridges until it hits the leaf + * devices. + */ +static void allocate_bridge_resources(const struct device *bridge) +{ + void assign_resource_cb(void *param, struct device *dev, struct resource *res) + { + /* We have to filter the same resources as update_bridge_resource(). */ + if (!res->size || !res->limit) + return; + + assign_resource(res, *(const resource_t *)param + res->base, dev); + } + + const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; + struct bus *const bus = bridge->link_list; + struct resource *res; + struct device *child; + + for (res = bridge->resource_list; res != NULL; res = res->next) { + if (!res->size) + continue; + + if (!(res->flags & IORESOURCE_BRIDGE)) + continue; + + if (!(res->flags & IORESOURCE_ASSIGNED)) + continue; + + /* Run assign_resource_cb() for all downstream resources of the same type. */ + search_bus_resources(bus, type_mask, res->flags & type_mask, + assign_resource_cb, &res->base); + } + + for (child = bus->children; child != NULL; child = child->sibling) { + if (!dev_has_children(child)) + continue; + + allocate_bridge_resources(child); + } +} + +/* + * Pass 2 of resource allocator begins at the domain level. Every domain + * has two types of resources - io and mem. For each of these resources, + * this function creates a list of memory ranges that can be used for + * downstream resource allocation. This list is constrained to remove + * any fixed resources in the domain sub-tree of the given resource + * type. It then uses the memory ranges to apply best fit on the + * resource requirements of the downstream devices. + * + * Once resources are allocated to all downstream devices of the domain, + * it walks down each downstream bridge to finish resource assignment + * of its children resources within its own window. + */ +static void allocate_domain_resources(const struct device *domain) +{ + struct device *child; + + /* Resource type I/O */ + allocate_toplevel_resources(domain, IORESOURCE_IO); + + /* + * Resource type Mem: Domain does not distinguish between mem and + * prefmem resources. Thus, the resource allocation at domain level + * considers mem and prefmem together when finding the best fit based + * on the biggest resource requirement. + */ + allocate_toplevel_resources(domain, IORESOURCE_MEM); + + for (child = domain->link_list->children; child; child = child->sibling) { + if (!dev_has_children(child)) + continue; + + /* Continue allocation for all downstream bridges. */ + allocate_bridge_resources(child); + } +} + +/* + * This function forms the guts of the resource allocator. It walks + * through the entire device tree for each domain two times. + * + * Every domain has a fixed set of ranges. These ranges cannot be + * relaxed based on the requirements of the downstream devices. They + * represent the available windows from which resources can be allocated + * to the different devices under the domain. + * + * In order to identify the requirements of downstream devices, resource + * allocator walks in a DFS fashion. It gathers the requirements from + * leaf devices and propagates those back up to their upstream bridges + * until the requirements for all the downstream devices of the domain + * are gathered. This is referred to as pass 1 of the resource allocator. + * + * Once the requirements for all the devices under the domain are + * gathered, the resource allocator walks a second time to allocate + * resources to downstream devices as per the requirements. It always + * picks the biggest resource request as per the type (i/o and mem) to + * allocate space from its fixed window to the immediate downstream + * device of the domain. In order to accomplish best fit for the + * resources, a list of ranges is maintained by each resource type (i/o + * and mem). At the domain level we don't differentiate between mem and + * prefmem. Since they are allocated space from the same window, the + * resource allocator at the domain level ensures that the biggest + * requirement is selected indepedent of the prefetch type. Once the + * resource allocation for all immediate downstream devices is complete + * at the domain level, the resource allocator walks down the subtree + * for each downstream bridge to continue the allocation process at the + * bridge level. Since bridges have either their whole window allocated + * or nothing, we only need to place downstream resources inside these + * windows by re-using offset that were pre-calculated in pass 1. This + * continues until resource allocation is realized for all downstream + * bridges in the domain sub-tree. This is referred to as pass 2 of the + * resource allocator. + * + * Some rules that are followed by the resource allocator: + * - Allocate resource locations for every device as long as + * the requirements can be satisfied. + * - Don't overlap with resources in fixed locations. + * - Don't overlap and follow the rules of bridges -- downstream + * devices of bridges should use parts of the address space + * allocated to the bridge. + */ +void allocate_resources(const struct device *root) +{ + const struct device *child; + + if ((root == NULL) || (root->link_list == NULL)) + return; + + for (child = root->link_list->children; child; child = child->sibling) { + + if (child->path.type != DEVICE_PATH_DOMAIN) + continue; + + post_log_path(child); + + /* Pass 1 - Gather requirements. */ + printk(BIOS_INFO, "==== Resource allocator: %s - Pass 1 (gathering requirements) ===\n", + dev_path(child)); + compute_domain_resources(child); + + /* Pass 2 - Allocate resources as per gathered requirements. */ + printk(BIOS_INFO, "=== Resource allocator: %s - Pass 2 (allocating resources) ===\n", + dev_path(child)); + allocate_domain_resources(child); + + printk(BIOS_INFO, "=== Resource allocator: %s - resource allocation complete ===\n", + dev_path(child)); + } +} diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig index edd7dcb..80c7a45 100644 --- a/src/northbridge/amd/agesa/family14/Kconfig +++ b/src/northbridge/amd/agesa/family14/Kconfig @@ -2,7 +2,7 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY14 bool - select RESOURCE_ALLOCATOR_V3 + select DEFAULT_RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_AGESA_FAMILY14 diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig index 8f012d5..d1af645 100644 --- a/src/northbridge/amd/agesa/family15tn/Kconfig +++ b/src/northbridge/amd/agesa/family15tn/Kconfig @@ -2,7 +2,7 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN bool - select RESOURCE_ALLOCATOR_V3 + select DEFAULT_RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_AGESA_FAMILY15_TN diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig index 4488f8d..d7bc660 100644 --- a/src/northbridge/amd/agesa/family16kb/Kconfig +++ b/src/northbridge/amd/agesa/family16kb/Kconfig @@ -2,7 +2,7 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY16_KB bool - select RESOURCE_ALLOCATOR_V3 + select DEFAULT_RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_AGESA_FAMILY16_KB diff --git a/src/northbridge/amd/pi/00630F01/Kconfig b/src/northbridge/amd/pi/00630F01/Kconfig index 292492e..a3a7cd2 100644 --- a/src/northbridge/amd/pi/00630F01/Kconfig +++ b/src/northbridge/amd/pi/00630F01/Kconfig @@ -2,7 +2,7 @@ config NORTHBRIDGE_AMD_PI_00630F01 bool - select RESOURCE_ALLOCATOR_V3 + select DEFAULT_RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_PI_00630F01 diff --git a/src/northbridge/amd/pi/00660F01/Kconfig b/src/northbridge/amd/pi/00660F01/Kconfig index e42ba80..d99a0f5 100644 --- a/src/northbridge/amd/pi/00660F01/Kconfig +++ b/src/northbridge/amd/pi/00660F01/Kconfig @@ -2,7 +2,7 @@ config NORTHBRIDGE_AMD_PI_00660F01 bool - select RESOURCE_ALLOCATOR_V3 + select DEFAULT_RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_PI_00660F01 diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index cb65506..b936543 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -2,7 +2,7 @@ config NORTHBRIDGE_AMD_PI_00730F01 bool - select RESOURCE_ALLOCATOR_V3 + select DEFAULT_RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_PI_00730F01 -- To view, visit https://review.coreboot.org/c/coreboot/+/41956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c27e89916e6e915d4dfe5435fac53fef768bf37 Gerrit-Change-Number: 41956 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: device/pci: Add early PCI dump
by Kyösti Mälkki (Code Review) 16 Jun '23

16 Jun '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48828 ) Change subject: device/pci: Add early PCI dump ...................................................................... device/pci: Add early PCI dump Change-Id: Ic095213ab51a3c29af462782fdb75cfcd409714f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/Makefile.inc A src/device/pci_dump.c M src/include/device/pci.h 3 files changed, 117 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48828/1 diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index bb125af..85c1324 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -35,6 +35,9 @@ ramstage-y += pci_ops.c smm-y += pci_ops.c +romstage-y += pci_dump.c +ramstage-y += pci_dump.c + ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c diff --git a/src/device/pci_dump.c b/src/device/pci_dump.c new file mode 100644 index 0000000..737b782 --- /dev/null +++ b/src/device/pci_dump.c @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <console/console.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> + +/* Output is in format of lspci -nxxxx so that lspci -F can parse it. */ +static int pci_s_dump_and_probe(pci_devfn_t bdf, uint8_t *last_bus) +{ + /* FIXME: Should use some macros here. */ + uint8_t bus = (bdf >> 20) & 0xff; + uint8_t dev = (bdf >> 15) & 0x1f; + uint8_t fn = (bdf >> 12) & 0x7; + + int i, j; + int ret = 0; + + uint32_t didvid, classrev; + uint8_t htype; + union { + uint8_t r8[16]; + uint16_t r16[8]; + uint32_t r32[4]; + } cfgdump; + + didvid = pci_s_read_config32(bdf, PCI_VENDOR_ID); + if (didvid == (uint32_t)-1ull) + return (fn == 0) ? -1 : 0; + + htype = pci_s_read_config8(bdf, PCI_HEADER_TYPE); + if ((fn == 0) && !(htype & 0x80)) + ret = -1; + htype &= ~0x80; + + classrev = pci_s_read_config32(bdf, PCI_CLASS_REVISION); + printk(BIOS_DEBUG, "%02x:%02x.%x %04x: (%04x:%04x) (rev %02x)\n", + bus, dev, fn, classrev >> 16, + didvid & 0xffff, didvid >> 16, classrev & 0xff); + + int max_reg = CONFIG(MMCONF_SUPPORT) ? 4096 : 256; + for (i = 0; i < max_reg / 16; i++) { + int non_zero = 0; + for (j = 0; j < 16; j += sizeof(uint32_t)) { + cfgdump.r32[j / sizeof(uint32_t)] = pci_s_read_config32(bdf, 16 * i + j); + if (cfgdump.r32[j / sizeof(uint32_t)]) + non_zero++; + } + + /* Standard 64 header is always printed, other lines only + if they are not all zeroes. */ + if ((i < 4) || non_zero) { + printk(BIOS_DEBUG, "%02x:", 16 * i); + for (j = 0; j < 16; j++) + printk(BIOS_DEBUG, " %02x", cfgdump.r8[j]); + printk(BIOS_DEBUG, "\n"); + } + } + printk(BIOS_DEBUG, "\n"); + + if (htype == PCI_HEADER_TYPE_BRIDGE) { + uint8_t bsec = pci_s_read_config8(bdf, PCI_SECONDARY_BUS); + uint8_t bsub = pci_s_read_config8(bdf, PCI_SUBORDINATE_BUS); + if ((bsub >= bsec) && (bsub > *last_bus)) + *last_bus = bsub; + } + return ret; +} + +void pci_s_dump_one(pci_devfn_t bdf) +{ + uint8_t dummy_pci_bus; + + printk(BIOS_DEBUG, "** PCI_DUMP START **\n"); + pci_s_dump_and_probe(bdf, &dummy_pci_bus); + printk(BIOS_DEBUG, "** PCI_DUMP END **\n"); +} + +void pci_dump_one(struct device *dev) +{ + pci_s_dump_one(PCI_BDF(dev)); +} + +void pci_dump_all(void) +{ + uint8_t bus, dev, fn; + uint8_t last_pci_bus = 0; + pci_devfn_t bdf; + + printk(BIOS_DEBUG, "** PCI_DUMP START **\n"); + for (bus = 0; bus <= last_pci_bus; bus++) { + for (dev = 0; dev <= 31; dev++) { + for (fn = 0; fn <= 7; fn++) { + bdf = PCI_DEV(bus, dev, fn); + if (pci_s_dump_and_probe(bdf, &last_pci_bus) < 0) + fn = 7; + } + } + } + printk(BIOS_DEBUG, "** PCI_DUMP END **\n"); +} + +void pci_dump_final(struct device *unused) +{ + pci_dump_all(); +} diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 045eec1..3df64d4 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -106,6 +106,11 @@ int pci_msix_table_bar(struct device *dev, u32 *offset, u8 *idx); struct msix_entry *pci_msix_get_table(struct device *dev); +void pci_s_dump_one(pci_devfn_t bdf); +void pci_dump_one(struct device *dev); +void pci_dump_all(void); +void pci_dump_final(struct device *dev); + #define PCI_IO_BRIDGE_ALIGN 4096 #define PCI_MEM_BRIDGE_ALIGN (1024*1024) -- To view, visit https://review.coreboot.org/c/coreboot/+/48828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic095213ab51a3c29af462782fdb75cfcd409714f Gerrit-Change-Number: 48828 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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