coreboot-gerrit April 2021

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Change in coreboot[master]: [RFC] Move SYSTEM_TYPE_xxx to devicetree.cb
by Kyösti Mälkki (Code Review) 15 Jun '23

15 Jun '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42142 ) Change subject: [RFC] Move SYSTEM_TYPE_xxx to devicetree.cb ...................................................................... [RFC] Move SYSTEM_TYPE_xxx to devicetree.cb This makes the entire range of SMBIOS_ENCLOSURE_xx enums usable. Change-Id: Ib546706d04fede6c14ac57280ae72dca4fb7085b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/Kconfig M src/arch/x86/smbios.c M src/mainboard/51nb/x210/Kconfig M src/mainboard/apple/macbook21/Kconfig M src/mainboard/apple/macbookair4_2/Kconfig M src/mainboard/compulab/intense_pc/Kconfig M src/mainboard/getac/p470/Kconfig M src/mainboard/google/auron/Kconfig M src/mainboard/google/butterfly/Kconfig M src/mainboard/google/cyan/Kconfig M src/mainboard/google/dedede/Kconfig M src/mainboard/google/deltaur/Kconfig M src/mainboard/google/drallion/Kconfig M src/mainboard/google/eve/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/google/hatch/Kconfig M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/link/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/google/parrot/Kconfig M src/mainboard/google/poppy/Kconfig M src/mainboard/google/rambi/Kconfig M src/mainboard/google/reef/Kconfig M src/mainboard/google/sarien/Kconfig M src/mainboard/google/slippy/Kconfig M src/mainboard/google/stout/Kconfig M src/mainboard/google/veyron/Kconfig.name M src/mainboard/google/zork/Kconfig M src/mainboard/hp/pavilion_m6_1035dx/Kconfig M src/mainboard/hp/snb_ivb_laptops/Kconfig M src/mainboard/intel/glkrvp/Kconfig M src/mainboard/lenovo/g505s/Kconfig M src/mainboard/lenovo/l520/Kconfig M src/mainboard/lenovo/s230u/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t410/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t440p/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/t60/Kconfig M src/mainboard/lenovo/x131e/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x230/Kconfig M src/mainboard/lenovo/x60/Kconfig M src/mainboard/packardbell/ms2290/Kconfig M src/mainboard/purism/librem_bdw/Kconfig M src/mainboard/purism/librem_skl/Kconfig M src/mainboard/razer/blade_stealth_kbl/Kconfig M src/mainboard/roda/rk886ex/Kconfig M src/mainboard/roda/rk9/Kconfig M src/mainboard/roda/rv11/Kconfig M src/mainboard/samsung/lumpy/Kconfig M src/mainboard/system76/lemp9/Kconfig 60 files changed, 1 insertion(+), 90 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/42142/1 diff --git a/src/Kconfig b/src/Kconfig index 63ecd0a..b38923d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -443,22 +443,6 @@ # load site-local kconfig to allow user specific defaults and overrides source "site-local/Kconfig" -config SYSTEM_TYPE_LAPTOP - default n - bool - -config SYSTEM_TYPE_TABLET - default n - bool - -config SYSTEM_TYPE_DETACHABLE - default n - bool - -config SYSTEM_TYPE_CONVERTIBLE - default n - bool - config CBFS_AUTOGEN_ATTRIBUTES default n bool diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index ee69408..12e7be3 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -487,16 +487,7 @@ */ smbios_enclosure_type __weak smbios_mainboard_enclosure_type(void) { - if (CONFIG(SYSTEM_TYPE_LAPTOP)) - return SMBIOS_ENCLOSURE_LAPTOP; - else if (CONFIG(SYSTEM_TYPE_TABLET)) - return SMBIOS_ENCLOSURE_TABLET; - else if (CONFIG(SYSTEM_TYPE_CONVERTIBLE)) - return SMBIOS_ENCLOSURE_CONVERTIBLE; - else if (CONFIG(SYSTEM_TYPE_DETACHABLE)) - return SMBIOS_ENCLOSURE_DETACHABLE; - else - return SMBIOS_ENCLOSURE_DESKTOP; + return SMBIOS_ENCLOSURE_UNKNOWN; } const char *__weak smbios_system_serial_number(void) diff --git a/src/mainboard/51nb/x210/Kconfig b/src/mainboard/51nb/x210/Kconfig index 44c0f862..45c5755 100644 --- a/src/mainboard/51nb/x210/Kconfig +++ b/src/mainboard/51nb/x210/Kconfig @@ -10,7 +10,6 @@ select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_KABYLAKE select SPD_READ_BY_WORD - select SYSTEM_TYPE_LAPTOP config MAINBOARD_FAMILY string diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index 9eb06ff..0bff36e 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_M select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index 2f48e50..4975a7f 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -11,7 +11,6 @@ select USE_NATIVE_RAMINIT select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X - select SYSTEM_TYPE_LAPTOP select GFX_GMA_PANEL_1_ON_EDP select MAINBOARD_HAS_LIBGFXINIT select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/compulab/intense_pc/Kconfig b/src/mainboard/compulab/intense_pc/Kconfig index 68a01f1..0ada3ce 100644 --- a/src/mainboard/compulab/intense_pc/Kconfig +++ b/src/mainboard/compulab/intense_pc/Kconfig @@ -10,7 +10,6 @@ select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 - select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT select SUPERIO_SMSC_SIO1007 select MAINBOARD_HAS_LIBGFXINIT diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index 283ff65..5b27af2 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -4,7 +4,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_M select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 20d2e44..f46c38a 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -14,7 +14,6 @@ select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select INTEL_INT15 - select SYSTEM_TYPE_LAPTOP if !BOARD_GOOGLE_BUDDY if BOARD_GOOGLE_BASEBOARD_AURON diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 4e01455..e8aac2e 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_C216 select EC_QUANTA_ENE_KB3940Q diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 92bafee..2835dd8 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -15,7 +15,6 @@ select SOC_INTEL_BRASWELL select HAVE_ACPI_RESUME select PCIEXP_L1_SUB_STATE if !BOARD_GOOGLE_CYAN - select SYSTEM_TYPE_LAPTOP select USE_GOOGLE_FSP if BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 1ec4941..b3dbc33 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -21,7 +21,6 @@ config BASEBOARD_DEDEDE_LAPTOP def_bool n - select SYSTEM_TYPE_LAPTOP config CHROMEOS bool diff --git a/src/mainboard/google/deltaur/Kconfig b/src/mainboard/google/deltaur/Kconfig index ddcdb26..b15bec8 100644 --- a/src/mainboard/google/deltaur/Kconfig +++ b/src/mainboard/google/deltaur/Kconfig @@ -15,7 +15,6 @@ select MAINBOARD_HAS_TPM2 select MAINBOARD_USES_IFD_EC_REGION select SOC_INTEL_TIGERLAKE - select SYSTEM_TYPE_LAPTOP select MAINBOARD_USES_IFD_GBE_REGION if BOARD_GOOGLE_DELTAN select SOC_INTEL_COMMON_BLOCK_HDA_VERB diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index c61a5b3..9ff354a 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -19,7 +19,6 @@ select SOC_INTEL_COMETLAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE - select SYSTEM_TYPE_LAPTOP select TPM2 select MAINBOARD_USES_IFD_EC_REGION diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index dcc5b38..31ff6e9 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -21,7 +21,6 @@ select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_TPM2 select SOC_INTEL_KABYLAKE - select SYSTEM_TYPE_CONVERTIBLE config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 5e3545a..eda91c5 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -18,7 +18,6 @@ select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select SOC_INTEL_SKYLAKE - select SYSTEM_TYPE_LAPTOP select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_NO_FSP_GOP if !BOARD_GOOGLE_GLADOS diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 46aa4d1..3b9fc5e 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -2,7 +2,6 @@ config BOARD_GOOGLE_BASEBOARD_HATCH def_bool n select BOARD_GOOGLE_HATCH_COMMON - select SYSTEM_TYPE_LAPTOP select VBOOT_LID_SWITCH config BOARD_GOOGLE_BASEBOARD_PUFF diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 07eb585..df9337f 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -33,7 +33,6 @@ select PCIEXP_COMMON_CLOCK select PCIEXP_L1_SUB_STATE select HAVE_EM100_SUPPORT - select SYSTEM_TYPE_LAPTOP if BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 2c2a05d..3a6c27b 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_C216 select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 7d9e1e8..9a258e2 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -39,7 +39,6 @@ config BASEBOARD_OCTOPUS_LAPTOP def_bool n - select SYSTEM_TYPE_LAPTOP config CHROMEOS bool diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 4afd761..6d1f1e5 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_C216 select EC_COMPAL_ENE932 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 8553821..20181a7 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -182,7 +182,6 @@ select EXCLUDE_NATIVE_SD_INTERFACE select MAINBOARD_HAS_SPI_TPM_CR50 select NO_FADT_8042 - select SYSTEM_TYPE_DETACHABLE select VARIANT_HAS_CAMERA_ACPI select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR @@ -200,7 +199,6 @@ def_bool n select DRIVERS_I2C_MAX98927 select NO_FADT_8042 - select SYSTEM_TYPE_DETACHABLE select VARIANT_HAS_CAMERA_ACPI select MAINBOARD_HAS_I2C_TPM_CR50 diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 3cb5e26..f54f131 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -13,7 +13,6 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 - select SYSTEM_TYPE_LAPTOP if !BOARD_GOOGLE_NINJA && !BOARD_GOOGLE_SUMO if BOARD_GOOGLE_BASEBOARD_RAMBI diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 25d02cd..2a169ea 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -27,7 +27,6 @@ config BASEBOARD_REEF_LAPTOP def_bool n - select SYSTEM_TYPE_LAPTOP config DRIVER_TPM_I2C_BUS hex diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 3cd4965..9af4a7d 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -20,8 +20,6 @@ select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE select SPD_READ_BY_WORD - select SYSTEM_TYPE_LAPTOP if BOARD_GOOGLE_SARIEN - select SYSTEM_TYPE_CONVERTIBLE if BOARD_GOOGLE_ARCADA select TPM2 select MAINBOARD_USES_IFD_EC_REGION select MAINBOARD_USES_IFD_GBE_REGION if BOARD_GOOGLE_SARIEN diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 21659ab..13857f4 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -1,6 +1,5 @@ config BOARD_GOOGLE_BASEBOARD_SLIPPY def_bool n - select SYSTEM_TYPE_LAPTOP select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index b0ab7f9..6586bb0 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_C216 select EC_QUANTA_IT8518 diff --git a/src/mainboard/google/veyron/Kconfig.name b/src/mainboard/google/veyron/Kconfig.name index bf734cc..f7b30fe 100644 --- a/src/mainboard/google/veyron/Kconfig.name +++ b/src/mainboard/google/veyron/Kconfig.name @@ -3,24 +3,19 @@ config BOARD_GOOGLE_VEYRON_JAQ bool "-> Veyron_Jaq (Haier Chromebook 11)" select BOARD_GOOGLE_VEYRON - select SYSTEM_TYPE_LAPTOP config BOARD_GOOGLE_VEYRON_JERRY bool "-> Veyron_Jerry (Hisense Chromebook 11)" select BOARD_GOOGLE_VEYRON - select SYSTEM_TYPE_LAPTOP config BOARD_GOOGLE_VEYRON_MIGHTY bool "-> Veyron_Mighty (Haier Chromebook 11(edu))" select BOARD_GOOGLE_VEYRON - select SYSTEM_TYPE_LAPTOP config BOARD_GOOGLE_VEYRON_MINNIE bool "-> Veyron_Minnie (ASUS Chromebook Flip C100)" select BOARD_GOOGLE_VEYRON - select SYSTEM_TYPE_LAPTOP config BOARD_GOOGLE_VEYRON_SPEEDY bool "-> Veyron_Speedy (ASUS C201 Chromebook)" select BOARD_GOOGLE_VEYRON - select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 9a2e373..8a44ddf 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -34,7 +34,6 @@ select PCIEXP_COMMON_CLOCK select PCIEXP_L1_SUB_STATE select HAVE_EM100_SUPPORT - select SYSTEM_TYPE_LAPTOP select DRIVERS_GENERIC_MAX98357A select HAVE_ACPI_RESUME select DRIVERS_USB_ACPI diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index 77c929f..bf51d33 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -4,7 +4,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig index c4cd3a4..8155807 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig @@ -9,7 +9,6 @@ select HAVE_OPTION_TABLE select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE - select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT if BOARD_HP_SNB_IVB_LAPTOPS diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig index 8ed2aff..0e1d3b9 100644 --- a/src/mainboard/intel/glkrvp/Kconfig +++ b/src/mainboard/intel/glkrvp/Kconfig @@ -18,7 +18,6 @@ config BASEBOARD_GLKRVP_LAPTOP def_bool n - select SYSTEM_TYPE_LAPTOP choice prompt "ON BOARD EC" diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 65201ab..b85bf47 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -4,7 +4,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/lenovo/l520/Kconfig b/src/mainboard/lenovo/l520/Kconfig index 5b9344a..626f450 100644 --- a/src/mainboard/lenovo/l520/Kconfig +++ b/src/mainboard/lenovo/l520/Kconfig @@ -15,7 +15,6 @@ select GFX_GMA_PANEL_1_ON_LVDS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X - select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT config MAINBOARD_DIR diff --git a/src/mainboard/lenovo/s230u/Kconfig b/src/mainboard/lenovo/s230u/Kconfig index 64f4b29..a00b471 100644 --- a/src/mainboard/lenovo/s230u/Kconfig +++ b/src/mainboard/lenovo/s230u/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index e6f5631..20d4d73 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -3,7 +3,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_P select NORTHBRIDGE_INTEL_GM45 select SOUTHBRIDGE_INTEL_I82801IX diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index e939234..d462159 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_IRONLAKE select SOUTHBRIDGE_INTEL_IBEXPEAK select EC_LENOVO_PMH7 diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index 182ca46..c2b5af1 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index e2fd824..35c9f64 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 6139452..7fc7280 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -18,7 +18,6 @@ select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 - select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT select DRIVERS_LENOVO_HYBRID_GRAPHICS select MAINBOARD_HAS_LIBGFXINIT diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 81b87c8..02e5e47 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/lenovo/t440p/Kconfig b/src/mainboard/lenovo/t440p/Kconfig index adb1722..a313eae 100644 --- a/src/mainboard/lenovo/t440p/Kconfig +++ b/src/mainboard/lenovo/t440p/Kconfig @@ -20,7 +20,6 @@ select NORTHBRIDGE_INTEL_HASWELL select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_LYNXPOINT - select SYSTEM_TYPE_LAPTOP select MAINBOARD_USES_IFD_GBE_REGION select H8_HAS_BAT_TRESHOLDS_IMPL diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 3529367..0cfa6e4 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -1,6 +1,5 @@ config BOARD_LENOVO_BASEBOARD_T520 def_bool n - select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 4dc77e9..fb1089f 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -1,6 +1,5 @@ config BOARD_LENOVO_BASEBOARD_T530 def_bool n - select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 57172ca..4380a6d 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_M select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index 06c5d83..276f7c0 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index 246e1db..33d568a 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 731f4cb..b4446db 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_BGA956 select NORTHBRIDGE_INTEL_GM45 select SOUTHBRIDGE_INTEL_I82801IX diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index d73eac3..4b50e48 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_IRONLAKE select SOUTHBRIDGE_INTEL_IBEXPEAK select EC_LENOVO_PMH7 diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 33e15a8..14ded19 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index f134bc8..097242a 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 5083fd5..1ceb085 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_M select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM diff --git a/src/mainboard/packardbell/ms2290/Kconfig b/src/mainboard/packardbell/ms2290/Kconfig index 4fc971f..7e00e9c 100644 --- a/src/mainboard/packardbell/ms2290/Kconfig +++ b/src/mainboard/packardbell/ms2290/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_IRONLAKE select SOUTHBRIDGE_INTEL_IBEXPEAK select HAVE_OPTION_TABLE diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index 202a35d..78aa0d6 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -1,6 +1,5 @@ config BOARD_PURISM_BASEBOARD_LIBREM_BDW def_bool n - select SYSTEM_TYPE_LAPTOP select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index c86ebf1..d55bc73 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -14,7 +14,6 @@ select SOC_INTEL_KABYLAKE if BOARD_PURISM_LIBREM13_V4 || BOARD_PURISM_LIBREM15_V4 select SOC_INTEL_SKYLAKE if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM15_V3 select SPD_READ_BY_WORD - select SYSTEM_TYPE_LAPTOP if BOARD_PURISM_BASEBOARD_LIBREM_SKL diff --git a/src/mainboard/razer/blade_stealth_kbl/Kconfig b/src/mainboard/razer/blade_stealth_kbl/Kconfig index 532bd76..4b6a338 100644 --- a/src/mainboard/razer/blade_stealth_kbl/Kconfig +++ b/src/mainboard/razer/blade_stealth_kbl/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select BOARD_ROMSIZE_KB_8192 select SUPERIO_ITE_IT8528E select SOC_INTEL_KABYLAKE diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index 9d08c96..742e818 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_M select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM diff --git a/src/mainboard/roda/rk9/Kconfig b/src/mainboard/roda/rk9/Kconfig index 7516255..4342d34 100644 --- a/src/mainboard/roda/rk9/Kconfig +++ b/src/mainboard/roda/rk9/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_BGA956 select NORTHBRIDGE_INTEL_GM45 select SOUTHBRIDGE_INTEL_I82801IX diff --git a/src/mainboard/roda/rv11/Kconfig b/src/mainboard/roda/rv11/Kconfig index 70c383f..af71965 100644 --- a/src/mainboard/roda/rv11/Kconfig +++ b/src/mainboard/roda/rv11/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_C216 select BOARD_ROMSIZE_KB_16384 diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 6e72921..5a5006c 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/system76/lemp9/Kconfig b/src/mainboard/system76/lemp9/Kconfig index cc21ca9..849b30d 100644 --- a/src/mainboard/system76/lemp9/Kconfig +++ b/src/mainboard/system76/lemp9/Kconfig @@ -18,7 +18,6 @@ select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_READ_BY_WORD - select SYSTEM_TYPE_LAPTOP select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB config MAINBOARD_DIR -- To view, visit https://review.coreboot.org/c/coreboot/+/42142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib546706d04fede6c14ac57280ae72dca4fb7085b Gerrit-Change-Number: 42142 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: mb/google: Add ALIGNED flag to known sections that need alignment
by Hung-Te Lin (Code Review) 14 Jun '23

14 Jun '23

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37263 ) Change subject: mb/google: Add ALIGNED flag to known sections that need alignment ...................................................................... mb/google: Add ALIGNED flag to known sections that need alignment Update sections in chromeos.fmd that need 4k alignment: - RW_ELOG: By src/driver/elog/elog.c - RW_NVRAM: By src/security/vboot/vbnv_flash.c - {RO,RW}_DDR_TRAINING: By soc/qualcomm/common/qclib.c and mainboard/kukui/romstage.c Change-Id: If6aacf6265f552e3190782dd9a78e0612b8c3a55 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/auron/chromeos.fmd M src/mainboard/google/beltino/chromeos.fmd M src/mainboard/google/butterfly/chromeos.fmd M src/mainboard/google/cheza/chromeos.fmd M src/mainboard/google/cyan/chromeos.fmd M src/mainboard/google/dragonegg/chromeos.fmd M src/mainboard/google/drallion/chromeos.fmd M src/mainboard/google/eve/chromeos.fmd M src/mainboard/google/fizz/chromeos.fmd M src/mainboard/google/foster/chromeos.fmd M src/mainboard/google/gale/chromeos.fmd M src/mainboard/google/glados/chromeos.fmd M src/mainboard/google/gru/chromeos.fmd M src/mainboard/google/hatch/chromeos-16MiB.fmd M src/mainboard/google/hatch/chromeos.fmd M src/mainboard/google/jecht/chromeos.fmd M src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/chromeos.fmd M src/mainboard/google/link/chromeos.fmd M src/mainboard/google/mistral/chromeos.fmd M src/mainboard/google/nyan/chromeos.fmd M src/mainboard/google/nyan_big/chromeos.fmd M src/mainboard/google/nyan_blaze/chromeos.fmd M src/mainboard/google/oak/chromeos.fmd M src/mainboard/google/octopus/chromeos.fmd M src/mainboard/google/parrot/chromeos.fmd M src/mainboard/google/poppy/chromeos.fmd M src/mainboard/google/rambi/chromeos.fmd M src/mainboard/google/reef/chromeos.fmd M src/mainboard/google/sarien/chromeos.fmd M src/mainboard/google/slippy/chromeos.fmd M src/mainboard/google/smaug/chromeos.fmd M src/mainboard/google/storm/chromeos.fmd M src/mainboard/google/stout/chromeos.fmd M src/mainboard/google/trogdor/chromeos.fmd M src/mainboard/google/veyron/chromeos.fmd M src/mainboard/google/veyron_mickey/chromeos.fmd M src/mainboard/google/veyron_rialto/chromeos.fmd 39 files changed, 70 insertions(+), 69 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/37263/1 diff --git a/src/mainboard/google/auron/chromeos.fmd b/src/mainboard/google/auron/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/auron/chromeos.fmd +++ b/src/mainboard/google/auron/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/beltino/chromeos.fmd b/src/mainboard/google/beltino/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/beltino/chromeos.fmd +++ b/src/mainboard/google/beltino/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/butterfly/chromeos.fmd b/src/mainboard/google/butterfly/chromeos.fmd index 93048a3..6af9ab8 100644 --- a/src/mainboard/google/butterfly/chromeos.fmd +++ b/src/mainboard/google/butterfly/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/cheza/chromeos.fmd b/src/mainboard/google/cheza/chromeos.fmd index b0d2d99..109f61b 100644 --- a/src/mainboard/google/cheza/chromeos.fmd +++ b/src/mainboard/google/cheza/chromeos.fmd @@ -24,16 +24,16 @@ RO_FRID 0x100 } RO_VPD(PRESERVE) 16K - RO_DDR_TRAINING(PRESERVE) 8K + RO_DDR_TRAINING(PRESERVE,ALIGNED) 8K RO_LIMITS_CFG(PRESERVE) 4K RO_FSG(PRESERVE) } RW_VPD(PRESERVE) 32K - RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K + RW_NVRAM(PRESERVE,ALIGNED) 16K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K RW_LIMITS_CFG(PRESERVE) 4K - RW_ELOG(PRESERVE) 4K + RW_ELOG(PRESERVE,ALIGNED) 4K RW_SHARED 4K { SHARED_DATA } diff --git a/src/mainboard/google/cyan/chromeos.fmd b/src/mainboard/google/cyan/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/cyan/chromeos.fmd +++ b/src/mainboard/google/cyan/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/dragonegg/chromeos.fmd b/src/mainboard/google/dragonegg/chromeos.fmd index 7bdeb17..a0bf5f2 100644 --- a/src/mainboard/google/dragonegg/chromeos.fmd +++ b/src/mainboard/google/dragonegg/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } RW_LEGACY(CBFS)@0x5d0000 0x230000 # Make WP_RO region align with SPI vendor diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd index 6e9170e..da90787 100644 --- a/src/mainboard/google/drallion/chromeos.fmd +++ b/src/mainboard/google/drallion/chromeos.fmd @@ -25,13 +25,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } WP_RO@0x17c8000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 diff --git a/src/mainboard/google/eve/chromeos.fmd b/src/mainboard/google/eve/chromeos.fmd index 1cc4a61..2b3a2bb 100644 --- a/src/mainboard/google/eve/chromeos.fmd +++ b/src/mainboard/google/eve/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 diff --git a/src/mainboard/google/fizz/chromeos.fmd b/src/mainboard/google/fizz/chromeos.fmd index 1cc4a61..2b3a2bb 100644 --- a/src/mainboard/google/fizz/chromeos.fmd +++ b/src/mainboard/google/fizz/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 diff --git a/src/mainboard/google/foster/chromeos.fmd b/src/mainboard/google/foster/chromeos.fmd index f9a531c..5f47ba7 100644 --- a/src/mainboard/google/foster/chromeos.fmd +++ b/src/mainboard/google/foster/chromeos.fmd @@ -17,12 +17,12 @@ RW_SHARED@0x378000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x37c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x37c000 0x4000 RW_SECTION_B@0x380000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 RW_FWID_B@0x77f00 0x100 } RW_VPD(PRESERVE)@0x3f8000 0x4000 - RW_NVRAM(PRESERVE)@0x3fc000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x3fc000 0x4000 } diff --git a/src/mainboard/google/gale/chromeos.fmd b/src/mainboard/google/gale/chromeos.fmd index 3a55bdc..120f7b7 100644 --- a/src/mainboard/google/gale/chromeos.fmd +++ b/src/mainboard/google/gale/chromeos.fmd @@ -27,7 +27,7 @@ RW_FWID_B@0x14ff00 0x100 } RW_VPD(PRESERVE)@0x6e0000 0x8000 - RW_ELOG(PRESERVE)@0x6e8000 0x8000 - RW_NVRAM(PRESERVE)@0x6f0000 0x10000 + RW_ELOG(PRESERVE,ALIGNED)@0x6e8000 0x8000 + RW_NVRAM(PRESERVE,ALIGNED)@0x6f0000 0x10000 RW_LEGACY(CBFS)@0x700000 0x100000 } diff --git a/src/mainboard/google/glados/chromeos.fmd b/src/mainboard/google/glados/chromeos.fmd index 9ba1bf7..0f516e2 100644 --- a/src/mainboard/google/glados/chromeos.fmd +++ b/src/mainboard/google/glados/chromeos.fmd @@ -15,13 +15,13 @@ RW_FWID_B@0x3effc0 0x40 } RW_MRC_CACHE@0x7e0000 0x10000 - RW_ELOG(PRESERVE)@0x7f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x7f0000 0x4000 RW_SHARED@0x7f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x7f8000 0x2000 - RW_NVRAM(PRESERVE)@0x7fa000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x7fa000 0x6000 SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 WP_RO@0xa00000 0x400000 { diff --git a/src/mainboard/google/gru/chromeos.fmd b/src/mainboard/google/gru/chromeos.fmd index 032f472..cada219 100644 --- a/src/mainboard/google/gru/chromeos.fmd +++ b/src/mainboard/google/gru/chromeos.fmd @@ -20,11 +20,11 @@ FW_MAIN_B(CBFS)@0x2000 0xe5f00 RW_FWID_B@0xe7f00 0x100 } - RW_ELOG(PRESERVE)@0x5d8000 0x1000 + RW_ELOG(PRESERVE,ALIGNED)@0x5d8000 0x1000 RW_UNUSED@0x5d9000 0x7000 RW_SHARED@0x5e0000 0x10000 { SHARED_DATA@0x0 0x10000 } - RW_NVRAM(PRESERVE)@0x5f0000 0x10000 + RW_NVRAM(PRESERVE,ALIGNED)@0x5f0000 0x10000 RW_LEGACY(CBFS)@0x600000 0x200000 } diff --git a/src/mainboard/google/hatch/chromeos-16MiB.fmd b/src/mainboard/google/hatch/chromeos-16MiB.fmd index 8880a4f..bbc666a 100644 --- a/src/mainboard/google/hatch/chromeos-16MiB.fmd +++ b/src/mainboard/google/hatch/chromeos-16MiB.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } # RW_LEGACY needs to be minimum of 1MB RW_LEGACY(CBFS)@0x700000 0x100000 diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd index 8368b0a..9e649d7 100644 --- a/src/mainboard/google/hatch/chromeos.fmd +++ b/src/mainboard/google/hatch/chromeos.fmd @@ -23,13 +23,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x20000 } - RW_ELOG(PRESERVE)@0x30000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x30000 0x4000 RW_SHARED@0x34000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x38000 0x2000 - RW_NVRAM(PRESERVE)@0x3a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x3a000 0x6000 } # Make WP_RO region align with SPI vendor # memory protected range specification. diff --git a/src/mainboard/google/jecht/chromeos.fmd b/src/mainboard/google/jecht/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/jecht/chromeos.fmd +++ b/src/mainboard/google/jecht/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd index d7d0a88..0888262 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd +++ b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd @@ -14,14 +14,14 @@ FW_MAIN_B(CBFS)@0x10000 0x20DFC0 RW_FWID_B@0x21DFC0 0x40 } - RW_ELOG(PRESERVE)@0x45D000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x45D000 0x4000 RW_SHARED@0x461000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x465000 0x2000 - RW_NVRAM(PRESERVE)@0x467000 0x5000 + RW_NVRAM(PRESERVE,ALIGNED)@0x467000 0x5000 RW_UNUSED@0x46C000 0x14000 SMMSTORE(PRESERVE)@0x480000 0x20000 RW_LEGACY(CBFS)@0x4a0000 0x760000 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 098ce49..c75233e 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select RTC + select FMD_GENPARSER select SOC_MEDIATEK_MT8183 select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS diff --git a/src/mainboard/google/kukui/chromeos.fmd b/src/mainboard/google/kukui/chromeos.fmd index 2635854..9456393 100644 --- a/src/mainboard/google/kukui/chromeos.fmd +++ b/src/mainboard/google/kukui/chromeos.fmd @@ -28,9 +28,9 @@ } RW_MISC 36K { RW_VPD(PRESERVE) 16K # At least 8K. - RW_NVRAM(PRESERVE) 8K - RW_DDR_TRAINING(PRESERVE) 8K - RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. + RW_NVRAM(PRESERVE,ALIGNED) 8K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K + RW_ELOG(PRESERVE,ALIGNED) 4K # Only ELOG_SIZE needed. } RW_SECTION_B 1500K { VBLOCK_B 8K diff --git a/src/mainboard/google/link/chromeos.fmd b/src/mainboard/google/link/chromeos.fmd index 3841445..cf7f76d 100644 --- a/src/mainboard/google/link/chromeos.fmd +++ b/src/mainboard/google/link/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd index 4d5f666..d2d92e6 100644 --- a/src/mainboard/google/mistral/chromeos.fmd +++ b/src/mainboard/google/mistral/chromeos.fmd @@ -23,13 +23,13 @@ RO_FRID 0x100 } RO_VPD(PRESERVE) 128K - RO_DDR_TRAINING(PRESERVE) 8K + RO_DDR_TRAINING(PRESERVE,ALIGNED) 8K } RW_VPD(PRESERVE) 32K - RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K - RW_ELOG(PRESERVE) 4K + RW_NVRAM(PRESERVE,ALIGNED) 16K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K + RW_ELOG(PRESERVE,ALIGNED) 4K RW_SHARED 4K { SHARED_DATA } diff --git a/src/mainboard/google/nyan/chromeos.fmd b/src/mainboard/google/nyan/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/nyan/chromeos.fmd +++ b/src/mainboard/google/nyan/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/nyan_big/chromeos.fmd b/src/mainboard/google/nyan_big/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/nyan_big/chromeos.fmd +++ b/src/mainboard/google/nyan_big/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/nyan_blaze/chromeos.fmd b/src/mainboard/google/nyan_blaze/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.fmd +++ b/src/mainboard/google/nyan_blaze/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/oak/chromeos.fmd b/src/mainboard/google/oak/chromeos.fmd index df35976..136c0d8 100644 --- a/src/mainboard/google/oak/chromeos.fmd +++ b/src/mainboard/google/oak/chromeos.fmd @@ -17,8 +17,8 @@ RW_SHARED@0x278000 0x2000 { SHARED_DATA@0x0 0x2000 } - RW_NVRAM(PRESERVE)@0x27a000 0x2000 - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x27a000 0x2000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/octopus/chromeos.fmd b/src/mainboard/google/octopus/chromeos.fmd index 332465a..28c1a5f 100644 --- a/src/mainboard/google/octopus/chromeos.fmd +++ b/src/mainboard/google/octopus/chromeos.fmd @@ -19,13 +19,13 @@ RW_VAR_MRC_CACHE@0x20000 0x1000 } } - RW_ELOG(PRESERVE)@0x21000 0x3000 + RW_ELOG(PRESERVE,ALIGNED)@0x21000 0x3000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x5000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x5000 FPF_STATUS@0x2f000 0x1000 } RW_SECTION_A@0x430000 0x480000 { diff --git a/src/mainboard/google/parrot/chromeos.fmd b/src/mainboard/google/parrot/chromeos.fmd index 6752888..625a30e 100644 --- a/src/mainboard/google/parrot/chromeos.fmd +++ b/src/mainboard/google/parrot/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/poppy/chromeos.fmd b/src/mainboard/google/poppy/chromeos.fmd index 1cc4a61..2b3a2bb 100644 --- a/src/mainboard/google/poppy/chromeos.fmd +++ b/src/mainboard/google/poppy/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 diff --git a/src/mainboard/google/rambi/chromeos.fmd b/src/mainboard/google/rambi/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/rambi/chromeos.fmd +++ b/src/mainboard/google/rambi/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index 87eb4e7..72d8df1 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -17,13 +17,13 @@ RW_MRC_CACHE@0x10000 0x10000 RW_VAR_MRC_CACHE@0x20000 0x1000 } - RW_ELOG(PRESERVE)@0x21000 0x3000 + RW_ELOG(PRESERVE,ALIGNED)@0x21000 0x3000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x5000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x5000 FPF_STATUS@0x2f000 0x1000 } RW_SECTION_A@0x430000 0x480000 { diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd index 65a915a..b63149f4 100644 --- a/src/mainboard/google/sarien/chromeos.fmd +++ b/src/mainboard/google/sarien/chromeos.fmd @@ -26,13 +26,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } WP_RO@0x1800000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 diff --git a/src/mainboard/google/slippy/chromeos.fmd b/src/mainboard/google/slippy/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/slippy/chromeos.fmd +++ b/src/mainboard/google/slippy/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/smaug/chromeos.fmd b/src/mainboard/google/smaug/chromeos.fmd index 4b1ba19..cb5ec8e 100644 --- a/src/mainboard/google/smaug/chromeos.fmd +++ b/src/mainboard/google/smaug/chromeos.fmd @@ -21,7 +21,7 @@ } RW_SHARED@0xf00000 0x4000 SHARED_DATA@0xf04000 0x4000 - RW_ELOG(PRESERVE)@0xf08000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0xf08000 0x4000 RW_VPD(PRESERVE)@0xf0c000 0x8000 - RW_NVRAM(PRESERVE)@0xf20000 0x10000 + RW_NVRAM(PRESERVE,ALIGNED)@0xf20000 0x10000 } diff --git a/src/mainboard/google/storm/chromeos.fmd b/src/mainboard/google/storm/chromeos.fmd index 3a55bdc..120f7b7 100644 --- a/src/mainboard/google/storm/chromeos.fmd +++ b/src/mainboard/google/storm/chromeos.fmd @@ -27,7 +27,7 @@ RW_FWID_B@0x14ff00 0x100 } RW_VPD(PRESERVE)@0x6e0000 0x8000 - RW_ELOG(PRESERVE)@0x6e8000 0x8000 - RW_NVRAM(PRESERVE)@0x6f0000 0x10000 + RW_ELOG(PRESERVE,ALIGNED)@0x6e8000 0x8000 + RW_NVRAM(PRESERVE,ALIGNED)@0x6f0000 0x10000 RW_LEGACY(CBFS)@0x700000 0x100000 } diff --git a/src/mainboard/google/stout/chromeos.fmd b/src/mainboard/google/stout/chromeos.fmd index 93048a3..6af9ab8 100644 --- a/src/mainboard/google/stout/chromeos.fmd +++ b/src/mainboard/google/stout/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd index 9af3d51..27ff291 100644 --- a/src/mainboard/google/trogdor/chromeos.fmd +++ b/src/mainboard/google/trogdor/chromeos.fmd @@ -23,16 +23,16 @@ RO_FRID 0x100 } RO_VPD(PRESERVE) 16K - RO_DDR_TRAINING(PRESERVE) 8K + RO_DDR_TRAINING(PRESERVE,ALIGNED) 8K RO_LIMITS_CFG(PRESERVE) 4K RO_FSG(PRESERVE) } RW_VPD(PRESERVE) 32K - RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K + RW_NVRAM(PRESERVE,ALIGNED) 16K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K RW_LIMITS_CFG(PRESERVE) 4K - RW_ELOG(PRESERVE) 4K + RW_ELOG(PRESERVE,ALIGNED) 4K RW_SHARED 4K { SHARED_DATA } diff --git a/src/mainboard/google/veyron/chromeos.fmd b/src/mainboard/google/veyron/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/veyron/chromeos.fmd +++ b/src/mainboard/google/veyron/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/veyron_mickey/chromeos.fmd b/src/mainboard/google/veyron_mickey/chromeos.fmd index 76ab2c3..da8bbc5 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.fmd +++ b/src/mainboard/google/veyron_mickey/chromeos.fmd @@ -17,8 +17,8 @@ RW_SHARED@0x278000 0x2000 { SHARED_DATA@0x0 0x2000 } - RW_NVRAM(PRESERVE)@0x27a000 0x2000 - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x27a000 0x2000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/veyron_rialto/chromeos.fmd b/src/mainboard/google/veyron_rialto/chromeos.fmd index df35976..136c0d8 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.fmd +++ b/src/mainboard/google/veyron_rialto/chromeos.fmd @@ -17,8 +17,8 @@ RW_SHARED@0x278000 0x2000 { SHARED_DATA@0x0 0x2000 } - RW_NVRAM(PRESERVE)@0x27a000 0x2000 - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x27a000 0x2000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 -- To view, visit https://review.coreboot.org/c/coreboot/+/37263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6aacf6265f552e3190782dd9a78e0612b8c3a55 Gerrit-Change-Number: 37263 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

5 32

Change in vboot[master]: [Debug] Disable Wimplicit-fallthrough
by Selma Bensaid (Code Review) 10 Jun '23

10 Jun '23

Hello Selma Bensaid, I'd like you to do a code review. Please visit https://review.coreboot.org/c/vboot/+/38910 to review the following change. Change subject: [Debug] Disable Wimplicit-fallthrough ...................................................................... [Debug] Disable Wimplicit-fallthrough Signed-off-by: Selma BENSAID <selma.bensaid(a)intel.corp-partner.google.com> Change-Id: Ib50af965b30509ba96b01c937474a9a064836e1f --- M Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/vboot refs/changes/10/38910/1 diff --git a/Makefile b/Makefile index 0539e8d..62c0307 100644 --- a/Makefile +++ b/Makefile @@ -142,7 +142,7 @@ -Wundef -Wmissing-prototypes -Wno-trigraphs -Wredundant-decls -Wshadow \ -Wwrite-strings -Wstrict-aliasing -Wdate-time -Wno-unknown-warning \ -Wno-address-of-packed-member -ffunction-sections -fdata-sections \ - -Wimplicit-fallthrough ${DEBUG_FLAGS} + ${DEBUG_FLAGS} # Note: FIRMWARE_ARCH is defined by the Chromium OS ebuild. ifeq (${FIRMWARE_ARCH},arm) -- To view, visit https://review.coreboot.org/c/vboot/+/38910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: vboot Gerrit-Branch: master Gerrit-Change-Id: Ib50af965b30509ba96b01c937474a9a064836e1f Gerrit-Change-Number: 38910 Gerrit-PatchSet: 1 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

2 3

Change in ...vboot[master]: vboot: Fix build error related to VB2_SHARED_DATA_VERSION_MINOR
by Rizwan Qureshi (Code Review) 10 Jun '23

10 Jun '23

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/vboot/+/32679 Change subject: vboot: Fix build error related to VB2_SHARED_DATA_VERSION_MINOR ...................................................................... vboot: Fix build error related to VB2_SHARED_DATA_VERSION_MINOR vboot fails to compile with the error "error: comparison is always false due to limited range of data type [-Werror=type-limits]" since struct_version_minor is uint16_t and can never be less than VB2_SHARED_DATA_VERSION_MINOR (0) Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: I0e68981fbecafe7ba40e00ee657e82c024a89325 --- M firmware/2lib/2misc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/vboot refs/changes/79/32679/1 diff --git a/firmware/2lib/2misc.c b/firmware/2lib/2misc.c index 95cbae3..195a0f9 100644 --- a/firmware/2lib/2misc.c +++ b/firmware/2lib/2misc.c @@ -128,7 +128,7 @@ return VB2_ERROR_SHARED_DATA_MAGIC; if (sd->struct_version_major != VB2_SHARED_DATA_VERSION_MAJOR || - sd->struct_version_minor < VB2_SHARED_DATA_VERSION_MINOR) + sd->struct_version_minor != VB2_SHARED_DATA_VERSION_MINOR) return VB2_ERROR_SHARED_DATA_VERSION; return VB2_SUCCESS; -- To view, visit https://review.coreboot.org/c/vboot/+/32679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: vboot Gerrit-Branch: master Gerrit-Change-Id: I0e68981fbecafe7ba40e00ee657e82c024a89325 Gerrit-Change-Number: 32679 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: payloads/external/GRUB2/Makefile: Add ./bootstrap to fix build
by Pablo Moyano (Code Review) 10 Jun '23

10 Jun '23

Pablo Moyano has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34105 ) Change subject: payloads/external/GRUB2/Makefile: Add ./bootstrap to fix build ...................................................................... payloads/external/GRUB2/Makefile: Add ./bootstrap to fix build At some point between Grub 2.02 and 2.04, something was added and it refuses to build without it. Change-Id: Ia8fca13fe58be55aa4569ff58bbfd76ab7a67cdd Signed-off-by: Pablo <42.pablo.ms(a)gmail.com> --- M payloads/external/GRUB2/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/34105/1 diff --git a/payloads/external/GRUB2/Makefile b/payloads/external/GRUB2/Makefile index 31c4066..b036aeb 100644 --- a/payloads/external/GRUB2/Makefile +++ b/payloads/external/GRUB2/Makefile @@ -28,7 +28,7 @@ echo " CONFIG GRUB2 $(NAME-y)" rm -rf grub2/build mkdir grub2/build - cd grub2 && ./autogen.sh + cd grub2 && ./bootstrap && ./autogen.sh cd grub2/build && ../configure CC="$(HOSTCC)" LD="$(LD)" \ FREETYPE="pkg-config freetype2" BUILD_FREETYPE="pkg-config freetype2" \ TARGET_CC="$(CC)" TARGET_OBJCOPY="$(OBJCOPY)" TARGET_STRIP="$(STRIP)" \ -- To view, visit https://review.coreboot.org/c/coreboot/+/34105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8fca13fe58be55aa4569ff58bbfd76ab7a67cdd Gerrit-Change-Number: 34105 Gerrit-PatchSet: 1 Gerrit-Owner: Pablo Moyano <42.pablo.ms(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: HACK: Enable PCIe refclk 100M usb
by Qizhong Cheng (Code Review) 10 Jun '23

10 Jun '23

Qizhong Cheng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48725 ) Change subject: HACK: Enable PCIe refclk 100M usb ...................................................................... HACK: Enable PCIe refclk 100M usb Don't pull into TOT. Thanks. A temporary patch for PCIe compliance test. Set GPIO65 pinmux for PCIe function which is clkreq#. Signed-off-by: mtk20626 <qizhong.cheng(a)mediatek.com> Change-Id: I978a2fa86fda8287436846e22ee3d8e2ced672ef --- M src/soc/mediatek/mt8192/usb.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/48725/1 diff --git a/src/soc/mediatek/mt8192/usb.c b/src/soc/mediatek/mt8192/usb.c index 44f2f15..08153d6 100644 --- a/src/soc/mediatek/mt8192/usb.c +++ b/src/soc/mediatek/mt8192/usb.c @@ -12,4 +12,5 @@ /* power on SSUSB SRAM FIFO */ setbits32(REG_SPM_POWERON_CONFIG_EN, 0xB160001); clrbits32(REG_SPM_SSPM_PWR_CON, 0x000001FF); + setbits32(REG_SPM_POWERON_CONFIG_EN + 0x380, 0x33); } -- To view, visit https://review.coreboot.org/c/coreboot/+/48725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I978a2fa86fda8287436846e22ee3d8e2ced672ef Gerrit-Change-Number: 48725 Gerrit-PatchSet: 1 Gerrit-Owner: Qizhong Cheng <qizhong.cheng(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: [WIP]soc/intel/xeon_sp: Allow experimental long mode support
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48502 ) Change subject: [WIP]soc/intel/xeon_sp: Allow experimental long mode support ...................................................................... [WIP]soc/intel/xeon_sp: Allow experimental long mode support The acpi_create_rmrr code needs to be cleaned up. Change-Id: I96817f69cdcaa1ea040bc328c50f5ab23c637cb2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/nb_acpi.c 3 files changed, 20 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/48502/1 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 2028a5e..8d9e469 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -25,7 +25,8 @@ config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_ALL_STAGES_X86_32 + select ARCH_ALL_STAGES_X86_32 if !EXP_ARCH_X86_64 + select ARCH_ALL_STAGES_X86_64 if EXP_ARCH_X86_64 select BOOT_DEVICE_SUPPORTS_WRITES select CPU_INTEL_COMMON select SOC_INTEL_COMMON diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 4fe8b20..807083f 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -219,9 +219,9 @@ // apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ - printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs); + printk(BIOS_SPEW, "%s injecting NVSA with 0x%lx\n", __FILE__, (uintptr_t)gnvs); acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (uint32_t)gnvs); + acpigen_write_name_dword("NVSA", (uint32_t)(uintptr_t)gnvs); acpigen_pop_len(); } } diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 19c3921..f586d9b 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -292,11 +292,11 @@ for (int stack = 0; stack <= PSTACK2; ++stack) { uint32_t bus = iio_resource.StackRes[stack].BusBase; - uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; + uintptr_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; if (!vtd_base) continue; uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); - printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, " + printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%lx, " "vtd_mmio_cap: 0x%llx\n", __func__, socket, stack, bus, vtd_base, vtd_mmio_cap); @@ -322,24 +322,24 @@ static unsigned long acpi_create_rmrr(unsigned long current) { - uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); +// uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); - uint32_t *ptr; + /* uint32_t *ptr; */ - // reserve memory - ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); - if (!ptr) { - ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); - assert(ptr != NULL); - memset(ptr, 0, size); - } + /* // reserve memory */ + /* ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); */ + /* if (!ptr) { */ + /* ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); */ + /* assert(ptr != NULL); */ + /* memset(ptr, 0, size); */ + /* } */ unsigned long tmp = current; - printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " - "End Address (limit): 0x%x\n", - 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); - current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, - (uint32_t) ((uint32_t) ptr + size - 1)); + /* printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " */ + /* "End Address (limit): 0x%x\n", */ + /* 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); */ + /* current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, */ + /* (uint32_t) ((uint32_t) ptr + size - 1)); */ printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " "PCI Path: 0x%x, 0x%x\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/48502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96817f69cdcaa1ea040bc328c50f5ab23c637cb2 Gerrit-Change-Number: 48502 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: sb/intel/bd82x6x/smihandler: Fix xHCI sleep handler
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41852 ) Change subject: sb/intel/bd82x6x/smihandler: Fix xHCI sleep handler ...................................................................... sb/intel/bd82x6x/smihandler: Fix xHCI sleep handler The xHCI S3/S4 quirk is only needed on PPT Revision A0. Fix always false condition by adding the missing read32 function call. Untested. Change-Id: Idc658aa9fe11c8ee93290e3d3ef66e73476f3c57 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/bd82x6x/smihandler.c 1 file changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/41852/1 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index cddb4cf..fbc7b81 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -100,6 +100,9 @@ switch (slp_typ) { case ACPI_S3: case ACPI_S4: + if (!pch_silicon_supported(PCH_TYPE_PPT, PCH_STEP_A0)) + break; + reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); reg16 &= ~0x03UL; pci_write_config32(PCH_XHCI_DEV, 0x74, reg16); @@ -112,14 +115,13 @@ PCI_BASE_ADDRESS_0) & ~0xFUL; if (!smm_validate_pointer((void *)(uintptr_t)xhci_bar)) { - /* FIXME: This looks broken */ - if ((xhci_bar + 0x4C0) & 1) + if (read32(xhci_bar + 0x4C0) & 1) pch_iobp_update(0xEC000082, ~0UL, (3 << 2)); - if ((xhci_bar + 0x4D0) & 1) + if (read32(xhci_bar + 0x4D0) & 1) pch_iobp_update(0xEC000182, ~0UL, (3 << 2)); - if ((xhci_bar + 0x4E0) & 1) + if (read32(xhci_bar + 0x4E0) & 1) pch_iobp_update(0xEC000282, ~0UL, (3 << 2)); - if ((xhci_bar + 0x4F0) & 1) + if (read32(xhci_bar + 0x4F0) & 1) pch_iobp_update(0xEC000382, ~0UL, (3 << 2)); } reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); -- To view, visit https://review.coreboot.org/c/coreboot/+/41852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc658aa9fe11c8ee93290e3d3ef66e73476f3c57 Gerrit-Change-Number: 41852 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 23

Change in coreboot[master]: soc/amd/common: Use ACPIMMIO_BASE() in ASL
by Kyösti Mälkki (Code Review) 10 Jun '23

10 Jun '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42944 ) Change subject: soc/amd/common: Use ACPIMMIO_BASE() in ASL ...................................................................... soc/amd/common: Use ACPIMMIO_BASE() in ASL Change-Id: Iff6bdbe5a12f1a47c7ce348a628e0b67aac37c7c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl M src/soc/amd/common/acpi/gpio_bank_lib.asl M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h M src/soc/amd/picasso/acpi/sb_fch.asl M src/soc/amd/stoneyridge/acpi/sb_fch.asl 5 files changed, 7 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/42944/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl index 837678a..f61f6a0 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl @@ -22,7 +22,7 @@ Name (RBUF, ResourceTemplate () { // Memory resource is for MISC FCH register set. // It is needed for enabling the clock. - Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) + Memory32Fixed(ReadWrite, ACPIMMIO_BASE(MISC), 0x100) }) Return (RBUF) diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl index f73340c..b60fba91 100644 --- a/src/soc/amd/common/acpi/gpio_bank_lib.asl +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -6,7 +6,7 @@ Method (GPAD, 0x1) { /* Arg0 - GPIO pin number */ - Return (Add(Multiply(Arg0, 4), ACPIMMIO_GPIO0_BASE)) + Return (Add(Multiply(Arg0, 4), ACPIMMIO_BASE(GPIO0))) } /* Read pin control dword */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index e5caefc..e8f4625 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -94,12 +94,6 @@ #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 -#ifdef __ACPI__ -/* ASL MemoryFixed32() fails if these are additions. */ -#define ACPIMMIO_MISC_BASE 0xfed80e00 -#define ACPIMMIO_GPIO0_BASE 0xfed81500 -#endif - #define ACPIMMIO_SM_PCI_BANK 0x0000 #define ACPIMMIO_GPIO_100_BANK 0x0100 #define ACPIMMIO_SMI_BANK 0x0200 diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 007df8d..d283402 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -34,7 +34,7 @@ ActiveLow, Exclusive, , , IRQR) { 0 } - Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x300) + Memory32Fixed (ReadWrite, ACPIMMIO_BASE(GPIO0), 0x300) } CreateDWordField (Local0, IRQR._INT, IRQN) If (PMOD) { @@ -44,7 +44,7 @@ } If (IRQN == 0x1f) { Return (ResourceTemplate() { - Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x300) + Memory32Fixed (ReadWrite, ACPIMMIO_BASE(GPIO0), 0x300) }) } Else { Return (Local0) @@ -396,7 +396,7 @@ Name (_HID, "AMD0040") Name (_UID, 0x3) Name (_CRS, ResourceTemplate() { - Memory32Fixed (ReadWrite, ACPIMMIO_MISC_BASE, 0x100) + Memory32Fixed (ReadWrite, ACPIMMIO_BASE(MISC), 0x100) }) Method (_STA, 0x0, NotSerialized) { diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl index c999b67..9adb82a 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl @@ -30,7 +30,7 @@ { Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) { 7 } - Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x300) + Memory32Fixed (ReadWrite, ACPIMMIO_BASE(GPIO0), 0x300) }) Method (_STA, 0x0, NotSerialized) @@ -132,7 +132,7 @@ Name (_HID, "AMD0040") Name (_UID, 0x3) Name (_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) + Memory32Fixed(ReadWrite, ACPIMMIO_BASE(MISC), 0x100) }) Method (_STA, 0x0, NotSerialized) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff6bdbe5a12f1a47c7ce348a628e0b67aac37c7c Gerrit-Change-Number: 42944 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Support FSP-T in long mode
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48501 ) Change subject: drivers/intel/fsp2_0: Support FSP-T in long mode ...................................................................... drivers/intel/fsp2_0: Support FSP-T in long mode TESTED on ocp/deltalake Change-Id: I6ce779f9d1b8733e8ca2db5e0f5e1058242e03f5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 2 files changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/48501/1 diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index c3bfbba..b46381b 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -6,6 +6,7 @@ #include <fsp/util.h> #include <cbfs.h> #include <types.h> +#include <mode_switch.h> void fsp_temp_ram_exit(void) { @@ -26,9 +27,12 @@ if (fsp_validate_component(&hdr, &file_data) != CB_SUCCESS) die("Invalid FSPM header!\n"); - temp_ram_exit = (void *)(hdr.image_base + hdr.temp_ram_exit_entry); + temp_ram_exit = (void *)(uintptr_t)(hdr.image_base + hdr.temp_ram_exit_entry); printk(BIOS_DEBUG, "Calling TempRamExit: %p\n", temp_ram_exit); - status = temp_ram_exit(NULL); + if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) + status = protected_mode_call_1arg(temp_ram_exit, (uintptr_t)NULL); + else + status = temp_ram_exit(NULL); if (status != FSP_SUCCESS) { printk(BIOS_CRIT, "TempRamExit returned 0x%08x\n", status); diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 04dc533..bb86d7b 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -12,6 +12,8 @@ .extern temp_ram_init_params +.code32 + .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -94,10 +96,18 @@ pop %ecx movl %ecx, temp_memory_start +#if ENV_X86_64 + #include <cpu/x86/64bit/entry64.inc> + movl %ebp, %edi + shlq $32, %rdi + movd %mm1, %rsi + or %rsi, %rdi +#else /* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */ push %ebp movd %mm1, %eax push %eax +#endif /* We can call into C functions now */ call bootblock_c_entry -- To view, visit https://review.coreboot.org/c/coreboot/+/48501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ce779f9d1b8733e8ca2db5e0f5e1058242e03f5 Gerrit-Change-Number: 48501 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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