Hello Iru Cai,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/46630
to review the following change.
Change subject: [WIP] mb/hp: Add EliteBook 820 G2 ......................................................................
[WIP] mb/hp: Add EliteBook 820 G2
Currently it boots to SeaBIOS.
Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai mytbk920423@gmail.com --- A src/mainboard/hp/820g2/Kconfig A src/mainboard/hp/820g2/Kconfig.name A src/mainboard/hp/820g2/Makefile.inc A src/mainboard/hp/820g2/acpi/ec.asl A src/mainboard/hp/820g2/acpi/superio.asl A src/mainboard/hp/820g2/acpi_tables.c A src/mainboard/hp/820g2/board_info.txt A src/mainboard/hp/820g2/devicetree.cb A src/mainboard/hp/820g2/dsdt.asl A src/mainboard/hp/820g2/gma-mainboard.ads A src/mainboard/hp/820g2/gpio.c A src/mainboard/hp/820g2/hda_verb.c A src/mainboard/hp/820g2/mainboard.c A src/mainboard/hp/820g2/pei_data.c A src/mainboard/hp/820g2/romstage.c 15 files changed, 444 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46630/1
diff --git a/src/mainboard/hp/820g2/Kconfig b/src/mainboard/hp/820g2/Kconfig new file mode 100644 index 0000000..f617551 --- /dev/null +++ b/src/mainboard/hp/820g2/Kconfig @@ -0,0 +1,34 @@ +if BOARD_HP_820_G2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select SOC_INTEL_BROADWELL + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default "hp/820g2" + +config MAINBOARD_PART_NUMBER + string + default "EliteBook 820 G2" + +config VGA_BIOS_FILE + string + default "pci8086,1616.rom" + +config VGA_BIOS_ID + string + default "8086,1616" + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/hp/820g2/Kconfig.name b/src/mainboard/hp/820g2/Kconfig.name new file mode 100644 index 0000000..3fcf1a1 --- /dev/null +++ b/src/mainboard/hp/820g2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_820_G2 + bool "EliteBook 820 G2" diff --git a/src/mainboard/hp/820g2/Makefile.inc b/src/mainboard/hp/820g2/Makefile.inc new file mode 100644 index 0000000..2543ee7 --- /dev/null +++ b/src/mainboard/hp/820g2/Makefile.inc @@ -0,0 +1,4 @@ +romstage-y += gpio.c +romstage-y += pei_data.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +ramstage-y += pei_data.c diff --git a/src/mainboard/hp/820g2/acpi/ec.asl b/src/mainboard/hp/820g2/acpi/ec.asl new file mode 100644 index 0000000..d39c59a --- /dev/null +++ b/src/mainboard/hp/820g2/acpi/ec.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 6) +/* FIXME: EC support */ +} diff --git a/src/mainboard/hp/820g2/acpi/superio.asl b/src/mainboard/hp/820g2/acpi/superio.asl new file mode 100644 index 0000000..55b1db5 --- /dev/null +++ b/src/mainboard/hp/820g2/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/hp/820g2/acpi_tables.c b/src/mainboard/hp/820g2/acpi_tables.c new file mode 100644 index 0000000..ca6f64b --- /dev/null +++ b/src/mainboard/hp/820g2/acpi_tables.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> +#include <arch/ioapic.h> +#include <soc/acpi.h> +#include <soc/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + acpi_init_gnvs(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + return acpi_madt_irq_overrides(current); +} diff --git a/src/mainboard/hp/820g2/board_info.txt b/src/mainboard/hp/820g2/board_info.txt new file mode 100644 index 0000000..db677c6 --- /dev/null +++ b/src/mainboard/hp/820g2/board_info.txt @@ -0,0 +1,2 @@ +Category: laptop +FIXME: put ROM package, ROM socketed, ROM protocol, Flashrom support, Release year diff --git a/src/mainboard/hp/820g2/devicetree.cb b/src/mainboard/hp/820g2/devicetree.cb new file mode 100644 index 0000000..57cf333 --- /dev/null +++ b/src/mainboard/hp/820g2/devicetree.cb @@ -0,0 +1,119 @@ +chip soc/intel/broadwell # FIXME: check these values + register "alt_gp_smi_en" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x000402e9" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpe0_en_1" = "0" + register "gpe0_en_2" = "0" + register "gpe0_en_3" = "0" + register "gpe0_en_4" = "0" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight_pwm_hz" = "200" + register "pcie_port_coalesce" = "1" + register "pcie_port_force_aspm" = "0" + register "sata_devslp_disable" = "0" + register "sata_devslp_mux" = "0" + register "sata_port0_gen3_dtle" = "0x0" + register "sata_port0_gen3_tx" = "0x0" + register "sata_port1_gen3_dtle" = "0x0" + register "sata_port1_gen3_tx" = "0x0" + register "sata_port2_gen3_dtle" = "0x0" + register "sata_port2_gen3_tx" = "0x0" + register "sata_port3_gen3_dtle" = "0x0" + register "sata_port3_gen3_tx" = "0x0" + register "sata_port_map" = "0xa" + register "sio_acpi_mode" = "0" + register "sio_i2c0_voltage" = "0" + register "sio_i2c1_voltage" = "0" + device cpu_cluster 0x0 on + device lapic 0x0 on + end + end + device domain 0x0 on + device pci 00.0 on # Host bridge + subsystemid 0x103c 0x225a + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x103c 0x225a + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x103c 0x225a + end + device pci 13.0 off # Smart Sound Audio DSP + end + device pci 14.0 on # xHCI Controller + subsystemid 0x103c 0x225a + end + device pci 15.0 off # Serial I/O DMA + end + device pci 15.1 off # I2C0 + end + device pci 15.2 off # I2C1 + end + device pci 15.3 off # GSPI0 + end + device pci 15.4 off # GSPI1 + end + device pci 15.5 off # UART0 + end + device pci 15.6 off # UART1 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x103c 0x225a + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 17.0 off # SDIO + end + device pci 19.0 on # Intel Gigabit Ethernet Unsupported PCI device 8086:15a2 + subsystemid 0x103c 0x225a + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x103c 0x225a + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x103c 0x225a + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x103c 0x225a + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 on # PCIe Port #4 + subsystemid 0x103c 0x225a + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x103c 0x225a + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge + subsystemid 0x103c 0x225a + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x103c 0x225a + end + device pci 1f.3 on # SMBus + subsystemid 0x103c 0x225a + end + device pci 1f.6 off # Thermal + end + end +end diff --git a/src/mainboard/hp/820g2/dsdt.asl b/src/mainboard/hp/820g2/dsdt.asl new file mode 100644 index 0000000..666115d --- /dev/null +++ b/src/mainboard/hp/820g2/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <soc/intel/broadwell/acpi/platform.asl> + #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <soc/intel/broadwell/acpi/systemagent.asl> + #include <soc/intel/broadwell/acpi/pch.asl> + } +} diff --git a/src/mainboard/hp/820g2/gma-mainboard.ads b/src/mainboard/hp/820g2/gma-mainboard.ads new file mode 100644 index 0000000..7b90060 --- /dev/null +++ b/src/mainboard/hp/820g2/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + HDMI1, + HDMI2, + eDP); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/820g2/gpio.c b/src/mainboard/hp/820g2/gpio.c new file mode 100644 index 0000000..b4ef103 --- /dev/null +++ b/src/mainboard/hp/820g2/gpio.c @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> + +const struct gpio_config mainboard_gpio_config[] = { + [0] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [2] = PCH_GPIO_OUT_LOW, + [3] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [4] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [5] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [6] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [7] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [8] = PCH_GPIO_OUT_HIGH, + [9] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [10] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [11] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [12] = PCH_GPIO_NATIVE, + [13] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [14] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [15] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [16] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [17] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [18] = PCH_GPIO_OUT_HIGH, + [19] = PCH_GPIO_NATIVE, + [20] = PCH_GPIO_NATIVE, + [21] = PCH_GPIO_NATIVE, + [22] = PCH_GPIO_NATIVE, + [23] = PCH_GPIO_NATIVE, + [24] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .reset = GPIO_RESET_RSMRST }, + [25] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = PCH_GPIO_OUT_HIGH, + [29] = PCH_GPIO_OUT_HIGH, + [30] = PCH_GPIO_NATIVE, + [31] = PCH_GPIO_NATIVE, + [32] = PCH_GPIO_NATIVE, + [33] = PCH_GPIO_NATIVE, + [34] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [35] = PCH_GPIO_NATIVE, + [36] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [37] = PCH_GPIO_NATIVE, + [38] = PCH_GPIO_NATIVE, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [40] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [41] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [42] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [43] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [44] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [46] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [47] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [48] = PCH_GPIO_OUT_HIGH, + [49] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [50] = PCH_GPIO_OUT_HIGH, + [51] = PCH_GPIO_OUT_HIGH, + [52] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [53] = PCH_GPIO_OUT_HIGH, + [54] = PCH_GPIO_OUT_HIGH, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .owner = GPIO_OWNER_GPIO, + .irqen = GPIO_IRQ_ENABLE, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = PCH_GPIO_OUT_HIGH, + [57] = PCH_GPIO_OUT_LOW, + [58] = PCH_GPIO_OUT_HIGH, + [59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [60] = PCH_GPIO_OUT_HIGH, + [61] = PCH_GPIO_OUT_LOW, + [62] = PCH_GPIO_NATIVE, + [63] = PCH_GPIO_NATIVE, + [64] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [65] = PCH_GPIO_OUT_LOW, + [66] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [67] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [68] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [69] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [70] = PCH_GPIO_OUT_LOW, + [71] = PCH_GPIO_NATIVE, + [72] = PCH_GPIO_NATIVE, + [73] = PCH_GPIO_NATIVE, + [74] = PCH_GPIO_NATIVE, + [75] = PCH_GPIO_NATIVE, + [76] = PCH_GPIO_NATIVE, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [79] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [80] = PCH_GPIO_OUT_LOW, + [81] = PCH_GPIO_NATIVE, + [82] = PCH_GPIO_OUT_HIGH, + [83] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [84] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [85] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [86] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [87] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [88] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [89] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [90] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [93] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [94] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + PCH_GPIO_END +}; diff --git a/src/mainboard/hp/820g2/hda_verb.c b/src/mainboard/hp/820g2/hda_verb.c new file mode 100644 index 0000000..ed96b9f --- /dev/null +++ b/src/mainboard/hp/820g2/hda_verb.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x00000000, /* Codec Vendor / Device ID: */ + 0x00000000, /* Subsystem ID */ + 13, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0421101f), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x04a11020), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40748605), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/820g2/mainboard.c b/src/mainboard/hp/820g2/mainboard.c new file mode 100644 index 0000000..98cc811 --- /dev/null +++ b/src/mainboard/hp/820g2/mainboard.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/820g2/pei_data.c b/src/mainboard/hp/820g2/pei_data.c new file mode 100644 index 0000000..90c45f6 --- /dev/null +++ b/src/mainboard/hp/820g2/pei_data.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->ec_present = 1; + + /* FIXME: check this */ + pei_data->dimm_channel0_disabled = 2; + pei_data->dimm_channel1_disabled = 2; + pei_data->spd_addresses[0] = 0xa0; + pei_data->spd_addresses[2] = 0xa4; + pei_data->dq_pins_interleaved = 0; + + /* FIXME: USB2 ports */ + pei_data_usb2_port(pei_data, 0, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_DOCK); + pei_data_usb2_port(pei_data, 1, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 2, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 3, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_MINI_PCIE); + pei_data_usb2_port(pei_data, 4, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 5, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + + /* FIXME: USB3 ports */ + pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); +} diff --git a/src/mainboard/hp/820g2/romstage.c b/src/mainboard/hp/820g2/romstage.c new file mode 100644 index 0000000..8fc2f9e --- /dev/null +++ b/src/mainboard/hp/820g2/romstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include <soc/romstage.h> + +void mainboard_pre_raminit(struct romstage_params *rp) +{ + /* Fill out PEI DATA */ + mainboard_fill_pei_data(&rp->pei_data); +} + +void mainboard_post_raminit(struct romstage_params *rp) +{ +}
Attention is currently required from: Martin Roth, Iru Cai. Iru Cai (vimacs) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46630 )
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Set Ready For Review
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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46630
to look at the new patch set (#5).
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
mb/hp: Add EliteBook 820 G2
It can now boot Arch Linux from SATA and USB.
Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai mytbk920423@gmail.com --- A Documentation/mainboard/hp/820g2.md A src/mainboard/hp/820g2/Kconfig A src/mainboard/hp/820g2/Kconfig.name A src/mainboard/hp/820g2/Makefile.inc A src/mainboard/hp/820g2/acpi/ec.asl A src/mainboard/hp/820g2/acpi/platform.asl A src/mainboard/hp/820g2/acpi/superio.asl A src/mainboard/hp/820g2/board_info.txt A src/mainboard/hp/820g2/devicetree.cb A src/mainboard/hp/820g2/dsdt.asl A src/mainboard/hp/820g2/gma-mainboard.ads A src/mainboard/hp/820g2/gpio.c A src/mainboard/hp/820g2/hda_verb.c A src/mainboard/hp/820g2/mainboard.c A src/mainboard/hp/820g2/pei_data.c 15 files changed, 608 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46630/5
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
mb/hp: Add EliteBook 820 G2
It can now boot Arch Linux from SATA and USB.
Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai mytbk920423@gmail.com --- A Documentation/mainboard/hp/820g2.md A src/mainboard/hp/820g2/Kconfig A src/mainboard/hp/820g2/Kconfig.name A src/mainboard/hp/820g2/Makefile.inc A src/mainboard/hp/820g2/acpi/ec.asl A src/mainboard/hp/820g2/acpi/platform.asl A src/mainboard/hp/820g2/acpi/superio.asl A src/mainboard/hp/820g2/board_info.txt A src/mainboard/hp/820g2/devicetree.cb A src/mainboard/hp/820g2/dsdt.asl A src/mainboard/hp/820g2/gma-mainboard.ads A src/mainboard/hp/820g2/gpio.c A src/mainboard/hp/820g2/hda_verb.c A src/mainboard/hp/820g2/mainboard.c A src/mainboard/hp/820g2/pei_data.c 15 files changed, 608 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46630/6
Attention is currently required from: Iru Cai. Hello build bot (Jenkins), Patrick Georgi, Iru Cai,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#7).
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
mb/hp: Add EliteBook 820 G2
Most of the components of this laptop are tested to work.
Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai mytbk920423@gmail.com --- A Documentation/mainboard/hp/elitebook_820_g2.md M Documentation/mainboard/index.md A src/mainboard/hp/elitebook_820_g2/Kconfig A src/mainboard/hp/elitebook_820_g2/Kconfig.name A src/mainboard/hp/elitebook_820_g2/Makefile.inc A src/mainboard/hp/elitebook_820_g2/acpi/ec.asl A src/mainboard/hp/elitebook_820_g2/acpi/platform.asl A src/mainboard/hp/elitebook_820_g2/acpi/superio.asl A src/mainboard/hp/elitebook_820_g2/board_info.txt A src/mainboard/hp/elitebook_820_g2/devicetree.cb A src/mainboard/hp/elitebook_820_g2/dsdt.asl A src/mainboard/hp/elitebook_820_g2/gma-mainboard.ads A src/mainboard/hp/elitebook_820_g2/gpio.c A src/mainboard/hp/elitebook_820_g2/hda_verb.c A src/mainboard/hp/elitebook_820_g2/pei_data.c 15 files changed, 592 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46630/7
Attention is currently required from: Iru Cai, Iru Cai (vimacs). Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46630 )
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 7:
(3 comments)
File Documentation/mainboard/hp/elitebook_820_g2.md:
https://review.coreboot.org/c/coreboot/+/46630/comment/659bcd66_f099b327 PS7, Line 114: Intel GbE (need a modified refcode) Please excuse my ignorance, what does this mean?
https://review.coreboot.org/c/coreboot/+/46630/comment/03aec672_b1a71c24 PS7, Line 114: need needs
https://review.coreboot.org/c/coreboot/+/46630/comment/17deae2e_7ed1669c PS7, Line 128: - Payload: SeaBIOS Please document the version.
Attention is currently required from: Iru Cai, Iru Cai (vimacs). Hello build bot (Jenkins), Patrick Georgi, Iru Cai,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#8).
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
mb/hp: Add EliteBook 820 G2
Most of the components of this laptop are tested to work.
Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai mytbk920423@gmail.com --- A Documentation/mainboard/hp/elitebook_820_g2.md M Documentation/mainboard/index.md A src/mainboard/hp/elitebook_820_g2/Kconfig A src/mainboard/hp/elitebook_820_g2/Kconfig.name A src/mainboard/hp/elitebook_820_g2/Makefile.inc A src/mainboard/hp/elitebook_820_g2/acpi/ec.asl A src/mainboard/hp/elitebook_820_g2/acpi/platform.asl A src/mainboard/hp/elitebook_820_g2/acpi/superio.asl A src/mainboard/hp/elitebook_820_g2/board_info.txt A src/mainboard/hp/elitebook_820_g2/devicetree.cb A src/mainboard/hp/elitebook_820_g2/dsdt.asl A src/mainboard/hp/elitebook_820_g2/gma-mainboard.ads A src/mainboard/hp/elitebook_820_g2/gpio.c A src/mainboard/hp/elitebook_820_g2/hda_verb.c A src/mainboard/hp/elitebook_820_g2/pei_data.c 15 files changed, 599 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46630/8
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Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 8:
(3 comments)
File Documentation/mainboard/hp/elitebook_820_g2.md:
https://review.coreboot.org/c/coreboot/+/46630/comment/dd5cecb0_6c6a8538 PS7, Line 114: Intel GbE (need a modified refcode)
Please excuse my ignorance, what does this mean?
The refcode extracted from the existing coreboot images (I'm using one from Purism Librem) disables Intel GbE, so need a modified one. I've written this in the Broadwell SoC document.
https://review.coreboot.org/c/coreboot/+/46630/comment/4b32059b_705edaaf PS7, Line 114: need
needs
Done
https://review.coreboot.org/c/coreboot/+/46630/comment/6f185405_04807007 PS7, Line 128: - Payload: SeaBIOS
Please document the version.
Done
Attention is currently required from: Paul Menzel, Iru Cai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46630 )
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 8:
(11 comments)
File Documentation/mainboard/hp/elitebook_820_g2.md:
https://review.coreboot.org/c/coreboot/+/46630/comment/55cbeceb_64fa8530 PS8, Line 28: ## Programming Isn't most of this section similar to that of another laptop with Sure Start?
https://review.coreboot.org/c/coreboot/+/46630/comment/357518cd_7f33634c PS8, Line 115: (needs a modified refcode) Is this modification documented anywhere?
https://review.coreboot.org/c/coreboot/+/46630/comment/f8f14e2c_3e2c29d5 PS8, Line 119: - DisplayPort : - VGA How about using a single entry for all video outputs?
- Internal LCD, DisplayPort and VGA video outputs
I assume the internal LCD is working (can't see any mention of it)
File src/mainboard/hp/elitebook_820_g2/Kconfig:
https://review.coreboot.org/c/coreboot/+/46630/comment/9e765cdd_8536a8b3 PS8, Line 24: config VGA_BIOS_FILE : string : default "pci8086,1616.rom" Please remove this. The file doesn't exist in the coreboot tree.
File src/mainboard/hp/elitebook_820_g2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46630/comment/fe99a890_d5076e36 PS8, Line 14: 0x0 nit: 0
https://review.coreboot.org/c/coreboot/+/46630/comment/fed126f6_8ee35231 PS8, Line 20: 0x0 nit: 0
https://review.coreboot.org/c/coreboot/+/46630/comment/b04380b3_44af4f58 PS8, Line 34: register "pcie_port_coalesce" = "1" Is this needed? 1c.0 is on
https://review.coreboot.org/c/coreboot/+/46630/comment/e77e4f13_ebb91f65 PS8, Line 35: register "pcie_port_force_aspm" = "0" : register "sata_devslp_disable" = "0" : register "sata_devslp_mux" = "0" devicetree settings default to zero already, I'd omit these.
https://review.coreboot.org/c/coreboot/+/46630/comment/6195c2dc_f3141da2 PS8, Line 70: SlotDataBusWidth2X out of curiosity, how did you verify this?
https://review.coreboot.org/c/coreboot/+/46630/comment/c342711d_43c639f5 PS8, Line 73: device pci 1e.0 off end # PCI bridge Doesn't exist since Lynx Point, please remove
File src/mainboard/hp/elitebook_820_g2/pei_data.c:
https://review.coreboot.org/c/coreboot/+/46630/comment/bc9e11b1_5c699c4c PS8, Line 22: USB_PORT_BACK_PANEL); Put these on the previous line?
Attention is currently required from: Paul Menzel, Iru Cai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46630 )
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 8:
(2 comments)
File Documentation/mainboard/hp/elitebook_820_g2.md:
https://review.coreboot.org/c/coreboot/+/46630/comment/993362e2_69b810ee PS8, Line 102: - NFC module : - Fingerprint reader : - Smart Card reader : - TPM If you have these devices, do they at least show up in the OS? (e.g. lsusb)
File src/mainboard/hp/elitebook_820_g2/gpio.c:
https://review.coreboot.org/c/coreboot/+/46630/comment/3b4959f6_f1f62105 PS8, Line 6: GPIO_IRQ_LEVEL I'm a bit suspicious of these IRQ level settings without IRQ enable. Maybe these are unused.
GPIO6, GPIO41 and GPIO42 are enabled as GPEs (see devicetree)
Attention is currently required from: Paul Menzel, Iru Cai.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46630 )
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8: Hi, do you still have this board and interested in getting this upstreamed?
Attention is currently required from: Felix Singer, Paul Menzel, Iru Cai.
Iru Cai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46630 )
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
Hi, do you still have this board and interested in getting this upstreamed?
I still have the board, but I don't have much time to do the coreboot things now.
Attention is currently required from: Paul Menzel, Iru Cai.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46630 )
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
I still have the board, but I don't have much time to do the coreboot things now.
Alright. Just let us know when you have time again 😊
Attention is currently required from: Paul Menzel, Iru Cai.
Hello build bot (Jenkins), Iru Cai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46630
to look at the new patch set (#9).
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
mb/hp: Add EliteBook 820 G2
Most of the components of this laptop are tested to work.
Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai mytbk920423@gmail.com --- A Documentation/mainboard/hp/elitebook_820_g2.md M Documentation/mainboard/index.md A src/mainboard/hp/elitebook_820_g2/Kconfig A src/mainboard/hp/elitebook_820_g2/Kconfig.name A src/mainboard/hp/elitebook_820_g2/Makefile.inc A src/mainboard/hp/elitebook_820_g2/acpi/ec.asl A src/mainboard/hp/elitebook_820_g2/acpi/platform.asl A src/mainboard/hp/elitebook_820_g2/acpi/superio.asl A src/mainboard/hp/elitebook_820_g2/board_info.txt A src/mainboard/hp/elitebook_820_g2/devicetree.cb A src/mainboard/hp/elitebook_820_g2/dsdt.asl A src/mainboard/hp/elitebook_820_g2/gma-mainboard.ads A src/mainboard/hp/elitebook_820_g2/gpio.c A src/mainboard/hp/elitebook_820_g2/hda_verb.c A src/mainboard/hp/elitebook_820_g2/pei_data.c 15 files changed, 588 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46630/9
Attention is currently required from: Paul Menzel, Angel Pons, Iru Cai.
Iru Cai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46630 )
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 9:
(12 comments)
Patchset:
PS9: Rebased on current master.
File Documentation/mainboard/hp/elitebook_820_g2.md:
https://review.coreboot.org/c/coreboot/+/46630/comment/086226ac_de945720 PS8, Line 28: ## Programming
Isn't most of this section similar to that of another laptop with Sure Start?
Yes, most of the following is copied from folio_9480m.
https://review.coreboot.org/c/coreboot/+/46630/comment/15bda94a_df504004 PS8, Line 115: (needs a modified refcode)
Is this modification documented anywhere?
No.
https://review.coreboot.org/c/coreboot/+/46630/comment/c35a6767_ac22276d PS8, Line 119: - DisplayPort : - VGA
How about using a single entry for all video outputs? […]
Done
File src/mainboard/hp/elitebook_820_g2/Kconfig:
https://review.coreboot.org/c/coreboot/+/46630/comment/038736fc_34467e63 PS8, Line 24: config VGA_BIOS_FILE : string : default "pci8086,1616.rom"
Please remove this. The file doesn't exist in the coreboot tree.
Done
File src/mainboard/hp/elitebook_820_g2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46630/comment/ddb01bef_d4fbc29b PS8, Line 14: 0x0
nit: 0
Done
https://review.coreboot.org/c/coreboot/+/46630/comment/2725bddf_1720c214 PS8, Line 20: 0x0
nit: 0
Done
https://review.coreboot.org/c/coreboot/+/46630/comment/478d05ef_f234cf91 PS8, Line 34: register "pcie_port_coalesce" = "1"
Is this needed? 1c. […]
Done
https://review.coreboot.org/c/coreboot/+/46630/comment/01ff7ae9_207a0653 PS8, Line 35: register "pcie_port_force_aspm" = "0" : register "sata_devslp_disable" = "0" : register "sata_devslp_mux" = "0"
devicetree settings default to zero already, I'd omit these.
Done
https://review.coreboot.org/c/coreboot/+/46630/comment/62d8f9a6_79b8b4d3 PS8, Line 70: SlotDataBusWidth2X
out of curiosity, how did you verify this?
`lspci -vvv` shows "LnkCap: Port #6, ... Width x2".
https://review.coreboot.org/c/coreboot/+/46630/comment/6d0084ac_c1443fad PS8, Line 73: device pci 1e.0 off end # PCI bridge
Doesn't exist since Lynx Point, please remove
Done
File src/mainboard/hp/elitebook_820_g2/pei_data.c:
https://review.coreboot.org/c/coreboot/+/46630/comment/755eb5ab_9c5d5bcb PS8, Line 22: USB_PORT_BACK_PANEL);
Put these on the previous line?
Done
Attention is currently required from: Paul Menzel, Angel Pons, Iru Cai.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46630 )
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 9:
(2 comments)
File src/mainboard/hp/elitebook_820_g2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46630/comment/514c8d6a_85851e6c PS9, Line 26: register "gen1_dec" = "0x007c0201" : register "gen2_dec" = "0x000c0101" : register "gen4_dec" = "0x000402e9" : register "gpe0_en_1" = "0x40" : register "gpe0_en_2" = "0x600" : register "gpe0_en_4" = "0x46" Same here. Goes to the LPC bridge
https://review.coreboot.org/c/coreboot/+/46630/comment/a54e1543_351c6c89 PS9, Line 33: register "sata_port1_gen3_dtle" = "0x2" : register "sata_port1_gen3_tx" = "0x80" : register "sata_port3_gen3_dtle" = "0x4" : register "sata_port3_gen3_tx" = "0x80" : # SATA (1), M.2 (3) : register "sata_port_map" = "0xa" Please move these into the scope of the SATA controller
Attention is currently required from: Paul Menzel, Angel Pons, Iru Cai.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46630 )
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 9:
(6 comments)
File src/mainboard/hp/elitebook_820_g2/Kconfig:
https://review.coreboot.org/c/coreboot/+/46630/comment/054419ef_45698818 PS9, Line 9: select MAINBOARD_HAS_LIBGFXINIT : select MEMORY_MAPPED_TPM : select MAINBOARD_HAS_TPM1 : select MAINBOARD_USES_IFD_GBE_REGION to keep the alphabetical order:
``` select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_TPM1 select MAINBOARD_USES_IFD_GBE_REGION select MEMORY_MAPPED_TPM ```
https://review.coreboot.org/c/coreboot/+/46630/comment/9bebede8_62485db6 PS9, Line 17: string Remove type, already defined elsewhere.
https://review.coreboot.org/c/coreboot/+/46630/comment/3c9735ba_cc77d9a9 PS9, Line 21: string Remove type, already defined elsewhere.
https://review.coreboot.org/c/coreboot/+/46630/comment/a7adbfaa_1e2d3870 PS9, Line 25: string Remove type, already defined elsewhere.
https://review.coreboot.org/c/coreboot/+/46630/comment/dcd72a00_889f95ad PS9, Line 29: bool Remove type, already defined elsewhere.
https://review.coreboot.org/c/coreboot/+/46630/comment/e86035f7_b329ea16 PS9, Line 33: hex Remove type, already defined elsewhere.
Attention is currently required from: Paul Menzel, Angel Pons, Iru Cai.
Hello build bot (Jenkins), Iru Cai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46630
to look at the new patch set (#10).
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
mb/hp: Add EliteBook 820 G2
Most of the components of this laptop are tested to work.
Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai mytbk920423@gmail.com --- A Documentation/mainboard/hp/elitebook_820_g2.md M Documentation/mainboard/index.md A src/mainboard/hp/elitebook_820_g2/Kconfig A src/mainboard/hp/elitebook_820_g2/Kconfig.name A src/mainboard/hp/elitebook_820_g2/Makefile.inc A src/mainboard/hp/elitebook_820_g2/acpi/ec.asl A src/mainboard/hp/elitebook_820_g2/acpi/platform.asl A src/mainboard/hp/elitebook_820_g2/acpi/superio.asl A src/mainboard/hp/elitebook_820_g2/board_info.txt A src/mainboard/hp/elitebook_820_g2/devicetree.cb A src/mainboard/hp/elitebook_820_g2/dsdt.asl A src/mainboard/hp/elitebook_820_g2/gma-mainboard.ads A src/mainboard/hp/elitebook_820_g2/gpio.c A src/mainboard/hp/elitebook_820_g2/hda_verb.c A src/mainboard/hp/elitebook_820_g2/pei_data.c 15 files changed, 584 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46630/10
Attention is currently required from: Paul Menzel, Angel Pons, Iru Cai.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46630 )
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 10:
(8 comments)
File src/mainboard/hp/elitebook_820_g2/Kconfig:
https://review.coreboot.org/c/coreboot/+/46630/comment/6befc864_3a71090f PS9, Line 9: select MAINBOARD_HAS_LIBGFXINIT : select MEMORY_MAPPED_TPM : select MAINBOARD_HAS_TPM1 : select MAINBOARD_USES_IFD_GBE_REGION
to keep the alphabetical order: […]
Done
https://review.coreboot.org/c/coreboot/+/46630/comment/2426813d_49d71186 PS9, Line 17: string
Remove type, already defined elsewhere.
Done
https://review.coreboot.org/c/coreboot/+/46630/comment/15abe9e2_7d7a02db PS9, Line 21: string
Remove type, already defined elsewhere.
Done
https://review.coreboot.org/c/coreboot/+/46630/comment/5dbe9431_165b05a8 PS9, Line 25: string
Remove type, already defined elsewhere.
Done
https://review.coreboot.org/c/coreboot/+/46630/comment/a30ac078_74135b56 PS9, Line 29: bool
Remove type, already defined elsewhere.
Done
https://review.coreboot.org/c/coreboot/+/46630/comment/4b303c64_0868dbdd PS9, Line 33: hex
Remove type, already defined elsewhere.
Done
File src/mainboard/hp/elitebook_820_g2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46630/comment/13a34025_dea43f9f PS9, Line 26: register "gen1_dec" = "0x007c0201" : register "gen2_dec" = "0x000c0101" : register "gen4_dec" = "0x000402e9" : register "gpe0_en_1" = "0x40" : register "gpe0_en_2" = "0x600" : register "gpe0_en_4" = "0x46"
Same here. […]
Done
https://review.coreboot.org/c/coreboot/+/46630/comment/025ff3ff_c5d6206d PS9, Line 33: register "sata_port1_gen3_dtle" = "0x2" : register "sata_port1_gen3_tx" = "0x80" : register "sata_port3_gen3_dtle" = "0x4" : register "sata_port3_gen3_tx" = "0x80" : # SATA (1), M.2 (3) : register "sata_port_map" = "0xa"
Please move these into the scope of the SATA controller
Done
Attention is currently required from: Paul Menzel, Angel Pons, Iru Cai.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46630 )
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 10:
(1 comment)
File src/mainboard/hp/elitebook_820_g2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46630/comment/0993ce64_6469a9a0 PS10, Line 2: register "gfx" = "GMA_STATIC_DISPLAYS(0)" : register "gpu_dp_b_hotplug" = "4" : register "gpu_dp_c_hotplug" = "4" : register "gpu_dp_d_hotplug" = "0" : register "panel_cfg" = "{ : .up_delay_ms = 200, : .down_delay_ms = 50, : .cycle_delay_ms = 500, : .backlight_on_delay_ms = 1, : .backlight_off_delay_ms = 1, : .backlight_pwm_hz = 200, : }" I missed this somehow. Please move into the graphics controller.
Attention is currently required from: Paul Menzel, Angel Pons, Iru Cai.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46630 )
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 10:
(2 comments)
File Documentation/mainboard/hp/elitebook_820_g2.md:
https://review.coreboot.org/c/coreboot/+/46630/comment/b15da592_1078277e PS8, Line 28: ## Programming
Yes, most of the following is copied from folio_9480m.
Could be reworked later.
https://review.coreboot.org/c/coreboot/+/46630/comment/1b77af0d_646a48f8 PS8, Line 115: (needs a modified refcode)
No.
I think this should be documented.
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Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 10:
(1 comment)
File Documentation/mainboard/hp/elitebook_820_g2.md:
https://review.coreboot.org/c/coreboot/+/46630/comment/1edac682_a0a31d76 PS8, Line 115: (needs a modified refcode)
I think this should be documented.
I wrote it in CB:75418, is this OK to put it on coreboot docs?
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Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 10: Code-Review+1
(5 comments)
File Documentation/mainboard/hp/elitebook_820_g2.md:
https://review.coreboot.org/c/coreboot/+/46630/comment/8c3ed101_e313470d PS8, Line 115: (needs a modified refcode)
I wrote it in CB:75418, is this OK to put it on coreboot docs?
Seems OK. Would be good to add a link here
File src/mainboard/hp/elitebook_820_g2/Kconfig:
https://review.coreboot.org/c/coreboot/+/46630/comment/242d211e_f4cd8a9e PS10, Line 23: default "8086,1616" Did youn test the VGA BIOS? If not, please remove. Besides, it's highly unlikely that this applies to all Elitebook 820 G2 out there: some have an i3 and others have an i7, with the latter having a better iGPU.
File src/mainboard/hp/elitebook_820_g2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46630/comment/2a503230_248616a0 PS10, Line 2: register "gfx" = "GMA_STATIC_DISPLAYS(0)" : register "gpu_dp_b_hotplug" = "4" : register "gpu_dp_c_hotplug" = "4" : register "gpu_dp_d_hotplug" = "0" : register "panel_cfg" = "{ : .up_delay_ms = 200, : .down_delay_ms = 50, : .cycle_delay_ms = 500, : .backlight_on_delay_ms = 1, : .backlight_off_delay_ms = 1, : .backlight_pwm_hz = 200, : }"
I missed this somehow. Please move into the graphics controller.
The other Broadwell boards have gfx stuff at the top of the devicetree, though.
https://review.coreboot.org/c/coreboot/+/46630/comment/c20635ee_ff4bb477 PS10, Line 56: # LPC bridge nit: align with other comments
File src/mainboard/hp/elitebook_820_g2/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/46630/comment/6c01af87_d1eb3763 PS10, Line 28: #include <soc/intel/broadwell/pch/acpi/pch.asl> Don't you need some include for backlight stuff?
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
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Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 10: Code-Review+1
(1 comment)
File Documentation/mainboard/hp/elitebook_820_g2.md:
https://review.coreboot.org/c/coreboot/+/46630/comment/8892dc50_82105d37 : PS8, Line 115: (needs a modified refcode)
Seems OK. […]
Looks also good to me. Thanks!
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#11).
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Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
mb/hp: Add EliteBook 820 G2
Most of the components of this laptop are tested to work.
Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai mytbk920423@gmail.com --- A Documentation/mainboard/hp/elitebook_820_g2.md M Documentation/mainboard/index.md A src/mainboard/hp/elitebook_820_g2/Kconfig A src/mainboard/hp/elitebook_820_g2/Kconfig.name A src/mainboard/hp/elitebook_820_g2/Makefile.inc A src/mainboard/hp/elitebook_820_g2/acpi/ec.asl A src/mainboard/hp/elitebook_820_g2/acpi/platform.asl A src/mainboard/hp/elitebook_820_g2/acpi/superio.asl A src/mainboard/hp/elitebook_820_g2/board_info.txt A src/mainboard/hp/elitebook_820_g2/devicetree.cb A src/mainboard/hp/elitebook_820_g2/dsdt.asl A src/mainboard/hp/elitebook_820_g2/gma-mainboard.ads A src/mainboard/hp/elitebook_820_g2/gpio.c A src/mainboard/hp/elitebook_820_g2/hda_verb.c A src/mainboard/hp/elitebook_820_g2/pei_data.c 15 files changed, 570 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46630/11
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Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 11:
(5 comments)
File Documentation/mainboard/hp/elitebook_820_g2.md:
https://review.coreboot.org/c/coreboot/+/46630/comment/4de187e0_220f04c0 : PS8, Line 115: (needs a modified refcode)
Looks also good to me. […]
Done
File src/mainboard/hp/elitebook_820_g2/Kconfig:
https://review.coreboot.org/c/coreboot/+/46630/comment/22b4cfd3_61077079 : PS10, Line 23: default "8086,1616"
Did youn test the VGA BIOS? If not, please remove. […]
Done
File src/mainboard/hp/elitebook_820_g2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46630/comment/bbbbe71b_8b871fa6 : PS10, Line 2: register "gfx" = "GMA_STATIC_DISPLAYS(0)" : register "gpu_dp_b_hotplug" = "4" : register "gpu_dp_c_hotplug" = "4" : register "gpu_dp_d_hotplug" = "0" : register "panel_cfg" = "{ : .up_delay_ms = 200, : .down_delay_ms = 50, : .cycle_delay_ms = 500, : .backlight_on_delay_ms = 1, : .backlight_off_delay_ms = 1, : .backlight_pwm_hz = 200, : }"
The other Broadwell boards have gfx stuff at the top of the devicetree, though.
Done
https://review.coreboot.org/c/coreboot/+/46630/comment/b7b50507_9080713e : PS10, Line 56: # LPC bridge
nit: align with other comments
Done
File src/mainboard/hp/elitebook_820_g2/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/46630/comment/99a39047_ce09a508 : PS10, Line 28: #include <soc/intel/broadwell/pch/acpi/pch.asl>
Don't you need some include for backlight stuff? […]
Done
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Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 11: Code-Review+1
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Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 11: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/46630/comment/192152d8_b61b994b : PS11, Line 9: Most of the components of this laptop are tested to work. …, cf Documentation.
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Hello Angel Pons, Felix Singer, Iru Cai, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46630?usp=email
to look at the new patch set (#12).
The following approvals got outdated and were removed: Code-Review+1 by Felix Singer, Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins)
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
mb/hp: Add EliteBook 820 G2
Most of the components of this laptop are tested to work, which is listed in the documentation.
Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai mytbk920423@gmail.com --- A Documentation/mainboard/hp/elitebook_820_g2.md A Documentation/mainboard/hp/elitebook_820_g2_flash.jpg M Documentation/mainboard/index.md A src/mainboard/hp/elitebook_820_g2/Kconfig A src/mainboard/hp/elitebook_820_g2/Kconfig.name A src/mainboard/hp/elitebook_820_g2/Makefile.inc A src/mainboard/hp/elitebook_820_g2/acpi/ec.asl A src/mainboard/hp/elitebook_820_g2/acpi/platform.asl A src/mainboard/hp/elitebook_820_g2/acpi/superio.asl A src/mainboard/hp/elitebook_820_g2/board_info.txt A src/mainboard/hp/elitebook_820_g2/data.vbt A src/mainboard/hp/elitebook_820_g2/devicetree.cb A src/mainboard/hp/elitebook_820_g2/dsdt.asl A src/mainboard/hp/elitebook_820_g2/gma-mainboard.ads A src/mainboard/hp/elitebook_820_g2/gpio.c A src/mainboard/hp/elitebook_820_g2/hda_verb.c A src/mainboard/hp/elitebook_820_g2/pei_data.c 17 files changed, 564 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46630/12
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Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 12:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/46630/comment/1909a5d4_72708036 : PS11, Line 9: Most of the components of this laptop are tested to work.
…, cf Documentation.
Done
Patchset:
PS8:
Alright. […]
Done
File Documentation/mainboard/hp/elitebook_820_g2.md:
https://review.coreboot.org/c/coreboot/+/46630/comment/a0ca1666_9ae5e595 : PS8, Line 28: ## Programming
Could be reworked later.
Acknowledged
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Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 13: Code-Review+2
(1 comment)
File src/mainboard/hp/elitebook_820_g2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46630/comment/c0c49623_58fc1fcf : PS13, Line 14: register "gpu_dp_d_hotplug" = "0" nit: Zero by default, can be removed.
Attention is currently required from: Angel Pons, Felix Singer, Iru Cai, Iru Cai, Paul Menzel.
Hello Angel Pons, Felix Singer, Iru Cai, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46630?usp=email
to look at the new patch set (#14).
The following approvals got outdated and were removed: Code-Review+2 by Felix Singer, Verified+1 by build bot (Jenkins)
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
mb/hp: Add EliteBook 820 G2
Most of the components of this laptop are tested to work, which is listed in the documentation.
Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai mytbk920423@gmail.com --- A Documentation/mainboard/hp/elitebook_820_g2.md A Documentation/mainboard/hp/elitebook_820_g2_flash.jpg M Documentation/mainboard/index.md A src/mainboard/hp/elitebook_820_g2/Kconfig A src/mainboard/hp/elitebook_820_g2/Kconfig.name A src/mainboard/hp/elitebook_820_g2/Makefile.inc A src/mainboard/hp/elitebook_820_g2/acpi/ec.asl A src/mainboard/hp/elitebook_820_g2/acpi/platform.asl A src/mainboard/hp/elitebook_820_g2/acpi/superio.asl A src/mainboard/hp/elitebook_820_g2/board_info.txt A src/mainboard/hp/elitebook_820_g2/data.vbt A src/mainboard/hp/elitebook_820_g2/devicetree.cb A src/mainboard/hp/elitebook_820_g2/dsdt.asl A src/mainboard/hp/elitebook_820_g2/gma-mainboard.ads A src/mainboard/hp/elitebook_820_g2/gpio.c A src/mainboard/hp/elitebook_820_g2/hda_verb.c A src/mainboard/hp/elitebook_820_g2/pei_data.c 17 files changed, 571 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46630/14
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Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 14:
(1 comment)
File src/mainboard/hp/elitebook_820_g2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46630/comment/ab929fc8_063c1d0d : PS13, Line 14: register "gpu_dp_d_hotplug" = "0"
nit: Zero by default, can be removed.
Done
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Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 15: Code-Review+1
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Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 15: Code-Review+2
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Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 15: Code-Review+2
Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46630?usp=email )
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
mb/hp: Add EliteBook 820 G2
Most of the components of this laptop are tested to work, which is listed in the documentation.
Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai mytbk920423@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46630 Reviewed-by: Martin L Roth gaumless@gmail.com Reviewed-by: Felix Singer service+coreboot-gerrit@felixsinger.de Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@mailbox.org --- A Documentation/mainboard/hp/elitebook_820_g2.md A Documentation/mainboard/hp/elitebook_820_g2_flash.jpg M Documentation/mainboard/index.md A src/mainboard/hp/elitebook_820_g2/Kconfig A src/mainboard/hp/elitebook_820_g2/Kconfig.name A src/mainboard/hp/elitebook_820_g2/Makefile.inc A src/mainboard/hp/elitebook_820_g2/acpi/ec.asl A src/mainboard/hp/elitebook_820_g2/acpi/platform.asl A src/mainboard/hp/elitebook_820_g2/acpi/superio.asl A src/mainboard/hp/elitebook_820_g2/board_info.txt A src/mainboard/hp/elitebook_820_g2/data.vbt A src/mainboard/hp/elitebook_820_g2/devicetree.cb A src/mainboard/hp/elitebook_820_g2/dsdt.asl A src/mainboard/hp/elitebook_820_g2/gma-mainboard.ads A src/mainboard/hp/elitebook_820_g2/gpio.c A src/mainboard/hp/elitebook_820_g2/hda_verb.c A src/mainboard/hp/elitebook_820_g2/pei_data.c 17 files changed, 571 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved
diff --git a/Documentation/mainboard/hp/elitebook_820_g2.md b/Documentation/mainboard/hp/elitebook_820_g2.md new file mode 100644 index 0000000..5d35c30 --- /dev/null +++ b/Documentation/mainboard/hp/elitebook_820_g2.md @@ -0,0 +1,141 @@ +# HP EliteBook 820 G2 + +This page is about the notebook [HP EliteBook 820 G2]. + +## Release status + +HP EliteBook 820 G2 was released in 2015 and is now end of life. +It can be bought from a secondhand market like Taobao or eBay. + +## Required proprietary blobs + +The following blobs are required to operate the hardware: + +1. EC firmware +2. Intel ME firmware +3. Broadwell mrc.bin and refcode.elf + +HP EliteBook 820 G2 uses SMSC MEC1324 as its embedded controller. +The EC firmware is stored in the flash chip, but we don't need to touch it +or use it in the coreboot build process. + +Intel ME firmware is in the flash chip. It is not needed when building coreboot. + +The Broadwell memory reference code binary and reference code blob is needed +when building coreboot. Read the document [Blobs used in Intel Broadwell boards] +on how to get these blobs. + +## Programming + +Before flashing, remove the battery and the hard drive cover according to the +[Maintenance and Service Guide] of this laptop. + +HP EliteBook 820 G2 has two flash chips, a 16MiB system flash, and a 2MiB +private flash. To install coreboot, we need to program both flash chips. +Read [HP Sure Start] for detailed information. + + + +To access the system flash, we need to connect the AC adapter to the machine, +then clip on the flash chip with an SOIC-8 clip. An [STM32-based flash programmer] +made with an STM32 development board is tested to work. + +To access the private flash chip, we can use a ch341a based flash programmer and +flash the chip with the AC adapter disconnected. + +To flash coreboot on a board running OME firmware, create a backup for both flash +chips, then do the following: + +1. Erase the private flash to disable the IFD protection +2. Modify the IFD to shrink the BIOS region, so that we can put the firmware outside + the protected flash region + +To erase the private flash chip, attach it with the flash programmer via the SOIC-8 clip, +then run: + + flashrom -p <programmer> --erase + +To modify the IFD, write the following flash layout to a file: + + 00000000:00000fff fd + 00001000:00002fff gbe + 00003000:005fffff me + 00600000:00bfffff bios + 00eb5000:00ffffff pd + +Suppose the above layout file is ``layout.txt`` and the origin content of the system flash +is in ``factory-sys.rom``, run: + + ifdtool -n layout.txt factory-sys.rom + +Then a flash image with a new IFD will be in ``factory-sys.rom.new``. + +Flash the IFD of the system flash: + + flashrom -p <programmer> --ifd -i fd -w factory-sys.rom.new + +Then flash the coreboot image: + + # first extend the 12M coreboot.rom to 16M + fallocate -l 16M build/coreboot.rom + flashrom -p <programmer> --ifd -i bios -w build/coreboot.rom + +After coreboot is installed, the coreboot firmware can be updated with internal flashing: + + flashrom -p internal --ifd -i bios --noverify-all -w build/coreboot.rom + +## Debugging + +The board can be debugged with EHCI debug. The EHCI debug port is the USB port on the left. + +## Test status + +### Untested + +- NFC module +- Fingerprint reader +- Smart Card reader + +### Working + +- mainboards with i3-5010U, i5-5300U CPU, 16G+8G DDR3L memory +- SATA and M.2 SATA disk +- PCIe SSD +- Webcam +- Touch screen +- Audio output from speaker and headphone jack +- Intel GbE (needs a modified refcode documented in [Blobs used in Intel Broadwell boards]) +- WLAN +- WWAN +- SD card reader +- Internal LCD, DisplayPort and VGA video outputs +- Dock +- USB +- Keyboard and touchpad +- EC ACPI +- S3 resume +- TPM +- Arch Linux with Linux 5.11.16 +- Broadwell MRC version 2.6.0 Build 0 and refcode from Purism Librem 13 v1 +- Graphics initialization with libgfxinit +- Payload: SeaBIOS 1.16.2 +- EC firmware: KBC Revision 96.54 from OEM firmware version 01.05 +- Internal flashing under coreboot + +## Technology + +```eval_rst ++------------------+-----------------------------+ +| SoC | Intel Broadwell | ++------------------+-----------------------------+ +| EC | SMSC MEC1324 | ++------------------+-----------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+-----------------------------+ +``` + +[HP EliteBook 820 G2]: https://support.hp.com/us-en/product/HP-EliteBook-820-G2-Notebook-PC/7343192... +[Blobs used in Intel Broadwell boards]: ../../soc/intel/broadwell/blobs.md +[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c04775894.pdf +[STM32-based flash programmer]: https://github.com/dword1511/stm32-vserprog +[HP Sure Start]: hp_sure_start.md diff --git a/Documentation/mainboard/hp/elitebook_820_g2_flash.jpg b/Documentation/mainboard/hp/elitebook_820_g2_flash.jpg new file mode 100644 index 0000000..1711527 --- /dev/null +++ b/Documentation/mainboard/hp/elitebook_820_g2_flash.jpg Binary files differ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index f5b4ed8..68532d5 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -85,6 +85,7 @@ - [EliteBook 2560p](hp/2560p.md) - [EliteBook 8760w](hp/8760w.md) - [EliteBook Folio 9480m](hp/folio_9480m.md) +- [EliteBook 820 G2](hp/elitebook_820_g2.md)
## Intel
diff --git a/src/mainboard/hp/elitebook_820_g2/Kconfig b/src/mainboard/hp/elitebook_820_g2/Kconfig new file mode 100644 index 0000000..98aed5c --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/Kconfig @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_HP_ELITEBOOK_820_G2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_12288 + select EC_HP_KBC1126 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_TPM1 + select MAINBOARD_USES_IFD_GBE_REGION + select MEMORY_MAPPED_TPM + select SOC_INTEL_BROADWELL + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + default "hp/elitebook_820_g2" + +config MAINBOARD_PART_NUMBER + default "EliteBook 820 G2" + +config EC_HP_KBC1126_ECFW_IN_CBFS + default n + +config EC_HP_KBC1126_GPE + default 0x6 + +endif diff --git a/src/mainboard/hp/elitebook_820_g2/Kconfig.name b/src/mainboard/hp/elitebook_820_g2/Kconfig.name new file mode 100644 index 0000000..65495f0 --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/Kconfig.name @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_HP_ELITEBOOK_820_G2 + bool "EliteBook 820 G2" diff --git a/src/mainboard/hp/elitebook_820_g2/Makefile.inc b/src/mainboard/hp/elitebook_820_g2/Makefile.inc new file mode 100644 index 0000000..774dbf1 --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/Makefile.inc @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +romstage-y += gpio.c +romstage-y += pei_data.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +ramstage-y += pei_data.c diff --git a/src/mainboard/hp/elitebook_820_g2/acpi/ec.asl b/src/mainboard/hp/elitebook_820_g2/acpi/ec.asl new file mode 100644 index 0000000..baa17a4 --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/hp/kbc1126/acpi/ec.asl> diff --git a/src/mainboard/hp/elitebook_820_g2/acpi/platform.asl b/src/mainboard/hp/elitebook_820_g2/acpi/platform.asl new file mode 100644 index 0000000..8023ae8 --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/acpi/platform.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK,1) +{ + _SB.PCI0.LPCB.EC0.ACPI = 1 + _SB.PCI0.LPCB.EC0.SLPT = 0 + + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + _SB.PCI0.LPCB.EC0.SLPT = Arg0 +} diff --git a/src/mainboard/hp/elitebook_820_g2/acpi/superio.asl b/src/mainboard/hp/elitebook_820_g2/acpi/superio.asl new file mode 100644 index 0000000..55b1db5 --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/hp/elitebook_820_g2/board_info.txt b/src/mainboard/hp/elitebook_820_g2/board_info.txt new file mode 100644 index 0000000..eec3459 --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/HP-EliteBook-820-G2-Notebook-PC/7343192... +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: n +Flashrom support: y +Release year: 2015 diff --git a/src/mainboard/hp/elitebook_820_g2/data.vbt b/src/mainboard/hp/elitebook_820_g2/data.vbt new file mode 100644 index 0000000..563cdba --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/data.vbt Binary files differ diff --git a/src/mainboard/hp/elitebook_820_g2/devicetree.cb b/src/mainboard/hp/elitebook_820_g2/devicetree.cb new file mode 100644 index 0000000..d6cb2ed --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/devicetree.cb @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/broadwell + chip cpu/intel/haswell + device cpu_cluster 0 on ops broadwell_cpu_bus_ops end + end + device domain 0 on + ops broadwell_pci_domain_ops + subsystemid 0x103c 0x225a inherit + + device pci 00.0 on end # Broadwell Host bridge + device pci 02.0 on # Internal graphics VGA controller + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 1, + .backlight_pwm_hz = 200, + }" + end + device pci 03.0 on end # Mini-HD audio + + chip soc/intel/broadwell/pch # Wildcat Point PCH + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # xHCI Controller + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2, Card Reader + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on # PCIe Port #4, WLAN + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + "M.2/E 2230" "SlotDataBusWidth1X" + end + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 on # PCIe Port #6, PCIe SSD + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2242/2260" "SlotDataBusWidth2X" + end + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen4_dec" = "0x000402e9" + register "gpe0_en_1" = "0x40" + register "gpe0_en_2" = "0x600" + register "gpe0_en_4" = "0x46" + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + # This laptop uses MEC1324, but it has the same interface + # as the KBC1126 laptops + chip ec/hp/kbc1126 + register "ec_data_port" = "0x62" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" + register "ec_fan_ctrl_value" = "0x6b" + device pnp ff.1 off end + end + end + device pci 1f.2 on # SATA Controller (AHCI) + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port1_gen3_tx" = "0x80" + register "sata_port3_gen3_dtle" = "0x4" + register "sata_port3_gen3_tx" = "0x80" + # SATA (1), M.2 (3) + register "sata_port_map" = "0xa" + end + device pci 1f.3 on end # SMBus + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/hp/elitebook_820_g2/dsdt.asl b/src/mainboard/hp/elitebook_820_g2/dsdt.asl new file mode 100644 index 0000000..6d7555d --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/dsdt.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + + #include <southbridge/intel/common/acpi/platform.asl> + #include "acpi/platform.asl" + #include <soc/intel/common/acpi/acpi_wake_source.asl> + + #include <soc/intel/broadwell/pch/acpi/globalnvs.asl> + #include <soc/intel/broadwell/acpi/device_nvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <soc/intel/broadwell/pch/acpi/pch.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } +} diff --git a/src/mainboard/hp/elitebook_820_g2/gma-mainboard.ads b/src/mainboard/hp/elitebook_820_g2/gma-mainboard.ads new file mode 100644 index 0000000..3962512 --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- All DisplayPorts + HDMI1, + DP2, -- VGA + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/elitebook_820_g2/gpio.c b/src/mainboard/hp/elitebook_820_g2/gpio.c new file mode 100644 index 0000000..8eb7bfd --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/gpio.c @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/lp_gpio.h> + +const struct pch_lp_gpio_map mainboard_lp_gpio_map[] = { + [0] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [2] = LP_GPIO_OUT_LOW, + [3] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [4] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [5] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [6] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [7] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [8] = LP_GPIO_OUT_HIGH, + [9] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [10] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [11] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [12] = LP_GPIO_NATIVE, + [13] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [14] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [15] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [16] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [17] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [18] = LP_GPIO_OUT_HIGH, + [19] = LP_GPIO_NATIVE, + [20] = LP_GPIO_NATIVE, + [21] = LP_GPIO_NATIVE, + [22] = LP_GPIO_NATIVE, + [23] = LP_GPIO_NATIVE, + [24] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .reset = GPIO_RESET_RSMRST }, + [25] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = LP_GPIO_OUT_HIGH, + [29] = LP_GPIO_OUT_LOW, + [30] = LP_GPIO_NATIVE, + [31] = LP_GPIO_NATIVE, + [32] = LP_GPIO_NATIVE, + [33] = LP_GPIO_NATIVE, + [34] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [35] = LP_GPIO_NATIVE, + [36] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [37] = LP_GPIO_NATIVE, + [38] = LP_GPIO_NATIVE, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [40] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [41] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [42] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [43] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [44] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [46] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [47] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [48] = LP_GPIO_OUT_HIGH, + [49] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [50] = LP_GPIO_OUT_HIGH, + [51] = LP_GPIO_OUT_HIGH, + [52] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [53] = LP_GPIO_OUT_HIGH, + [54] = LP_GPIO_OUT_HIGH, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .owner = GPIO_OWNER_GPIO, .irqen = GPIO_IRQ_ENABLE, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = LP_GPIO_OUT_HIGH, + [57] = LP_GPIO_OUT_LOW, + [58] = LP_GPIO_OUT_HIGH, + [59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [60] = LP_GPIO_OUT_HIGH, + [61] = LP_GPIO_OUT_LOW, + [62] = LP_GPIO_NATIVE, + [63] = LP_GPIO_NATIVE, + [64] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [65] = LP_GPIO_OUT_LOW, + [66] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [67] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [68] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [69] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [70] = LP_GPIO_OUT_LOW, + [71] = LP_GPIO_NATIVE, + [72] = LP_GPIO_NATIVE, + [73] = LP_GPIO_NATIVE, + [74] = LP_GPIO_NATIVE, + [75] = LP_GPIO_NATIVE, + [76] = LP_GPIO_NATIVE, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [79] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [80] = LP_GPIO_OUT_LOW, + [81] = LP_GPIO_NATIVE, + [82] = LP_GPIO_OUT_HIGH, + [83] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [84] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [85] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [86] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [87] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [88] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [89] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [90] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [93] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [94] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + LP_GPIO_END +}; diff --git a/src/mainboard/hp/elitebook_820_g2/hda_verb.c b/src/mainboard/hp/elitebook_820_g2/hda_verb.c new file mode 100644 index 0000000..7199d3f --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/hda_verb.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0280, /* Codec Vendor / Device ID: Realtek */ + 0x103c225a, /* Subsystem ID */ + 57, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(0, 0x103c198f), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0421101f), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x04a11020), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40748605), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + 0x02050007, 0x0204c200, 0x02050063, 0x02044800, + 0x02050066, 0x02040809, 0x02050015, 0x02048842, + 0x0205000f, 0x0204cccc, 0x02050010, 0x0204ccdd, + 0x02050065, 0x02042000, 0x0205001c, 0x0204c900, + 0x02050018, 0x02043788, 0x02050008, 0x02048210, + 0x02050068, 0x02043022, 0x02050006, 0x02040800, + 0x02050061, 0x02040403, 0x02050061, 0x02040403, + 0x0205005f, 0x02040800, 0x02050060, 0x02040800, + 0x0205002c, 0x02044002, 0x0205002e, 0x02041ec4, + 0x0205002f, 0x02040000, 0x02050033, 0x0204c5e8, + 0x02050034, 0x02041a98, 0x02050035, 0x0204f5ad, + 0x02050036, 0x0204cbd2, 0x02050037, 0x02041605, + 0x02050038, 0x0204f5ad, 0x02050039, 0x0204ea5f, + 0x0205003a, 0x02040b42, 0x0205003b, 0x0204fb54, + 0x0205003c, 0x0204fcd9, 0x0205003d, 0x02040000, + 0x02050030, 0x02041f5c, 0x02050031, 0x02040111, + 0x02050032, 0x02041f5f, 0x0205003e, 0x02041ea9, + 0x0205002f, 0x02040000, 0x02050042, 0x0204c66e, + 0x02050043, 0x02041a29, 0x02050035, 0x0204f5ad, + 0x02050044, 0x0204ccdd, 0x02050045, 0x02041549, + 0x02050038, 0x0204f5ad, 0x02050046, 0x0204ee79, + 0x02050047, 0x020409f4, 0x0205003b, 0x0204fb54, + 0x02050048, 0x0204fa4c, 0x0205003d, 0x02040000, + 0x0205003f, 0x02041f4d, 0x02050040, 0x02040129, + 0x02050041, 0x02041f51, 0x02050049, 0x02041f61, + 0x0205002f, 0x02040000, 0x0205004d, 0x0204c2f4, + 0x0205004e, 0x02041d2e, 0x02050035, 0x0204f5ad, + 0x0205004f, 0x0204c5e8, 0x02050050, 0x02041a98, + 0x02050038, 0x0204f5ad, 0x02050051, 0x0204d30e, + 0x02050052, 0x020413e6, 0x0205003b, 0x0204fb54, + 0x02050053, 0x02040b73, 0x0205003d, 0x02040000, + 0x0205004a, 0x02041faf, 0x0205004b, 0x0204008a, + 0x0205004c, 0x02041fb0, 0x02050054, 0x02041fb0, + 0x0205002f, 0x02040000, 0x02050058, 0x0204c17a, + 0x02050059, 0x02041e8f, 0x02050035, 0x0204f5ad, + 0x0205005a, 0x0204c2f4, 0x0205005b, 0x02041d2e, + 0x02050038, 0x0204f5ad, 0x0205005c, 0x0204c899, + 0x0205005d, 0x0204195b, 0x0205003b, 0x0204fb54, + 0x0205005e, 0x02041444, 0x0205003d, 0x02040000, + 0x02050055, 0x02041fd8, 0x02050056, 0x02040045, + 0x02050057, 0x02041fd8, 0x0205002c, 0x0204ffc2, + 0x02050026, 0x02042828, 0x02050029, 0x02040250, + 0x02050004, 0x0204c09e, 0x0205000e, 0x02045001, +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/elitebook_820_g2/pei_data.c b/src/mainboard/hp/elitebook_820_g2/pei_data.c new file mode 100644 index 0000000..a31f211 --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/pei_data.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[2] = 0x52; +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->ec_present = 1; + + /* P1 */ + pei_data_usb2_port(pei_data, 0, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + /* P2: left side port, USB debug */ + pei_data_usb2_port(pei_data, 1, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + /* P3: digitizer and right side ports (Microchip hub) */ + pei_data_usb2_port(pei_data, 2, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + /* P4: WLAN */ + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + /* P5: fingerprint reader */ + pei_data_usb2_port(pei_data, 4, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + /* P6: WWAN */ + pei_data_usb2_port(pei_data, 5, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + /* P7: webcam */ + pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + /* P8 */ + pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + + /* P1 */ + pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0); + /* P2: left side, USB debug */ + pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0); + /* P3: right side (Microchip hub) */ + pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); + /* P4 */ + pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); +}
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46630?usp=email )
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 16:
Automatic boot test returned (PASS/FAIL/TOTAL): 6 / 9 / 15
FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176899 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176897 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/176896 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/176895 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/176894 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176893 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/176892 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/176891 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/176889 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/176888 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/176887 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176886 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/176885 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/176884 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/176883
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
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Felix Singer (Code Review)
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Iru Cai (Code Review)
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Iru Cai (vimacs) (Code Review)
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Martin L Roth (Code Review)
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Paul Menzel (Code Review)