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Change in coreboot[master]: sb/intel/common: Move named packages out of method
by Patrick Georgi (Code Review) 12 Feb '21

12 Feb '21

Attention is currently required from: Patrick Rudolph. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50475 ) Change subject: sb/intel/common: Move named packages out of method ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabfb20dcb3f655658844d99ab7a3b479684d9d19 Gerrit-Change-Number: 50475 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 12 Feb 2021 07:54:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/common/fixed_bars.h: Add casts to `uintptr_t`
by Patrick Georgi (Code Review) 12 Feb '21

12 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50469 ) Change subject: nb/intel/common/fixed_bars.h: Add casts to `uintptr_t` ...................................................................... nb/intel/common/fixed_bars.h: Add casts to `uintptr_t` 64-bit builds need this, as the Kconfig values fit in a 32-bit integer. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I570374f92394f839a97e28fabc8fa07a7e673e83 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50469 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/northbridge/intel/common/fixed_bars.h 1 file changed, 9 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved HAOUAS Elyes: Looks good to me, approved Patrick Rudolph: Looks good to me, approved diff --git a/src/northbridge/intel/common/fixed_bars.h b/src/northbridge/intel/common/fixed_bars.h index d1b005b..e149d22 100644 --- a/src/northbridge/intel/common/fixed_bars.h +++ b/src/northbridge/intel/common/fixed_bars.h @@ -9,16 +9,16 @@ #include <stdint.h> -#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_FIXED_MCHBAR_MMIO_BASE + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_FIXED_MCHBAR_MMIO_BASE + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_FIXED_MCHBAR_MMIO_BASE + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)((uintptr_t)CONFIG_FIXED_MCHBAR_MMIO_BASE + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)((uintptr_t)CONFIG_FIXED_MCHBAR_MMIO_BASE + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)((uintptr_t)CONFIG_FIXED_MCHBAR_MMIO_BASE + (x)))) -#define DMIBAR8(x) (*((volatile u8 *)(CONFIG_FIXED_DMIBAR_MMIO_BASE + (x)))) -#define DMIBAR16(x) (*((volatile u16 *)(CONFIG_FIXED_DMIBAR_MMIO_BASE + (x)))) -#define DMIBAR32(x) (*((volatile u32 *)(CONFIG_FIXED_DMIBAR_MMIO_BASE + (x)))) +#define DMIBAR8(x) (*((volatile u8 *)((uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE + (x)))) +#define DMIBAR16(x) (*((volatile u16 *)((uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE + (x)))) +#define DMIBAR32(x) (*((volatile u32 *)((uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE + (x)))) -#define EPBAR8(x) (*((volatile u8 *)(CONFIG_FIXED_EPBAR_MMIO_BASE + (x)))) -#define EPBAR16(x) (*((volatile u16 *)(CONFIG_FIXED_EPBAR_MMIO_BASE + (x)))) -#define EPBAR32(x) (*((volatile u32 *)(CONFIG_FIXED_EPBAR_MMIO_BASE + (x)))) +#define EPBAR8(x) (*((volatile u8 *)((uintptr_t)CONFIG_FIXED_EPBAR_MMIO_BASE + (x)))) +#define EPBAR16(x) (*((volatile u16 *)((uintptr_t)CONFIG_FIXED_EPBAR_MMIO_BASE + (x)))) +#define EPBAR32(x) (*((volatile u32 *)((uintptr_t)CONFIG_FIXED_EPBAR_MMIO_BASE + (x)))) #endif /* ! NORTHBRIDGE_INTEL_COMMON_FIXED_BARS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I570374f92394f839a97e28fabc8fa07a7e673e83 Gerrit-Change-Number: 50469 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors
by Patrick Georgi (Code Review) 12 Feb '21

12 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49749 ) Change subject: nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors ...................................................................... nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I3ff4577ce662697cb3d8fb34003217fd6275dd42 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49749 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/haswell/acpi/ctdp.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/memmap.h M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/romstage.c 8 files changed, 29 insertions(+), 31 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved HAOUAS Elyes: Looks good to me, approved diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index dcc9162..e3f9aec 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -108,4 +108,13 @@ This probably only happens when the DRAM gets hot, but what MRC exactly does when this setting is enabled has not been investigated. +config FIXED_MCHBAR_MMIO_BASE + default 0xfed10000 + +config FIXED_DMIBAR_MMIO_BASE + default 0xfed18000 + +config FIXED_EPBAR_MMIO_BASE + default 0xfed19000 + endif diff --git a/src/northbridge/intel/haswell/acpi/ctdp.asl b/src/northbridge/intel/haswell/acpi/ctdp.asl index 47b7940..565b2d2 100644 --- a/src/northbridge/intel/haswell/acpi/ctdp.asl +++ b/src/northbridge/intel/haswell/acpi/ctdp.asl @@ -9,7 +9,7 @@ Name (CTCU, 2) /* CTDP Up Select */ Name (SPL1, 0) /* Saved PL1 value */ - OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR + 0x5000, 0x1000) + OperationRegion (MCHB, SystemMemory, CONFIG_FIXED_MCHBAR_MMIO_BASE + 0x5000, 0x1000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x930), /* PACKAGE_POWER_SKU */ diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 1ff2826..bc1a1c8 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -175,9 +175,9 @@ Name (PDRS, ResourceTemplate () { Memory32Fixed (ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) - Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000) - Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000) - Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000) + Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00008000) + Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) + Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index a0e4211..f81ff9f 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -14,12 +14,12 @@ { printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); - pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); - pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); + pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, EPBAR + 4, 0); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, 0); + pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR + 4, 0); /* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(HOST_BRIDGE, PAM0, 0x30); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index f6678ca..f158c21 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -34,9 +34,8 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#include <northbridge/intel/common/fixed_bars.h> + #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) @@ -62,10 +61,7 @@ * EPBAR - Egress Port Root Complex Register Block */ -#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + (x))) -#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + (x))) -#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + (x))) -#define EPBAR64(x) *((volatile u64 *)(DEFAULT_EPBAR + (x))) +#define EPBAR64(x) (*((volatile u64 *)((uintptr_t)CONFIG_FIXED_EPBAR_MMIO_BASE + (x)))) #include "registers/epbar.h" @@ -73,10 +69,7 @@ * DMIBAR */ -#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + (x))) -#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + (x))) -#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + (x))) -#define DMIBAR64(x) *((volatile u64 *)(DEFAULT_DMIBAR + (x))) +#define DMIBAR64(x) (*((volatile u64 *)((uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE + (x)))) #include "registers/dmibar.h" diff --git a/src/northbridge/intel/haswell/memmap.h b/src/northbridge/intel/haswell/memmap.h index 0ff7b52..02bdecc 100644 --- a/src/northbridge/intel/haswell/memmap.h +++ b/src/northbridge/intel/haswell/memmap.h @@ -3,10 +3,6 @@ #ifndef __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__ #define __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__ -#define DEFAULT_MCHBAR 0xfed10000 -#define DEFAULT_DMIBAR 0xfed18000 -#define DEFAULT_EPBAR 0xfed19000 - #define GFXVT_BASE_ADDRESS 0xfed90000ULL #define GFXVT_BASE_SIZE 0x1000 diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index c2c8143..61ad236 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -477,7 +477,7 @@ reg32 &= ~(0xff << 16); reg32 |= 1 | (1 << 16); EPBAR32(EPLE1D) = reg32; - EPBAR64(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; + EPBAR64(EPLE1A) = CONFIG_FIXED_DMIBAR_MMIO_BASE; for (unsigned int i = 0; i <= 2; i++) { const struct device *const dev = pcidev_on_root(1, i); @@ -493,7 +493,7 @@ EPBAR32(eple_d[i]) = reg32; pci_update_config32(dev, PEG_ESD, ~(0xff << 16), (1 << 16)); - pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); + pci_write_config32(dev, PEG_LE1A, CONFIG_FIXED_EPBAR_MMIO_BASE); pci_write_config32(dev, PEG_LE1A + 4, 0); pci_update_config32(dev, PEG_LE1D, ~(0xff << 16), (1 << 16) | 1); @@ -513,7 +513,7 @@ DMIBAR32(DMILE1D) = reg32; DMIBAR64(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE; - DMIBAR64(DMILE2A) = (uintptr_t)DEFAULT_EPBAR; + DMIBAR64(DMILE2A) = CONFIG_FIXED_EPBAR_MMIO_BASE; reg32 = DMIBAR32(DMILE2D); reg32 &= ~(0xff << 16); reg32 |= 1 | (1 << 16); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index f5d500b2..cbb9834 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -50,9 +50,9 @@ struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, + .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, + .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, + .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .hpet_address = HPET_ADDR, -- To view, visit https://review.coreboot.org/c/coreboot/+/49749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ff4577ce662697cb3d8fb34003217fd6275dd42 Gerrit-Change-Number: 49749 Gerrit-PatchSet: 8 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sandybridge MRC boards: Drop channel disable masks
by Patrick Georgi (Code Review) 12 Feb '21

12 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49751 ) Change subject: sandybridge MRC boards: Drop channel disable masks ...................................................................... sandybridge MRC boards: Drop channel disable masks Platform code will overwrite these values anyway, so do not program them in mainboards. Change-Id: I7571d336a1402c6cfae5835a95dc706a28106271 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49751 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/asus/p8z77-m_pro/early_init.c M src/mainboard/google/butterfly/early_init.c M src/mainboard/google/link/early_init.c M src/mainboard/google/parrot/early_init.c M src/mainboard/google/stout/early_init.c M src/mainboard/intel/dcp847ske/romstage.c M src/mainboard/intel/emeraldlake2/early_init.c M src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/lenovo/x220/early_init.c M src/mainboard/roda/rv11/variants/rv11/early_init.c M src/mainboard/roda/rv11/variants/rw11/early_init.c M src/mainboard/samsung/lumpy/early_init.c M src/mainboard/samsung/stumpy/early_init.c 13 files changed, 0 insertions(+), 76 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index eadf0a9..4e41d01 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -103,8 +103,6 @@ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 0, /* Asus 2203 BIOS shows XUECA016, but no EC */ .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */ - .dimm_channel0_disabled = 0, /* Both DIMM enabled */ - .dimm_channel1_disabled = 0, /* Both DIMM enabled */ .max_ddr3_freq = 1600, /* 1333=Sandy; 1600=Ivy */ .usb_port_config = { /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */ diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index d213f7d..ba30016 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -94,12 +94,6 @@ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, .ddr3lv_support = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { /* enabled USB oc pin length */ diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index 4f710c6..088d538 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -102,12 +102,6 @@ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, .ddr3lv_support = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index ab8a23f..a11dc91 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -71,12 +71,6 @@ .spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index 84ca487..6b28e00 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -108,12 +108,6 @@ .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { /* enabled USB oc pin length */ diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index d52ea3c..df8112c 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -32,12 +32,6 @@ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 0, .gbe_enable = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, .max_ddr3_freq = 1333, .usb_port_config = { #define USB_CONFIG(enabled, current, ocpin) { enabled, ocpin, 0x040 * current } diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index e7cd7f9..aa481dc 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -68,12 +68,6 @@ .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { { 1, 0, 0x0040 }, /* P0: Front port (OC0) */ diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index fac3da9..55902db 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -75,14 +75,6 @@ .ec_present = 1, .gbe_enable = 1, .ddr3lv_support = 0, - /* - * 0 = leave channel enabled - * 1 = disable dimm 0 on channel - * 2 = disable dimm 1 on channel - * 3 = disable dimm 0+1 on channel - */ - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { /* enabled USB oc pin length */ diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index eb5bb6e..07a5dbd 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -30,12 +30,6 @@ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, .gbe_enable = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, .max_ddr3_freq = 1333, .usb_port_config = { { 1, 0, 0x0040 }, diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c index ce3b0c6..37de919 100644 --- a/src/mainboard/roda/rv11/variants/rv11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -29,12 +29,6 @@ .ec_present = 1, .gbe_enable = 1, .ddr3lv_support = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { /* Enabled / OC PIN / Length */ diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index 9455987..c18318d 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -59,12 +59,6 @@ .ec_present = 1, .gbe_enable = 1, .ddr3lv_support = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 0, - .dimm_channel1_disabled = 0, .max_ddr3_freq = 1600, .usb_port_config = { /* Enabled / OC PIN / Length */ diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 276a2c1..3d4ad80 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -133,12 +133,6 @@ .spd_addresses = { 0xa0, 0x00,0x00,0x00 }, .ts_addresses = { 0x30, 0x00, 0x00, 0x00 }, .ec_present = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, .max_ddr3_freq = 1333, .usb_port_config = { { 1, 0, 0x0080 }, /* P0: Port 0 (OC0) */ diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index 858313f..d18da56 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -118,12 +118,6 @@ .spd_addresses = { 0xa0, 0x00,0xa4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, .max_ddr3_freq = 1333, .usb_port_config = { { 1, 0, 0x0080 }, /* P0: Front port (OC0) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/49751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7571d336a1402c6cfae5835a95dc706a28106271 Gerrit-Change-Number: 49751 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/broadwell: Use southbridge common RCBA
by Patrick Georgi (Code Review) 12 Feb '21

12 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50041 ) Change subject: soc/intel/broadwell: Use southbridge common RCBA ...................................................................... soc/intel/broadwell: Use southbridge common RCBA Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I94953bed3f331848271464bee829f8209167f150 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50041 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/broadwell/acpi/hostbridge.asl M src/soc/intel/broadwell/include/soc/iomap.h M src/soc/intel/broadwell/include/soc/rcba.h M src/soc/intel/broadwell/pch/acpi/pch.asl M src/soc/intel/broadwell/pch/bootblock.c M src/soc/intel/broadwell/pch/lpc.c 6 files changed, 8 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/broadwell/acpi/hostbridge.asl b/src/soc/intel/broadwell/acpi/hostbridge.asl index e36fa47..3ba5046 100644 --- a/src/soc/intel/broadwell/acpi/hostbridge.asl +++ b/src/soc/intel/broadwell/acpi/hostbridge.asl @@ -174,7 +174,7 @@ Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed (ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) + Memory32Fixed (ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, MCH_BASE_SIZE) Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, DMI_BASE_SIZE) Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, EP_BASE_SIZE) diff --git a/src/soc/intel/broadwell/include/soc/iomap.h b/src/soc/intel/broadwell/include/soc/iomap.h index 61e53fc..4b4e3d9 100644 --- a/src/soc/intel/broadwell/include/soc/iomap.h +++ b/src/soc/intel/broadwell/include/soc/iomap.h @@ -15,9 +15,6 @@ #define GDXC_BASE_ADDRESS 0xfed84000 #define GDXC_BASE_SIZE 0x1000 -#define RCBA_BASE_ADDRESS 0xfed1c000 -#define RCBA_BASE_SIZE 0x4000 - #define HPET_BASE_ADDRESS 0xfed00000 #define GFXVT_BASE_ADDRESS 0xfed90000ULL diff --git a/src/soc/intel/broadwell/include/soc/rcba.h b/src/soc/intel/broadwell/include/soc/rcba.h index 0c63eb2..2649e9c 100644 --- a/src/soc/intel/broadwell/include/soc/rcba.h +++ b/src/soc/intel/broadwell/include/soc/rcba.h @@ -3,18 +3,7 @@ #ifndef _BROADWELL_RCBA_H_ #define _BROADWELL_RCBA_H_ -#include <soc/iomap.h> - -#define RCBA8(x) *((volatile u8 *)(RCBA_BASE_ADDRESS + x)) -#define RCBA16(x) *((volatile u16 *)(RCBA_BASE_ADDRESS + x)) -#define RCBA32(x) *((volatile u32 *)(RCBA_BASE_ADDRESS + x)) - -#define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) -#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) -#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) -#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) -#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) +#include <southbridge/intel/common/rcba.h> #define RPC 0x0400 /* 32bit */ #define RPFN 0x0404 /* 32bit */ diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl index b7d6838..0e90c95 100644 --- a/src/soc/intel/broadwell/pch/acpi/pch.asl +++ b/src/soc/intel/broadwell/pch/acpi/pch.asl @@ -13,7 +13,7 @@ } // Root Complex Register Block - OperationRegion (RCRB, SystemMemory, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) + OperationRegion (RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Field (RCRB, DWordAcc, Lock, Preserve) { Offset (0x3404), // High Performance Timer Configuration diff --git a/src/soc/intel/broadwell/pch/bootblock.c b/src/soc/intel/broadwell/pch/bootblock.c index 7f6d0d5..d00a431 100644 --- a/src/soc/intel/broadwell/pch/bootblock.c +++ b/src/soc/intel/broadwell/pch/bootblock.c @@ -13,7 +13,7 @@ static void map_rcba(void) { - pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1); + pci_write_config32(PCH_DEV_LPC, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); } static void enable_port80_on_lpc(void) @@ -48,7 +48,7 @@ static void pch_enable_bars(void) { /* Set up southbridge BARs */ - pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1); + pci_write_config32(PCH_DEV_LPC, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); pci_write_config32(PCH_DEV_LPC, PMBASE, ACPI_BASE_ADDRESS | 1); diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 84b8d00..873e57e 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -491,10 +491,10 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* RCBA */ - if (default_decode_base > RCBA_BASE_ADDRESS) { + if (default_decode_base > CONFIG_FIXED_RCBA_MMIO_BASE) { res = new_resource(dev, RCBA); - res->base = RCBA_BASE_ADDRESS; - res->size = 16 * 1024; + res->base = CONFIG_FIXED_RCBA_MMIO_BASE; + res->size = CONFIG_RCBA_LENGTH; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE; } -- To view, visit https://review.coreboot.org/c/coreboot/+/50041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94953bed3f331848271464bee829f8209167f150 Gerrit-Change-Number: 50041 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/superiotool: Add ITE IT8616E/IT8656E support
by Patrick Georgi (Code Review) 12 Feb '21

12 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50457 ) Change subject: util/superiotool: Add ITE IT8616E/IT8656E support ...................................................................... util/superiotool: Add ITE IT8616E/IT8656E support Datasheet is not publicly available. Derive which registers to dump from IT8625E, since there are mainboards that can use either chip depending on BOM configuration. Default values are taken from an HP 280 G2 running a coreboot build that does not configure the Super I/O. Change-Id: Icc8c56e9cd19e940e85176ac51b8ef978275eb71 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50457 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M util/superiotool/ite.c 1 file changed, 38 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index 074d320..9b29ceb 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -402,6 +402,44 @@ {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x10,0x0b,0x06,EOT}}, {EOT}}}, + {0x8616, "IT8616E/IT8656E", { + /* Derived from IT8625E, defaults dumped from hardware */ + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,EOT}, + {0x86,0x16,MISC,0x40,0x00,EOT}}, + {0x3, "Parallel port (unusable)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x72,0x73,0x74,0xf0,EOT}, + {0x00,0x03,0x78,0x07,0x78,0x07,0x02,0x00,0x00,0x04,0x0b,EOT}}, + {0x4, "Environment controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xf9,0xfa,0xfb,0xfc,0xfd,EOT}, + {0x00,0x02,0x90,0x02,0x30,0x09,0x00,0x00,0x00, + 0x00,0xe0,0x00,NANA,0x48,0x00,0x00,0x00,0x40,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT}, + {0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x48,EOT}}, + {0x6, "Mouse", + {0x30,0x70,0x71,0xf0,EOT}, + {0x00,0x0c,0x02,0x00,EOT}}, + {0x7, "GPIO", + {0x25,0x26,0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x60, + 0x61,0x62,0x63,0x70,0x71,0x72,0x73,0x74,0xb0,0xb1, + 0xb2,0xb3,0xb4,0xb5,0xb8,0xba,0xbb,0xbc,0xbd,0xc0, + 0xc1,0xc2,0xc3,0xc4,0xc8,0xc9,0xca,0xcb,0xcc,0xcd, + 0xce,0xcf,0xd0,0xd1,0xd2,0xd3,0xd4,0xd5,0xd6,0xd7, + 0xd8,0xd9,0xe0,0xe1,0xe2,0xe3,0xe4,0xec,0xf0,0xf1, + 0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,EOT}, + {0x00,0xf3,0x00,0x00,0x00,0x01,0x48,0x01,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,MISC,0x38,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x03,0x01, + 0x00,0x00,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x17,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x0e,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0xa, "Consumer IR", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x03,0x10,0x0b,0x06,EOT}}, + {EOT}}}, {0x8623, "IT8623E", { /* Defaults are not specified as no datasheet available */ {NOLDN, NULL, -- To view, visit https://review.coreboot.org/c/coreboot/+/50457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc8c56e9cd19e940e85176ac51b8ef978275eb71 Gerrit-Change-Number: 50457 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/superiotool: Add ITE IT8625E support
by Patrick Georgi (Code Review) 12 Feb '21

12 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50456 ) Change subject: util/superiotool: Add ITE IT8625E support ...................................................................... util/superiotool: Add ITE IT8625E support Values as per "IT8625E Preliminary Specification V0.3 (For D Version)". Change-Id: Ic3ff13d93f66d09a1f2ea953736336b201a7114c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50456 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M util/superiotool/ite.c 1 file changed, 43 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index 6e604a0..074d320 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -446,6 +446,49 @@ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, NANA,NANA,NANA,NANA,NANA,EOT}}, {EOT}}}, + {0x8625, "IT8625E", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,EOT}, + {0x86,0x25,MISC,0x40,0x00,EOT}}, + {0x1, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x03,0xf8,0x04,0x00,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x02,0xf8,0x03,0x00,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x62,0x63,0x70,0x74,0xf0,EOT}, + {0x00,0x03,0x78,0x07,0x78,0x07,0x03,0x0b,EOT}}, + {0x4, "Environment controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xf9,0xfa,0xfb,0xfc,0xfd,EOT}, + {0x00,0x02,0x90,0x02,0x30,0x09,0x00,0x00,0x00, + 0x00,0x00,0x00,NANA,0x48,0x00,0x00,0x00,0x40,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT}, + {0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x48,EOT}}, + {0x6, "Mouse", + {0x30,0x70,0x71,0xf0,EOT}, + {0x00,0x0c,0x02,0x00,EOT}}, + {0x7, "GPIO", + {0x25,0x26,0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x60, + 0x61,0x62,0x63,0x70,0x71,0x72,0x73,0x74,0xb0,0xb1, + 0xb2,0xb3,0xb4,0xb5,0xb8,0xba,0xbb,0xbc,0xbd,0xc0, + 0xc1,0xc2,0xc3,0xc4,0xc8,0xc9,0xca,0xcb,0xcc,0xcd, + 0xce,0xcf,0xd0,0xd1,0xd2,0xd3,0xd4,0xd5,0xd6,0xd7, + 0xd8,0xd9,0xe0,0xe1,0xe2,0xe3,0xe4,0xec,0xf0,0xf1, + 0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,EOT}, + {0x00,0xf3,0x00,0x00,0x00,0x00,0x48,0x01,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,MISC,0x38,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01, + 0x00,0x00,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x0f,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x0e,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0xa, "Consumer IR", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x03,0x10,0x0b,0x06,EOT}}, + {EOT}}}, {0x8661, "IT8661F/IT8770F", { {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x20,0x21,0x22, -- To view, visit https://review.coreboot.org/c/coreboot/+/50456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3ff13d93f66d09a1f2ea953736336b201a7114c Gerrit-Change-Number: 50456 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/razer/blade_stealth_kbl: Configure IRQs as level triggered for HID...
by Patrick Georgi (Code Review) 12 Feb '21

12 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50453 ) Change subject: mb/razer/blade_stealth_kbl: Configure IRQs as level triggered for HID over I2C ...................................................................... mb/razer/blade_stealth_kbl: Configure IRQs as level triggered for HID over I2C As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3… BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ifdc3f061d919c8db9001c7a4cc26eb21117958d7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50453 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/razer/blade_stealth_kbl/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 44b3523..a358fb8 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -191,7 +191,7 @@ chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end -- To view, visit https://review.coreboot.org/c/coreboot/+/50453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdc3f061d919c8db9001c7a4cc26eb21117958d7 Gerrit-Change-Number: 50453 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/system76/lemp9: Configure IRQs as level triggered for HID over I2C
by Patrick Georgi (Code Review) 12 Feb '21

12 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50452 ) Change subject: mb/system76/lemp9: Configure IRQs as level triggered for HID over I2C ...................................................................... mb/system76/lemp9: Configure IRQs as level triggered for HID over I2C As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3… BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ice096777077bd2e9cfbaf744371fc372c0c05606 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50452 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/system76/lemp9/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 3a0758a..263036d 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -97,7 +97,7 @@ chip drivers/i2c/hid register "generic.hid" = ""ELAN040D"" register "generic.desc" = ""ELAN Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 15 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/50452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice096777077bd2e9cfbaf744371fc372c0c05606 Gerrit-Change-Number: 50452 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: tests: Add lib/stack-test test case
by Patrick Georgi (Code Review) 12 Feb '21

12 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50305 ) Change subject: tests: Add lib/stack-test test case ...................................................................... tests: Add lib/stack-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Icf0cceac290618a50ecc4e65f1f9551dbf31bd32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50305 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> --- M tests/lib/Makefile.inc A tests/lib/stack-test.c 2 files changed, 138 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Fagerburg: Looks good to me, approved diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index ccc6596..2c80b93 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -13,6 +13,7 @@ tests-y += imd_cbmem-romstage-test tests-y += imd_cbmem-ramstage-test tests-y += region_file-test +tests-y += stack-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -71,3 +72,7 @@ region_file-test-srcs += tests/lib/region_file-test.c region_file-test-srcs += src/commonlib/region.c region_file-test-srcs += tests/stubs/console.c + +stack-test-srcs += tests/lib/stack-test.c +stack-test-srcs += src/lib/stack.c +stack-test-srcs += tests/stubs/console.c diff --git a/tests/lib/stack-test.c b/tests/lib/stack-test.c new file mode 100644 index 0000000..f494c08 --- /dev/null +++ b/tests/lib/stack-test.c @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <tests/test.h> +#include <lib.h> +#include <symbols.h> + + +#if CONFIG_STACK_SIZE == 0 +# define STACK_SIZE 0x1000 +#else +# define STACK_SIZE CONFIG_STACK_SIZE +#endif + +/* Value used for stack initialization. Change if implementation changes. */ +#define STACK_GUARD_VALUE 0xDEADBEEF + +__weak extern u8 _stack[]; +__weak extern u8 _estack[]; +TEST_REGION(stack, STACK_SIZE); + + +static void fill_stack(u32 value) +{ + u32 *stack = (u32 *)_stack; + for (size_t i = 0; i < STACK_SIZE / sizeof(u32); ++i) + stack[i] = value; +} + +/* Fill stack region with guard value. */ +static void clean_stack(void) +{ + fill_stack(STACK_GUARD_VALUE); +} + +static int setup_stack_test(void **state) +{ + void *top_of_stack = _stack + sizeof(_stack); + + clean_stack(); + *state = top_of_stack; + + return 0; +} + +static void test_empty_stack(void **state) +{ + void *top_of_stack = *state; + + /* Expect success when checking empty stack. */ + assert_int_equal(0, checkstack(top_of_stack, 0)); +} + +static void test_almost_full_stack(void **state) +{ + void *top_of_stack = *state; + u32 *stack = (u32 *)_stack; + + /* Fill stack with random value except last word */ + for (size_t i = 1; i < STACK_SIZE / sizeof(u32); ++i) + stack[i] = 0xAA11FF44; + + /* Expect success when checking almost-full stack, + because last guard value is present */ + assert_int_equal(0, checkstack(top_of_stack, 0)); +} + +static void test_full_stack(void **state) +{ + void *top_of_stack = *state; + + /* Fill stack with value different than stack guard */ + fill_stack(0x600DB015); + + /* Expect failure when checking full stack as absence of guard value at the end of + the stack indicates stack overrun. */ + assert_int_equal(-1, checkstack(top_of_stack, 0)); +} + +static void test_partialy_filled_stack(void **state) +{ + void *top_of_stack = *state; + u32 *stack = (u32 *)_stack; + size_t i = STACK_SIZE / sizeof(u32) / 2; + + for (; i < STACK_SIZE / sizeof(u32); ++i) + stack[i] = 0x4321ABDC + i; + + /* Expect success when checking partially-filled stack, + because only part of stack is filled with non-guard value. */ + assert_int_equal(0, checkstack(top_of_stack, 0)); +} + +static void test_alternately_filled_stack(void **state) +{ + void *top_of_stack = *state; + u32 *stack = (u32 *)_stack; + size_t i; + + for (i = 0; i < STACK_SIZE / sizeof(u32); i += 2) + stack[i] = STACK_GUARD_VALUE; + + for (i = 1; i < STACK_SIZE / sizeof(u32); i += 2) + stack[i] = 0x42420707; + + assert_int_equal(0, checkstack(top_of_stack, 0)); +} + +static void test_incorrectly_initialized_stack(void **state) +{ + void *top_of_stack = *state; + u32 *stack = (u32 *)_stack; + + /* Remove last stack guard value */ + stack[0] = 0xFF00FF11; + + /* Expect failure when there is no last stack guard value even if no other value was + changed. */ + assert_int_equal(-1, checkstack(top_of_stack, 0)); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test_setup(test_empty_stack, setup_stack_test), + cmocka_unit_test_setup(test_almost_full_stack, setup_stack_test), + cmocka_unit_test_setup(test_full_stack, setup_stack_test), + cmocka_unit_test_setup(test_partialy_filled_stack, setup_stack_test), + cmocka_unit_test_setup(test_alternately_filled_stack, setup_stack_test), + cmocka_unit_test_setup(test_incorrectly_initialized_stack, setup_stack_test), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/50305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf0cceac290618a50ecc4e65f1f9551dbf31bd32 Gerrit-Change-Number: 50305 Gerrit-PatchSet: 5 Gerrit-Owner: jacz(a)semihalf.com Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2021