Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu.
Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56793
to look at the new patch set (#11).
Change subject: soc/mediatek: Enable PCIe support for mt8195
......................................................................
soc/mediatek: Enable PCIe support for mt8195
Enable PCIe support for mt8195.
TEST=Build pass and boot up to kernel successfully via SSD on Cherry
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x1987
PCI SSVID : 0x1987
SN : 28F40713077B0012602
MN : Phison ESE1A043-X28
RAB : 0x1
AERL : 0x3
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model Phison ESE1A043-X28
BUG=b:178565024
Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com>
Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff
---
M src/soc/mediatek/mt8195/Makefile.inc
M src/soc/mediatek/mt8195/soc.c
2 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/56793/11
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff
Gerrit-Change-Number: 56793
Gerrit-PatchSet: 11
Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
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Gerrit-MessageType: newpatchset