coreboot-gerrit December 2021

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Change in coreboot[master]: soc/mediatek/mt8195: Add driver to configure PCIe
by Jianjun Wang (Code Review) 31 Dec '21

31 Dec '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Angel Pons. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56792 ) Change subject: soc/mediatek/mt8195: Add driver to configure PCIe ...................................................................... Patch Set 8: (1 comment) File src/soc/mediatek/mt8195/pcie.c: https://review.coreboot.org/c/coreboot/+/56792/comment/27ee9841_a9a43934 PS6, Line 16: { : .cpu_addr = 0x20000000, : .pci_addr = 0x20000000, : .size = 0x1000000, : .type = IORESOURCE_IO, : }, : { : .cpu_addr = 0x21000000, : .pci_addr = 0x21000000, : .size = 0x3000000, : .type = IORESOURCE_MEM, : }, > Probably hardware-specific. Indeed, it would be great to specify where the values come from (e.g. […] comments updated. -- To view, visit https://review.coreboot.org/c/coreboot/+/56792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6799c53b03a33be91157ea088d829beb4272976 Gerrit-Change-Number: 56792 Gerrit-PatchSet: 8 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 31 Dec 2021 08:19:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Enable PCIe support for mt8195
by Jianjun Wang (Code Review) 31 Dec '21

31 Dec '21

Attention is currently required from: Hung-Te Lin. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56793 to look at the new patch set (#8). Change subject: soc/mediatek: Enable PCIe support for mt8195 ...................................................................... soc/mediatek: Enable PCIe support for mt8195 Enable PCIe support for mt8195. TEST=Build pass and boot up to kernel successfully via SSD on Cherry board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x1987 PCI SSVID : 0x1987 SN : 28F40713077B0012602 MN : Phison ESE1A043-X28 RAB : 0x1 AERL : 0x3 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model Phison ESE1A043-X28 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff --- M src/soc/mediatek/mt8195/Kconfig M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/soc.c 3 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/56793/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/56793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff Gerrit-Change-Number: 56793 Gerrit-PatchSet: 8 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Add PCIe support
by Jianjun Wang (Code Review) 31 Dec '21

31 Dec '21

Attention is currently required from: Shelley Chen, Hung-Te Lin, Furquan Shaikh, Paul Menzel, Angel Pons, Yu-Ping Wu. Hello Shelley Chen, Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56791 to look at the new patch set (#8). Change subject: soc/mediatek: Add PCIe support ...................................................................... soc/mediatek: Add PCIe support Add PCIe support for MediaTek platform. Reference: - MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250) - linux/drivers/pci/controller/pcie-mediatek-gen3.c This code is based on MT8195 platform, but it should be common in each platform with the same PCIe IP in the future. TEST=Build pass and boot up to kernel successfully via SSD on Cherry board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x1987 PCI SSVID : 0x1987 SN : 28F40713077B0012602 MN : Phison ESE1A043-X28 RAB : 0x1 AERL : 0x3 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model Phison ESE1A043-X28 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 --- A src/soc/mediatek/common/include/soc/pcie_common.h A src/soc/mediatek/common/pcie.c 2 files changed, 370 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/56791/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 8 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src: Use 'stdint.h' when appropriate
by HAOUAS Elyes (Code Review) 31 Dec '21

31 Dec '21

Attention is currently required from: Tristan Corrick, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Tristan Corrick, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60549 to look at the new patch set (#3). Change subject: src: Use 'stdint.h' when appropriate ...................................................................... src: Use 'stdint.h' when appropriate Change-Id: I1df255d55b8f43a711d836c2565c367bd988098a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asrock/b85m_pro4/romstage.c M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/romstage.c M src/mainboard/hp/folio_9480m/romstage.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/msi/h81m-p33/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c M src/northbridge/intel/gm45/early_init.c M src/soc/intel/baytrail/include/soc/modphy_table.h M src/soc/intel/baytrail/modphy_table.c M src/southbridge/intel/i82801gx/early_init.c 11 files changed, 2 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/60549/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/60549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1df255d55b8f43a711d836c2565c367bd988098a Gerrit-Change-Number: 60549 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Add PCIe support
by Jianjun Wang (Code Review) 31 Dec '21

31 Dec '21

Attention is currently required from: Shelley Chen, Hung-Te Lin, Furquan Shaikh, Paul Menzel, Angel Pons, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... Patch Set 7: (11 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56791/comment/8f905163_abd95494 PS6, Line 18: SSD > Which one exactly? On what board? […] Sorry for the late response, updated the board info and boot log, thanks. File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/56791/comment/76b7937a_e1d8fde9 PS2, Line 329: mtk_pcie_gen3_probe > Hi Jianjun, thanks for putting this together. […] Sorry for the late response, the device_operations has been used by soc_ops, can we still add this pci_domain_ops? File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/56791/comment/3533ed27_744e1727 PS6, Line 106: setctions > sections Done https://review.coreboot.org/c/coreboot/+/56791/comment/26c4f50c_53d5057f PS6, Line 111: mdelay(100); > One way to avoid this delay would be to assert PERST# earlier, and do something else in the meantime […] Yes, it's truly a long time, but it defined by PCIe spec, remove it directly will cause some compatibility issues, we can make this driver as user configurable first, and try to found a way to assert PERST# earlier, thanks. https://review.coreboot.org/c/coreboot/+/56791/comment/2f809e0c_e56fb118 PS6, Line 122: __func__, val); > Error messages should be user understandable. Please elaborate, and also document the effects. Done https://review.coreboot.org/c/coreboot/+/56791/comment/6f02e355_146fbbbc PS6, Line 159: res->cpu_addr | PCIE_ATR_SIZE(fls(res->size))); > Should fit in one line. Done https://review.coreboot.org/c/coreboot/+/56791/comment/27fbc25e_47778c52 PS6, Line 174: static int mtk_pcie_dev_assign_resource(struct device *dev, > Please excuse my ignorance, but what is special for assigning resources on MediaTek, that no common […] Thanks for your review, the PCIe module in arm platform seems different from the X86 platform, we have a 64MBytes MMIO space starting from 0x2000_0000, but I can't found any common function that can assign this start address to the PCIe resources(e.g. BAR, Bridge window), so I add these functions for: 1. Use mtk_pcie_dev_assign_resource to maintain the usage of the MMIO space; 2. Use mtk_pcie_bridge_assign_resources to update the resource base/size information of the bridge, let the config space of the root port can get the correct memory/io base/limit. https://review.coreboot.org/c/coreboot/+/56791/comment/03a2f7c2_23b15681 PS6, Line 180: printk(BIOS_INFO, "res->index = %#lx\n", res->index); > Looks more like debugging or spew? Done https://review.coreboot.org/c/coreboot/+/56791/comment/27631b49_10378538 PS6, Line 194: __func__, ctrl->mmio_io_size); > Plesae add the values to error message. […] Done https://review.coreboot.org/c/coreboot/+/56791/comment/26abe9ac_3d0742e8 PS6, Line 285: ret = mtk_pcie_startup_port(ctrl); : if (ret) : return; > Rewrite as […] Done https://review.coreboot.org/c/coreboot/+/56791/comment/b0cb8a91_540d2458 PS6, Line 289: printk(BIOS_INFO, "%s: Try to probe PCIe bus\n", __func__); > 1. Trying … […] This messages seems redundant, it has been removed, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 7 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 31 Dec 2021 07:47:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: REmove unused <string.h>
by HAOUAS Elyes (Code Review) 31 Dec '21

31 Dec '21

Attention is currently required from: Xi Chen, Hung-Te Lin. HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60559 ) Change subject: soc/mediatek: REmove unused <string.h> ...................................................................... soc/mediatek: REmove unused <string.h> Change-Id: I8f88541dce457e978a2cbea036d4f6eae387963f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/mediatek/mt8186/spm.c M src/soc/mediatek/mt8192/spm.c M src/soc/mediatek/mt8195/dp_intf.c M src/soc/mediatek/mt8195/dptx_hal.c M src/soc/mediatek/mt8195/mt6360.c M src/soc/mediatek/mt8195/spm.c 6 files changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/60559/1 diff --git a/src/soc/mediatek/mt8186/spm.c b/src/soc/mediatek/mt8186/spm.c index bc263eb..a1186ca 100644 --- a/src/soc/mediatek/mt8186/spm.c +++ b/src/soc/mediatek/mt8186/spm.c @@ -12,7 +12,6 @@ #include <soc/spm.h> #include <soc/spm_common.h> #include <soc/symbols.h> -#include <string.h> #include <timer.h> #define SPM_SYSTEM_BASE_OFFSET 0x40000000 diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c index 3a444df..f98f5fc 100644 --- a/src/soc/mediatek/mt8192/spm.c +++ b/src/soc/mediatek/mt8192/spm.c @@ -8,7 +8,6 @@ #include <soc/spm.h> #include <soc/spm_common.h> #include <soc/symbols.h> -#include <string.h> #include <timer.h> #define SPM_SYSTEM_BASE_OFFSET 0x40000000 diff --git a/src/soc/mediatek/mt8195/dp_intf.c b/src/soc/mediatek/mt8195/dp_intf.c index 6683767..7c9e204 100644 --- a/src/soc/mediatek/mt8195/dp_intf.c +++ b/src/soc/mediatek/mt8195/dp_intf.c @@ -10,7 +10,6 @@ #include <soc/pll.h> #include <soc/pll_common.h> #include <soc/spm.h> -#include <string.h> #include <timer.h> static void mtk_dpintf_mask(struct mtk_dpintf *dpintf, u32 offset, u32 val, u32 mask) diff --git a/src/soc/mediatek/mt8195/dptx_hal.c b/src/soc/mediatek/mt8195/dptx_hal.c index cc96cc8..ad68260 100644 --- a/src/soc/mediatek/mt8195/dptx_hal.c +++ b/src/soc/mediatek/mt8195/dptx_hal.c @@ -7,7 +7,6 @@ #include <soc/dptx.h> #include <soc/dptx_hal.h> #include <soc/dptx_reg.h> -#include <string.h> #include <timer.h> #include <types.h> diff --git a/src/soc/mediatek/mt8195/mt6360.c b/src/soc/mediatek/mt8195/mt6360.c index 142e244..729478e 100644 --- a/src/soc/mediatek/mt8195/mt6360.c +++ b/src/soc/mediatek/mt8195/mt6360.c @@ -4,7 +4,6 @@ #include <device/i2c_simple.h> #include <soc/mt6360.h> #include <stdbool.h> -#include <string.h> static struct mt6360_i2c_data i2c_data[] = { [MT6360_INDEX_LDO] = { diff --git a/src/soc/mediatek/mt8195/spm.c b/src/soc/mediatek/mt8195/spm.c index 018063c..52b0fd3 100644 --- a/src/soc/mediatek/mt8195/spm.c +++ b/src/soc/mediatek/mt8195/spm.c @@ -8,7 +8,6 @@ #include <soc/spm.h> #include <soc/spm_common.h> #include <soc/symbols.h> -#include <string.h> #include <timer.h> #define SPM_SYSTEM_BASE_OFFSET 0x40000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/60559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f88541dce457e978a2cbea036d4f6eae387963f Gerrit-Change-Number: 60559 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd: Remove unused <string.h>
by HAOUAS Elyes (Code Review) 31 Dec '21

31 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60558 ) Change subject: soc/amd: Remove unused <string.h> ...................................................................... soc/amd: Remove unused <string.h> Change-Id: Ibd3e7a62a2e833017f550eddd915b7dfb539d019 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/60558/1 diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index a90cbcf..fd95246 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -4,7 +4,6 @@ * ACPI - create the Fixed ACPI Description Tables (FADT) */ -#include <string.h> #include <console/console.h> #include <acpi/acpi.h> #include <acpi/acpigen.h> diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index b2cc20b..dda50b7 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -4,7 +4,6 @@ * ACPI - create the Fixed ACPI Description Tables (FADT) */ -#include <string.h> #include <console/console.h> #include <acpi/acpi.h> #include <acpi/acpigen.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/60558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd3e7a62a2e833017f550eddd915b7dfb539d019 Gerrit-Change-Number: 60558 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/smbios_defaults.c: Remove unused <string.h>
by HAOUAS Elyes (Code Review) 31 Dec '21

31 Dec '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60557 ) Change subject: arch/x86/smbios_defaults.c: Remove unused <string.h> ...................................................................... arch/x86/smbios_defaults.c: Remove unused <string.h> Change-Id: I099fe27c4f45411ed1a7157d097cf3e749eb11ff Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/smbios_defaults.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/60557/1 diff --git a/src/arch/x86/smbios_defaults.c b/src/arch/x86/smbios_defaults.c index 8b62ebb..7c10df3 100644 --- a/src/arch/x86/smbios_defaults.c +++ b/src/arch/x86/smbios_defaults.c @@ -3,7 +3,6 @@ #include <memory_info.h> #include <smbios.h> #include <stdint.h> -#include <string.h> /* this function will fill the corresponding locator */ __weak void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) -- To view, visit https://review.coreboot.org/c/coreboot/+/60557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I099fe27c4f45411ed1a7157d097cf3e749eb11ff Gerrit-Change-Number: 60557 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/dram/lpddr4.c: Remove unused <string.h>
by HAOUAS Elyes (Code Review) 31 Dec '21

31 Dec '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60556 ) Change subject: device/dram/lpddr4.c: Remove unused <string.h> ...................................................................... device/dram/lpddr4.c: Remove unused <string.h> Change-Id: Iba3135178f2d6021702971e4d887e9b4f8afeb76 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/dram/lpddr4.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/60556/1 diff --git a/src/device/dram/lpddr4.c b/src/device/dram/lpddr4.c index 3c686d0..a0c71f2 100644 --- a/src/device/dram/lpddr4.c +++ b/src/device/dram/lpddr4.c @@ -4,7 +4,6 @@ #include <cbmem.h> #include <device/device.h> #include <device/dram/lpddr4.h> -#include <string.h> #include <memory_info.h> #include <smbios.h> #include <types.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/60556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba3135178f2d6021702971e4d887e9b4f8afeb76 Gerrit-Change-Number: 60556 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/ec/google: Remove unused <string.h>
by HAOUAS Elyes (Code Review) 31 Dec '21

31 Dec '21

Attention is currently required from: Tim Wawrzynczak. HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60555 ) Change subject: src/ec/google: Remove unused <string.h> ...................................................................... src/ec/google: Remove unused <string.h> Change-Id: I4fdd0c9241293c7b911d19d8d80eaf1695edbccd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/google/chromeec/ec_smbios.c M src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/60555/1 diff --git a/src/ec/google/chromeec/ec_smbios.c b/src/ec/google/chromeec/ec_smbios.c index 1ee7283..6a2c7cf 100644 --- a/src/ec/google/chromeec/ec_smbios.c +++ b/src/ec/google/chromeec/ec_smbios.c @@ -3,7 +3,6 @@ #include <stddef.h> #include <ec/google/chromeec/ec.h> #include <console/console.h> -#include <string.h> #include <smbios.h> const char *google_chromeec_smbios_system_sku(void) diff --git a/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c b/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c index e61ecfd8..d6bca74 100644 --- a/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c +++ b/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c @@ -5,7 +5,7 @@ #include <console/console.h> #include <device/device.h> #include <device/path.h> -#include <string.h> + #include "chip.h" #define CROS_EC_I2C_TUNNEL_HID "GOOG0012" -- To view, visit https://review.coreboot.org/c/coreboot/+/60555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fdd0c9241293c7b911d19d8d80eaf1695edbccd Gerrit-Change-Number: 60555 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit December 2021