coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: ec/lenovo/h8/acpi: Replace LNot() with ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 31 Dec '21

31 Dec '21

Attention is currently required from: Felix Singer, Alexander Couzens. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60594 ) Change subject: ec/lenovo/h8/acpi: Replace LNot() with ASL 2.0 syntax ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8de151e7df39a0282d032b8ca96c2d1b01014c3a Gerrit-Change-Number: 60594 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Fri, 31 Dec 2021 14:04:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/quanta/it8518/acpi: Replace LNot() with ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 31 Dec '21

31 Dec '21

Attention is currently required from: Felix Singer. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60595 ) Change subject: ec/quanta/it8518/acpi: Replace LNot() with ASL 2.0 syntax ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98ac7a9c1cd16609cf6bd38e1bd9bf8cf54817fb Gerrit-Change-Number: 60595 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Fri, 31 Dec 2021 14:04:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/pci: Add PCIe interfaces for MediaTek platform
by Angel Pons (Code Review) 31 Dec '21

31 Dec '21

Attention is currently required from: Jianjun Wang. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56794 ) Change subject: libpayload/pci: Add PCIe interfaces for MediaTek platform ...................................................................... Patch Set 3: (2 comments) File payloads/libpayload/drivers/pcie_mediatek.c: https://review.coreboot.org/c/coreboot/+/56794/comment/3f950ad2_e08d8b9e PS3, Line 34: PCIE_CFG_FORCE_BYTE_EN | PCIE_CFG_BYTE_EN(bytes) Ah, if I understand correctly, this avoids clearing the wrong bytes when doing 8-bit or 16-bit writes. https://review.coreboot.org/c/coreboot/+/56794/comment/9c9de724_80704f67 PS3, Line 50: ((1 << (size * 8)) - 1) This mask shouldn't be necessary, as the return type of the `pci_read_configX()` functions already truncates the value accordingly. -- To view, visit https://review.coreboot.org/c/coreboot/+/56794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 Gerrit-Change-Number: 56794 Gerrit-PatchSet: 3 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 31 Dec 2021 14:02:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/i82371eb/acpi: Replace Decrement() with ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 31 Dec '21

31 Dec '21

Attention is currently required from: Felix Singer, Patrick Rudolph. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60587 ) Change subject: sb/intel/i82371eb/acpi: Replace Decrement() with ASL 2.0 syntax ...................................................................... Patch Set 1: (2 comments) File src/southbridge/intel/i82371eb/acpi/intx.asl: https://review.coreboot.org/c/coreboot/+/60587/comment/ee7195ca_6c9f2dc6 PS1, Line 43: \ we lost "\" File src/southbridge/intel/i82371eb/acpi/pirq.asl: https://review.coreboot.org/c/coreboot/+/60587/comment/d3799004_21e1f185 PS1, Line 53: \ same -- To view, visit https://review.coreboot.org/c/coreboot/+/60587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae59333a910cc913bb28ed5436c124b2ab282435 Gerrit-Change-Number: 60587 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 31 Dec 2021 14:01:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Add driver to configure PCIe
by Angel Pons (Code Review) 31 Dec '21

31 Dec '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu, Jianjun Wang. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56792 ) Change subject: soc/mediatek/mt8195: Add driver to configure PCIe ...................................................................... Patch Set 10: (7 comments) File src/soc/mediatek/mt8195/pcie.c: https://review.coreboot.org/c/coreboot/+/56792/comment/f633f21a_22a29b5b PS10, Line 16: static struct mtk_pcie_mmio_res pcie_mmio_res_p0[] = { : /* Some devices still need io ranges, reserve 16MB for compatibility */ : { : .cpu_addr = 0x20000000, : .pci_addr = 0x20000000, : .size = 0x1000000, : .type = IORESOURCE_IO, : }, : { : .cpu_addr = 0x21000000, : .pci_addr = 0x21000000, : .size = 0x3000000, : .type = IORESOURCE_MEM, : }, : }; In coreboot code, these resources would be reported in the bridge device's `read_resources` device operation. This calls `pci_bus_read_resources()` by default, but it's possible to call a different function that uses the values defined in here instead. See my comment on line 64 on how to bind specific device operations to the SoC's bridge devices. https://review.coreboot.org/c/coreboot/+/56792/comment/6d25c52a_8c364055 PS10, Line 39: const https://review.coreboot.org/c/coreboot/+/56792/comment/eb6c4240_c91f4585 PS10, Line 54: struct pad_func *pins = pcie_pins[port]; const https://review.coreboot.org/c/coreboot/+/56792/comment/4c4f0c8d_ca25eba8 PS10, Line 55: size_t pin_num = ARRAY_SIZE(pcie_pins[port]); nit: local variable not needed https://review.coreboot.org/c/coreboot/+/56792/comment/7d36d9b1_2fbe229e PS10, Line 64: void mtk_pcie_prepare(void) This code should be linked to a PCI device in devicetree.cb for the bridge device. Device operations can be bound to PCI devices by matching PCI vendor/device IDs using a PCI driver. The matching is done when scanning buses, which begins with the domain device: pci_domain_scan_bus() ---> pci_scan_bus() ---> pci_probe_dev() ---> set_pci_ops() The `set_pci_ops()` function first looks for a matching PCI driver in the list of PCI drivers [1], and falls back to default PCI operations if a matching PCI driver isn't found. Because the PCI bridge devices are part of the SoC, their vendor/device IDs are known, so you can use a PCI driver for them. You can use `src/northbridge/intel/haswell/pcie.c` as an example. [1]: We use some linker magic to have an array of PCI driver entries without having to declare an array in C code. Each PCI driver entry is put in a special section (see `__pci_driver` macro definition) so that the linker places them next to each other, effectively making the linker build the array for us. https://review.coreboot.org/c/coreboot/+/56792/comment/cc68bd84_2f84d061 PS10, Line 66: struct mtk_pcie_controller *ctrl; : : ctrl = (struct mtk_pcie_controller *)xzalloc(sizeof(*ctrl)); Looks like `ctrl` isn't used anywhere else, does it need to be dynamically allocated? https://review.coreboot.org/c/coreboot/+/56792/comment/bd9a0230_e51aa420 PS10, Line 70: 0x112f0000 Hmmm, so this value is used in the MTK common PCIe code. It would be nice to associate this value to the `struct device` itself, but I'm not sure what the best way would be. If the SoCs have at most one PCIe controller, this value could be a Kconfig option. However, I don't know if this is the case, as I don't have any datasheets. In any case, I'd avoid this approach as it's not very flexible. If some SoCs can have multiple PCIe controllers, one option would be to create a `mtk_pcie_soc_get_base()` function, declared in a MTK common header and defined in SoC-specific code, that takes a `const struct device *` parameter for the bridge and returns the corresponding value. For example, by checking the PCI vendor/device IDs or the PCI bus/device/function numbers. Also, I imagine this magic base address is SoC-specific and comes from some datasheet. It would be nice to add a comment referencing the source of this value. -- To view, visit https://review.coreboot.org/c/coreboot/+/56792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6799c53b03a33be91157ea088d829beb4272976 Gerrit-Change-Number: 56792 Gerrit-PatchSet: 10 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 31 Dec 2021 13:52:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: superio/winbond/w83627hf/acpi: Replace LOr() with ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 31 Dec '21

31 Dec '21

Attention is currently required from: Felix Singer, Felix Held. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60575 ) Change subject: superio/winbond/w83627hf/acpi: Replace LOr() with ASL 2.0 syntax ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96cd391f1bdeea0c7e0c4a71c225a3e6925b4c6b Gerrit-Change-Number: 60575 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 31 Dec 2021 13:48:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/gma/acpi: Replace LOr() with ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 31 Dec '21

31 Dec '21

Attention is currently required from: Felix Singer, Patrick Rudolph. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60576 ) Change subject: drivers/intel/gma/acpi: Replace LOr() with ASL 2.0 syntax ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26f785c2f959539141e70053ae38aac16d3b9185 Gerrit-Change-Number: 60576 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 31 Dec 2021 13:46:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/jecht: Replace LOr() with ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 31 Dec '21

31 Dec '21

Attention is currently required from: Felix Singer. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60577 ) Change subject: mb/google/jecht: Replace LOr() with ASL 2.0 syntax ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib34e8af6668e3c875fabd1fa84862109afa94d18 Gerrit-Change-Number: 60577 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Fri, 31 Dec 2021 13:45:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/aopen/dxplplusu/acpi: Replace LOr() with ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 31 Dec '21

31 Dec '21

Attention is currently required from: Felix Singer. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60578 ) Change subject: mb/aopen/dxplplusu/acpi: Replace LOr() with ASL 2.0 syntax ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib563f8ce5873e53c94992d81e78118a1194fc9af Gerrit-Change-Number: 60578 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Fri, 31 Dec 2021 13:44:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/acpi: Replace Increment() with ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 31 Dec '21

31 Dec '21

Attention is currently required from: Felix Singer, Lance Zhao, Tim Wawrzynczak. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60579 ) Change subject: arch/x86/acpi: Replace Increment() with ASL 2.0 syntax ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45ce13509f3e93d7d8cd69689604f24b926bcfbc Gerrit-Change-Number: 60579 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 31 Dec 2021 13:44:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2021