coreboot-gerrit December 2021

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Change in coreboot[master]: soc/intel/alderlake: Add Kconfigs for all PCH types
by Tim Wawrzynczak (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Angel Pons, Subrata Banik, Usha P, Patrick Rudolph, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59804 ) Change subject: soc/intel/alderlake: Add Kconfigs for all PCH types ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Good call Angel! -- To view, visit https://review.coreboot.org/c/coreboot/+/59804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976 Gerrit-Change-Number: 59804 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 17:27:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp/Kconfig: Drop redundant select
by Tim Wawrzynczak (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Angel Pons. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59803 ) Change subject: mb/intel/adlrvp/Kconfig: Drop redundant select ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I725b5b89cb049289b5505d1be5b9a434d64a6b78 Gerrit-Change-Number: 59803 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 17:26:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common Add support for CSE IOM/NPHY sub-parition update
by Krishna P Bhat D (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Marx Wang, Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Balaji Manigandan, Nick Vaccaro, Patrick Rudolph. Hello Marx Wang, build bot (Jenkins), Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Balaji Manigandan, Nick Vaccaro, Kane Chen, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59685 to look at the new patch set (#12). Change subject: soc/intel/common Add support for CSE IOM/NPHY sub-parition update ...................................................................... soc/intel/common Add support for CSE IOM/NPHY sub-parition update This patch adds the following support to coreboot 1. Kconfig to add IOM/NPHY in the COREBOOT/FW_MAIN_A/FW_MAIN_B partition of BIOS 2. Helper functions to support update. Pre-requisites to enable IOM/NPHY FW Update: 1.NPHY and IOM blobs have to be added to added COREBOOT, FW_MAIN_A and FW_MAIN_B through board configuration files. CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE: IOM blob Path SOC_INTEL_CSE_NPHY_CBFS_FILE: NPHY blob path 2.Enable CONFIG_CSE_SUB_PARTITION_UPDATE to enable CSE sub-partition NPHY/IOM update. coreboot follows below procedure to update NPHY and IOM: NPHY Update: 1.coreboot will navigate through the CSE region, identify the CSE’s NPHY FW version and BIOS NPHY version. 2.Compare both versions, if there is a difference, CSE will trigger an NPHY FW update. Otherwise, skips the NPHY FW update. IOM Update: 1.coreboot will navigate through the CSE region, identify CSE's IOM FW version and BIOS IOM version. 2.Compares both versions, if there is a difference, coreboot will trigger an IOM FW update.Otherwise, skip IOM FW update. Before coreboot triggers update of NPHY/IOM, BIOS sends SET BOOT PARTITION INFO(RO) to CSE and issues GLOBAL RESET commands if CSE boots from RW. coreboot updates CSE's NPHY and IOM sub-partition only if CSE boots from CSE RO Boot partition. Once CSE boots from RO, BIOS sends HMRFPO command to CSE, then triggers update of NPHY and IOM FW in the CSE Region(RO and RW). coreboot triggers NPHY/IOM update procedure in all ChromeOS boot modes(Normal and Recovery). BUG=b:202143532 BRANCH=None TEST=Build and verify CSE sub-partitions IOM and NPHY are getting updated with CBFS IOM and NPHY blobs. Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h A src/soc/intel/common/block/include/intelblocks/cse_layout.h 6 files changed, 505 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/59685/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/59685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Gerrit-Change-Number: 59685 Gerrit-PatchSet: 12 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marx Wang <marx.wang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/i2c/tpm: Add override function for TPM I2C bus
by EricR Lai (Code Review) 01 Dec '21

01 Dec '21

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59768 ) Change subject: drivers/i2c/tpm: Add override function for TPM I2C bus ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Thank for all good thoughts. Will restore this for the real needs in the future. -- To view, visit https://review.coreboot.org/c/coreboot/+/59768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I658468ed3880de0a6b947c212fa8737956928c57 Gerrit-Change-Number: 59768 Gerrit-PatchSet: 4 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 01 Dec 2021 16:02:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/tpm: Add override function for TPM I2C bus
by EricR Lai (Code Review) 01 Dec '21

01 Dec '21

EricR Lai has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/59768 ) Change subject: drivers/i2c/tpm: Add override function for TPM I2C bus ...................................................................... Abandoned temporary add new variant for it. will consider this if requested in the future. -- To view, visit https://review.coreboot.org/c/coreboot/+/59768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I658468ed3880de0a6b947c212fa8737956928c57 Gerrit-Change-Number: 59768 Gerrit-PatchSet: 4 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: src/northbridge/amd/pi/00730F01: enable PARALLEL_MP
by Arthur Heymans (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Michał Żygowski, Michał Kopeć. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59808 ) Change subject: src/northbridge/amd/pi/00730F01: enable PARALLEL_MP ...................................................................... Patch Set 2: (1 comment) File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/c/coreboot/+/59808/comment/8cdad80e_e760d7de PS2, Line 955: /* : * APIC ID calculation is tightly coupled with AGESA v5 code. : * This calculation MUST match the assignment calculation done : * in LocalApicInitializationAtEarly() function. : * And reference GetLocalApicIdForCore() : * : * Apply APIC enumeration rules : * For systems with >= 16 APICs, put the IO-APICs at 0..n and : * put the local-APICs at m..z : * : * This is needed because many IO-APIC devices only have 4 bits : * for their APIC id and therefore must reside at 0..15 : */ : if ((node_nums * core_max) + ioapic_count >= 0x10) { : lapicid_start = (ioapic_count - 1) / core_max; : lapicid_start = (lapicid_start + 1) * core_max; : printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); : } : u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); : printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", : i, j, apic_id); : : struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); : if (cpu) : amd_cpu_topology(cpu, i, j); > The comment describes what is done typically in the large core count systems. And yes the code assigns the IOAPICs at CONFIG_MAX_CPUS + n (n is the number of IOAPIC). This apic calculation could probably be removed since there is at most 8 CPUs in fam 16h models 30-3fh supported by the binaryPI, for the rest of the code IDK, would have to look deeper. Anway this is subject to change in another patch. Well both the parallel mp code as this code here add lapic devices to the linked list so regardless of the ioapic it's good to make sure these things won't be conflicting. -- To view, visit https://review.coreboot.org/c/coreboot/+/59808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db Gerrit-Change-Number: 59808 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 15:45:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kano: Enable USB2 port 9 for BlueTooth
by Paul Menzel (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: David Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59658 ) Change subject: mb/google/brya/var/kano: Enable USB2 port 9 for BlueTooth ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59658/comment/579f59fc_a1d39741 PS2, Line 7: BlueTooth Bluetooth -- To view, visit https://review.coreboot.org/c/coreboot/+/59658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7971509d7428562c80e781339ead059a189cea13 Gerrit-Change-Number: 59658 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 15:44:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Documentatiion/mb/facebook/fbg1701.md: Update memory information
by Paul Menzel (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Frans Hendriks. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59756 ) Change subject: Documentatiion/mb/facebook/fbg1701.md: Update memory information ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59756/comment/dacc478a_685a1b2e PS2, Line 7: Documentatiion Documentation -- To view, visit https://review.coreboot.org/c/coreboot/+/59756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bc851f72ae03e98ab1b2e0e04b07ccf6135ebeb Gerrit-Change-Number: 59756 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 15:43:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mp_init.c: Fix building without an SMI_HANDLER
by 9elements QA (Code Review) 01 Dec '21

01 Dec '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59694 ) Change subject: cpu/x86/mp_init.c: Fix building without an SMI_HANDLER ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 9 / 1 / 10 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/82891 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/82890 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/82889 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/82888 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/82887 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/82886 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/82885 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/82884 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/82883 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/82882 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/59694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieeaa85691e4c4516bb51df0e87c4ecaa940810f0 Gerrit-Change-Number: 59694 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 01 Dec 2021 15:24:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/northbridge/amd/pi/00730F01: enable PARALLEL_MP
by Michał Żygowski (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Michał Kopeć, Arthur Heymans. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59808 ) Change subject: src/northbridge/amd/pi/00730F01: enable PARALLEL_MP ...................................................................... Patch Set 2: (1 comment) File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/c/coreboot/+/59808/comment/0e2cabb7_cfb3ad35 PS2, Line 955: /* : * APIC ID calculation is tightly coupled with AGESA v5 code. : * This calculation MUST match the assignment calculation done : * in LocalApicInitializationAtEarly() function. : * And reference GetLocalApicIdForCore() : * : * Apply APIC enumeration rules : * For systems with >= 16 APICs, put the IO-APICs at 0..n and : * put the local-APICs at m..z : * : * This is needed because many IO-APIC devices only have 4 bits : * for their APIC id and therefore must reside at 0..15 : */ : if ((node_nums * core_max) + ioapic_count >= 0x10) { : lapicid_start = (ioapic_count - 1) / core_max; : lapicid_start = (lapicid_start + 1) * core_max; : printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); : } : u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); : printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", : i, j, apic_id); : : struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); : if (cpu) : amd_cpu_topology(cpu, i, j); > Can this be removed? BTW that comment about the io-apic ID does not match what the other code does a […] The comment describes what is done typically in the large core count systems. And yes the code assigns the IOAPICs at CONFIG_MAX_CPUS + n (n is the number of IOAPIC). This apic calculation could probably be removed since there is at most 8 CPUs in fam 16h models 30-3fh supported by the binaryPI, for the rest of the code IDK, would have to look deeper. Anway this is subject to change in another patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/59808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db Gerrit-Change-Number: 59808 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 01 Dec 2021 15:22:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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coreboot-gerrit December 2021