coreboot-gerrit December 2021

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Change in coreboot[master]: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update
by Krishna P Bhat D (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Marx Wang, Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Balaji Manigandan, Nick Vaccaro, Patrick Rudolph. Hello Marx Wang, build bot (Jenkins), Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Balaji Manigandan, Nick Vaccaro, Kane Chen, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59685 to look at the new patch set (#13). Change subject: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update ...................................................................... soc/intel/common: Add support for CSE IOM/NPHY sub-parition update This patch adds the following support to coreboot 1. Kconfig to add IOM/NPHY in the COREBOOT/FW_MAIN_A/FW_MAIN_B partition of BIOS 2. Helper functions to support update. Pre-requisites to enable IOM/NPHY FW Update: 1.NPHY and IOM blobs have to be added to added COREBOOT, FW_MAIN_A and FW_MAIN_B through board configuration files. CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE: IOM blob Path SOC_INTEL_CSE_NPHY_CBFS_FILE: NPHY blob path 2.Enable CONFIG_CSE_SUB_PARTITION_UPDATE to enable CSE sub-partition NPHY/IOM update. coreboot follows below procedure to update NPHY and IOM: NPHY Update: 1.coreboot will navigate through the CSE region, identify the CSE’s NPHY FW version and BIOS NPHY version. 2.Compare both versions, if there is a difference, CSE will trigger an NPHY FW update. Otherwise, skips the NPHY FW update. IOM Update: 1.coreboot will navigate through the CSE region, identify CSE's IOM FW version and BIOS IOM version. 2.Compares both versions, if there is a difference, coreboot will trigger an IOM FW update.Otherwise, skip IOM FW update. Before coreboot triggers update of NPHY/IOM, BIOS sends SET BOOT PARTITION INFO(RO) to CSE and issues GLOBAL RESET commands if CSE boots from RW. coreboot updates CSE's NPHY and IOM sub-partition only if CSE boots from CSE RO Boot partition. Once CSE boots from RO, BIOS sends HMRFPO command to CSE, then triggers update of NPHY and IOM FW in the CSE Region(RO and RW). coreboot triggers NPHY/IOM update procedure in all ChromeOS boot modes(Normal and Recovery). BUG=b:202143532 BRANCH=None TEST=Build and verify CSE sub-partitions IOM and NPHY are getting updated with CBFS IOM and NPHY blobs. Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h A src/soc/intel/common/block/include/intelblocks/cse_layout.h 6 files changed, 505 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/59685/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/59685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Gerrit-Change-Number: 59685 Gerrit-PatchSet: 13 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marx Wang <marx.wang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core
by Sridhar Siricilla (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Arthur Heymans, Nico Huber, Paul Menzel, Tim Wawrzynczak, Ravindra, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59359 ) Change subject: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core ...................................................................... Patch Set 5: (4 comments) Patchset: PS3: > Looking at code and referring to the sample implementation, I think below are only changes that we n […] Agree. >. Don't need to create any new cpu_index() function that returns sorted cpu index. Kindly note CPPC3 package entries are same across all cores except nominal performance which depends on the core type (small or big). Here only differentiator is nominal performance which has to be assigned to 0xCE(MSR).offset:8. Do you mean coreboot should set the MSR 0xCE with calculated nominal performance (based on core type) in the MP code instead of generating ACPI code for this element? File src/soc/intel/common/block/acpi/cpu_hybrid.c: https://review.coreboot.org/c/coreboot/+/59359/comment/ebce0226_61becb4e PS3, Line 63: get_cpu_type_bitmask > global_cpu_type_bitmask can be accessed by acpi_get_cpu_hybrid_info() directly, so get_cpu_type_bitm […] Ack https://review.coreboot.org/c/coreboot/+/59359/comment/5d803081_ab056c6f PS3, Line 152: acpigen_write_dword(core_id); > why not call XPPC using the actual information you want: big or small core instead of passing the co […] Correct, I have updated the patch that doesn't use bitmask. https://review.coreboot.org/c/coreboot/+/59359/comment/b2d5187d_a0031993 PS3, Line 98: void acpi_write_xppc_method(int core_id) : { : struct cpu_hybrid cpu_hybrid_info; : : acpi_get_cpu_hybrid_info(&cpu_hybrid_info); : acpigen_write_method(XPPC_PACKAGE_NAME, 1); : : if (cpu_is_nominal_freq_supported()) { : : /* : * If Nominal Frequency is supported, update Nominal Frequency and set core's : * Nominal Performance to a scaling factor which depends on core type(big or : * small). : */ : acpigen_set_package_element_int(CPPC_PACKAGE_NAME, 22, : cpu_hybrid_info.nominal_freq); : : /* LOCAL2_OP = (CORE >> core_id) & 1 */ : acpigen_emit_byte(SHIFT_RIGHT_OP); : acpigen_write_integer(cpu_hybrid_info.type_mask); : acpigen_emit_byte(ARG0_OP); : acpigen_emit_byte(LOCAL1_OP); : acpigen_write_and(LOCAL1_OP, ONE_OP, LOCAL2_OP); : : /* : * If core id is big Core, then set big core's scaling factor : * to core's nominal frequency otherwise set small core's scaling factor. : */ : acpigen_write_if_lequal_op_int(LOCAL2_OP, 1); : acpigen_set_package_element_int(CPPC_PACKAGE_NAME, 3, : cpu_hybrid_info.big_core_nom_perf); : acpigen_write_else(); : acpigen_set_package_element_int(CPPC_PACKAGE_NAME, 3, : cpu_hybrid_info.small_core_nom_perf); : acpigen_pop_len(); : } : : acpigen_emit_byte(RETURN_OP); : acpigen_emit_namestring(CPPC_PACKAGE_NAME); : acpigen_pop_len(); : } : : void acpigen_write_CPPC_hybrid_method(int core_id) : { : char scope[16]; : : if (core_id == 0) : snprintf(scope, 12, XPPC_PACKAGE_NAME, 0); : else : snprintf(scope, 16, CONFIG_ACPI_CPU_STRING "." XPPC_PACKAGE_NAME, 0); : : acpigen_write_method("_CPC", 0); : acpigen_emit_byte(RETURN_OP); : acpigen_emit_namestring(scope); : acpigen_write_dword(core_id); : acpigen_pop_len(); > I'm a bit confused. […] >Each CPU has _CPC method and they all use the implementation called XPPC_PACKAGE_NAME of CPU0? Might just as well generate it for each CPU and drop that weird bitmask code altogether. Correct, I have updated the patch without using the cpu type bit mask. -- To view, visit https://review.coreboot.org/c/coreboot/+/59359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca Gerrit-Change-Number: 59359 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 01 Dec 2021 18:33:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/gimble: Add PsysPmax setting to 143W
by Tim Wawrzynczak (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Chia-Ling Hou. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59797 ) Change subject: mb/google/gimble: Add PsysPmax setting to 143W ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: LGTM with the commit msg updates -- To view, visit https://review.coreboot.org/c/coreboot/+/59797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6a203f05ecfcc1020a422850d35fa3fa64e01d0 Gerrit-Change-Number: 59797 Gerrit-PatchSet: 1 Gerrit-Owner: Chia-Ling Hou <chia-ling.hou(a)intel.corp-partner.google.com> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Chia-Ling Hou <chia-ling.hou(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 18:06:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/gimble: Add PsysPmax setting to 143W
by Tim Wawrzynczak (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Chia-Ling Hou. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59797 ) Change subject: mb/google/gimble: Add PsysPmax setting to 143W ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6a203f05ecfcc1020a422850d35fa3fa64e01d0 Gerrit-Change-Number: 59797 Gerrit-PatchSet: 1 Gerrit-Owner: Chia-Ling Hou <chia-ling.hou(a)intel.corp-partner.google.com> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Chia-Ling Hou <chia-ling.hou(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 18:05:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Add PCIe support
by Shelley Chen (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Hung-Te Lin, Furquan Shaikh, Yu-Ping Wu, Jianjun Wang. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... Patch Set 6: (1 comment) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/56791/comment/4c23d633_9239fd4e PS2, Line 329: mtk_pcie_gen3_probe > Furquan is no longer in the team. […] Hi Jianjun, thanks for putting this together. As Furquan mentioned above, there is a pci_domain_ops callback structure that you can use to pull in the platform-specific functions: static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, }; the pci_domain_* functions are generic and already defined. If you need to add anything platform-specific, you can define your own functions and replace the associated field as appropriate. You can define the pci_domain_ops callback struct in the soc.c file for your soc (src/soc/mediatek/mt8195/soc.c ). -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 6 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 18:02:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add fls() (Find Last Set)
by Julius Werner (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Hung-Te Lin, Shelley Chen, Paul Menzel, Yu-Ping Wu, Jianjun Wang. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59738 ) Change subject: lib: Add fls() (Find Last Set) ...................................................................... Patch Set 4: (2 comments) File src/include/lib.h: https://review.coreboot.org/c/coreboot/+/59738/comment/e97f0a76_f8e61469 PS4, Line 56: /* Find Last Set: fls(1) == 1, fls(0) == 0, fls(1 << 31) == 32 */ Hmmm... this has the same problem that we originally had with ffs(). The established BSD versions of these functions count bits from 1, which is just intuitively wrong if you ask me. Everyone else counts bits from 0. The Linux kernel has both variants with ffs()/fls() counting from 1 and __ffs()/__fls() counting from 0. We chose to only provide the intuitive one here, and follow Linux' naming convention to avoid misunderstandings... that's why we only have __ffs() and not ffs(), and that's why I think you should also only add an __fls() here which is calculated as (32 - clz(x) - 1) (and rewrite the storage code needing this to work appropriately). Which then brings me to the thing I should have realized to begin with: at that point, __fls() is just the same as log2(). So you can really just use log2() in that code (and that's how we wrote all other code that needs something like this before, that's why nobody ever saw the need to add this here). But I'm also okay with adding __fls() as an alias for log2() if you think that makes things easier to read. https://review.coreboot.org/c/coreboot/+/59738/comment/2659442b_64065031 PS4, Line 66: If you do add anything new here, please also add a 64-bit variant down here and add the equivalents to libpayload.h, for consistency. -- To view, visit https://review.coreboot.org/c/coreboot/+/59738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib458abfec7e03b2979569a8440a6e69b0285ac32 Gerrit-Change-Number: 59738 Gerrit-PatchSet: 4 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 17:52:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/felwinter: Swap TPM and touchscreen I2C bus
by Tim Wawrzynczak (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Paul Menzel, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59799 ) Change subject: mb/google/brya/var/felwinter: Swap TPM and touchscreen I2C bus ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/mainboard/google/brya/variants/felwinter/overridetree.cb: https://review.coreboot.org/c/coreboot/+/59799/comment/41135934_4b88d2f3 PS1, Line 68: }" > That seems to do more than the commit message summary says? (More than just swapping the busses?) Since the I2C bus information changed, this common SoC config can't be derived from the baseboard anymore, so it has to be moved here as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/59799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic05843487ea540b8cd9a50d5f73803905fd80d49 Gerrit-Change-Number: 59799 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 17:35:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Fix S0i3 regression
by Tim Wawrzynczak (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Lance Zhao, Maulik V Vaghela, Paul Menzel, Meera Ravindranath, Subrata Banik, Archana Patni, Michael Niewöhner, Ronak Kanabar. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59790 ) Change subject: mb/google/brya: Fix S0i3 regression ...................................................................... Patch Set 2: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59790/comment/3b04ebe4_73bab76b PS2, Line 8: > Please describe the problem. […] When entering S0ix states, when the PM timer is enabled, the system is unable to enter S0i3 (PM timer off is required for S0i3 entry). https://review.coreboot.org/c/coreboot/+/59790/comment/1d81c90c_e1d9ddbc PS2, Line 9: ACPI PM timer needs to be disabled explicitly in CB to increment S0i3 : counter as FSP has no control to do the same since suggestion: I would state this more like ``` Keeping the PM timer being enabled will disqualify an ADL system from entering S0i3, and will also cause an increase in power during suspend states. The PM timer is not required for brya boards, therefore disable it. ``` https://review.coreboot.org/c/coreboot/+/59790/comment/5d1abb28_23347587 PS2, Line 14: TEST=Boot gimble to OS and verify S0i3 counter incrementing > How can this be verified? After exiting S0ix suspend state, `cat /sys/kernel/debug/pmc_core/substate_residencies` will show S0i3 residency and not S0i2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8005dacd732c033980ccc479375ff5b06df8dac1 Gerrit-Change-Number: 59790 Gerrit-PatchSet: 2 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Archana Patni <archana.patni(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Archana Patni <archana.patni(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 17:32:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add Kconfigs for all PCH types
by Subrata Banik (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Angel Pons, Usha P, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59804 ) Change subject: soc/intel/alderlake: Add Kconfigs for all PCH types ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976 Gerrit-Change-Number: 59804 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 17:31:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add Kconfig for ADL_N PCH
by Tim Wawrzynczak (Code Review) 01 Dec '21

01 Dec '21

Attention is currently required from: Reka Norman, Maulik V Vaghela, Paul Menzel, Rizwan Qureshi, Angel Pons, Subrata Banik, Sridhar Siricilla, Krishna P Bhat D, Usha P, Patrick Rudolph, Kangheui Won. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59751 ) Change subject: soc/intel/alderlake: Add Kconfig for ADL_N PCH ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I'd prefer to squash this change into CB:59752 for simplicity. +1 and also rebase on CB:59804 -- To view, visit https://review.coreboot.org/c/coreboot/+/59751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1be10aea36db5a14ca8d7cf5c087163e44554f78 Gerrit-Change-Number: 59751 Gerrit-PatchSet: 2 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Kangheui Won <khwon(a)google.com> Gerrit-Comment-Date: Wed, 01 Dec 2021 17:28:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit December 2021