coreboot-gerrit December 2021

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Change in coreboot[master]: mb/intel/adlrvp: Add support for external clock buffer
by Subrata Banik (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: V Sowmya, Maulik V Vaghela, Angel Pons, Subrata Banik, Tim Wawrzynczak, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59976 ) Change subject: mb/intel/adlrvp: Add support for external clock buffer ...................................................................... Patch Set 9: (2 comments) File src/mainboard/intel/adlrvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/59976/comment/ca6121a0_f941997d PS9, Line 29: . Rests > `, the rest are ` Ack https://review.coreboot.org/c/coreboot/+/59976/comment/3f6940a7_ace08fbe PS9, Line 29: Now if more than 4 PCH devices : * connected on the platform, external differential buffer chip needs to be placed at : * platform level. > `If more than 4 PCH devices are connected on the platform, an external differential buffer chip need […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Gerrit-Change-Number: 59976 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 08 Dec 2021 17:48:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Fix value of SA_DEVFN_CPU_PCIE1_0
by Tim Wawrzynczak (Code Review) 08 Dec '21

08 Dec '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59981 ) Change subject: soc/intel/alderlake: Fix value of SA_DEVFN_CPU_PCIE1_0 ...................................................................... soc/intel/alderlake: Fix value of SA_DEVFN_CPU_PCIE1_0 The macro was defined using PCH_DEV_SLOT_CPU_1, which doesn't exist, so replace it with the correct value of SA_DEV_SLOT_CPU_1. Change-Id: If6d294d681907c51ac5678c9251364d4d6df4329 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/include/soc/pci_devs.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/59981/1 diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index 1729160..956a021 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -26,7 +26,7 @@ #endif #define SA_DEV_SLOT_CPU_1 0x01 -#define SA_DEVFN_CPU_PCIE1_0 PCI_DEVFN(PCH_DEV_SLOT_CPU_1, 0) +#define SA_DEVFN_CPU_PCIE1_0 PCI_DEVFN(SA_DEV_SLOT_CPU_1, 0) #define SA_DEV_SLOT_IGD 0x02 #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/59981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d294d681907c51ac5678c9251364d4d6df4329 Gerrit-Change-Number: 59981 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Add support for external clock buffer
by Tim Wawrzynczak (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: V Sowmya, Subrata Banik, Maulik V Vaghela, Angel Pons, Tim Wawrzynczak, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59976 ) Change subject: mb/intel/adlrvp: Add support for external clock buffer ...................................................................... Patch Set 9: Code-Review+2 (2 comments) File src/mainboard/intel/adlrvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/59976/comment/8d2f55a4_f4f89819 PS9, Line 29: . Rests `, the rest are ` https://review.coreboot.org/c/coreboot/+/59976/comment/73ff512e_53cacc6e PS9, Line 29: Now if more than 4 PCH devices : * connected on the platform, external differential buffer chip needs to be placed at : * platform level. `If more than 4 PCH devices are connected on the platform, an external differential buffer chip needs to be placed at the platform level.` -- To view, visit https://review.coreboot.org/c/coreboot/+/59976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Gerrit-Change-Number: 59976 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 08 Dec 2021 17:14:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution
by Michał Żygowski (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Michał Kopeć. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52781 ) Change subject: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution ...................................................................... Patch Set 7: (1 comment) File src/cpu/amd/agesa/family14/model_14_init.c: https://review.coreboot.org/c/coreboot/+/52781/comment/0ad50b8d_0d3eb619 PS7, Line 76: display_mtrrs(); Some debug leftovers, to remove -- To view, visit https://review.coreboot.org/c/coreboot/+/52781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If706f8851ed0b1d45729e81175d82abb1d9193be Gerrit-Change-Number: 52781 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Wed, 08 Dec 2021 16:36:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/primus: Fix PLD group order
by Tim Wawrzynczak (Code Review) 08 Dec '21

08 Dec '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59953 ) Change subject: mb/google/brya/var/primus: Fix PLD group order ...................................................................... mb/google/brya/var/primus: Fix PLD group order In ec/google/chromeec: Add PLD to EC conn in ACPI table(667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. It causes the DUT to not boot into the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2 to solve this issue. BUG=b:209568644 BRANCH=none TEST=build coreboot and system boot into OS. Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: If5ce6ca061d9d56ba0bbb1f157b2ba278d3fa9c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59953 Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb 2 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Scott Chao: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 8424319..ef5ad98 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -322,7 +322,7 @@ chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "group" = "ACPI_PLD_GROUP(2, 1)" device ref tcss_usb3_port3 on end end end @@ -340,7 +340,7 @@ chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "group" = "ACPI_PLD_GROUP(2, 1)" device ref usb2_port3 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb index c12939f..ce06d30 100644 --- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb @@ -316,7 +316,7 @@ chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "group" = "ACPI_PLD_GROUP(2, 1)" device ref tcss_usb3_port3 on end end end @@ -334,7 +334,7 @@ chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "group" = "ACPI_PLD_GROUP(2, 1)" device ref usb2_port3 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/59953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5ce6ca061d9d56ba0bbb1f157b2ba278d3fa9c3 Gerrit-Change-Number: 59953 Gerrit-PatchSet: 4 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/primus: Fix PLD group order
by Tim Wawrzynczak (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Paul Menzel, Scott Chao. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59953 ) Change subject: mb/google/brya/var/primus: Fix PLD group order ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: FYI here is the temporary kernel revert as well (since this appears to possibly be a kernel bug), https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/… -- To view, visit https://review.coreboot.org/c/coreboot/+/59953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5ce6ca061d9d56ba0bbb1f157b2ba278d3fa9c3 Gerrit-Change-Number: 59953 Gerrit-PatchSet: 3 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 08 Dec 2021 16:05:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/primus: Fix PLD group order
by Casper Chang (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Paul Menzel, Scott Chao. Casper Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59953 ) Change subject: mb/google/brya/var/primus: Fix PLD group order ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Hi Tim, would you please help to submit this CL? Thanks a lot. -- To view, visit https://review.coreboot.org/c/coreboot/+/59953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5ce6ca061d9d56ba0bbb1f157b2ba278d3fa9c3 Gerrit-Change-Number: 59953 Gerrit-PatchSet: 3 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 08 Dec 2021 15:23:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Add support for external clock buffer
by Subrata Banik (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: V Sowmya, Maulik V Vaghela, Angel Pons, Subrata Banik, Tim Wawrzynczak, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59976 ) Change subject: mb/intel/adlrvp: Add support for external clock buffer ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59976/comment/ee08d457_9805720f PS8, Line 27: [ 5.496967] audit: type=1400 audit(1638945356.685:2): avc: denied { search } for pid=88 comm="kworker/0:3" name="mmc0:aaaa" dev="debugfs" ino=18919 scontext=u:r:kernel:s0 tcontext=u:object_r:debugfs_mmc:s0 tclass=dir permissive=1 > nit: this line is irrelevant Thanks Angel. You are right -- To view, visit https://review.coreboot.org/c/coreboot/+/59976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Gerrit-Change-Number: 59976 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 08 Dec 2021 15:03:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Add support for external clock buffer
by Subrata Banik (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: V Sowmya, Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, EricR Lai. Hello V Sowmya, build bot (Jenkins), Maulik V Vaghela, Angel Pons, Tim Wawrzynczak, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59976 to look at the new patch set (#9). Change subject: mb/intel/adlrvp: Add support for external clock buffer ...................................................................... mb/intel/adlrvp: Add support for external clock buffer ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's 3 will be used for CPU. Rests CLK SRC's are for PCH. Now if more than 4 PCH devices connected on the platform, external differential buffer chip needs to be placed at platform level. A mainboard designer can choose to add an external clock chip, and select the SRC CLK using CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER. CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to discrete buffer for further distribution to platform. TEST=Able to detect SD card connected at x4 PCIe Gen 3 Slot. localhost ~ # dmesg | grep mmc [ 4.997840] mmc0: SDHCI controller on PCI [0000:ae:00.0] using ADMA [ 5.460902] mmc0: new ultra high speed DDR50 SDHC card at address aaaa [ 5.473555] mmcblk0: mmc0:aaaa SS08G 7.40 GiB [ 5.494268] mmcblk0: p1 Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Signed-off-by: Subrata Banik <subi.banik(a)gmail.com> --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/romstage_fsp_params.c 2 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59976/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/59976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Gerrit-Change-Number: 59976 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/corsola: get SKU ID
by Yu-Ping Wu (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59944 ) Change subject: mb/google/corsola: get SKU ID ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2888190d498df28b5ae13cf92cc41d088e8f8ee7 Gerrit-Change-Number: 59944 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 08 Dec 2021 15:01:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2021