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Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59809 )
Change subject: cpu/amd/agesa/Kconfig: select NO_SMM for Family 14h
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59809/comment/cda2c8ec_b4df0e11
PS6, Line 11:
> Mention the fam15h and fam16h changes too?
Done
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Hello build bot (Jenkins), Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59809
to look at the new patch set (#7).
Change subject: cpu/amd/agesa/Kconfig: select NO_SMM for Family 14h
......................................................................
cpu/amd/agesa/Kconfig: select NO_SMM for Family 14h
Move the SMM Kconfig options to the specific agesa cpu families.
Select NO_SMM for family14 since since no Fam14h platform uses SMM.
Leave SMM_ASEG enabled for family15tn and family16kb for now.
TEST=Boot Debian 11 on PC Engines apu1
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
Change-Id: I09bbe036a88dada847219606ec79c68e7ca8e5cc
---
M src/cpu/amd/agesa/Kconfig
M src/cpu/amd/agesa/family14/Kconfig
M src/cpu/amd/agesa/family15tn/Kconfig
M src/cpu/amd/agesa/family16kb/Kconfig
4 files changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/59809/7
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59494 )
Change subject: libpayload/libc/fmap: Implement new FlashMap API
......................................................................
Patch Set 5:
(1 comment)
File payloads/libpayload/include/fmap.h:
https://review.coreboot.org/c/coreboot/+/59494/comment/6f3a1342_734bdb92
PS4, Line 6: #include <commonlib/bsd/cb_err.h>
> Done in CB:59916. Let's continnue discussion there. […]
Done
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Change subject: libpayload: Add include/commonlib/bsd to installed headers
......................................................................
Patch Set 3: Code-Review+2
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Attention is currently required from: V Sowmya, Subrata Banik, Maulik V Vaghela, Angel Pons, Tim Wawrzynczak.
Hello V Sowmya, build bot (Jenkins), Maulik V Vaghela, Angel Pons, Tim Wawrzynczak, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59976
to look at the new patch set (#8).
Change subject: mb/intel/adlrvp: Add support for external clock buffer
......................................................................
mb/intel/adlrvp: Add support for external clock buffer
ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals.
Out of 7 SRCCLK's 3 will be used for CPU. Rests CLK SRC's are for PCH.
Now if more than 4 PCH devices connected on the platform, external
differential buffer chip needs to be placed at platform level.
A mainboard designer can choose to add an external clock chip,
and select the SRC CLK using CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER.
CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock
to discrete buffer for further distribution to platform.
TEST=Able to detect SD card connected at x4 PCIe Gen 3 Slot.
localhost ~ # dmesg | grep mmc
[ 4.997840] mmc0: SDHCI controller on PCI [0000:ae:00.0] using ADMA
[ 5.460902] mmc0: new ultra high speed DDR50 SDHC card at address aaaa
[ 5.473555] mmcblk0: mmc0:aaaa SS08G 7.40 GiB
[ 5.494268] mmcblk0: p1
[ 5.496967] audit: type=1400 audit(1638945356.685:2): avc: denied { search } for pid=88 comm="kworker/0:3" name="mmc0:aaaa" dev="debugfs" ino=18919 scontext=u:r:kernel:s0 tcontext=u:object_r:debugfs_mmc:s0 tclass=dir permissive=1
Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb
Signed-off-by: Subrata Banik <subi.banik(a)gmail.com>
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
2 files changed, 39 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59976/8
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