coreboot-gerrit December 2021

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Change in coreboot[master]: mb/intel/adlrvp: Add support for external clock buffer
by EricR Lai (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: V Sowmya, Subrata Banik, Maulik V Vaghela, Angel Pons, Tim Wawrzynczak. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59976 ) Change subject: mb/intel/adlrvp: Add support for external clock buffer ...................................................................... Patch Set 7: (1 comment) File src/mainboard/intel/adlrvp/Kconfig: https://review.coreboot.org/c/coreboot/+/59976/comment/ac418650_eabdeccd PS5, Line 146: config GEN3_EXTERNAL_CLOCK_BUFFER > Make sense to me. If pch_m, CONFIG_MAX_PCIE_CLOCK_SRC equal to CONFIG_MAX_PCIE_CLOCK_REQ. Basically do nothing, but if's fine to add depend too. -- To view, visit https://review.coreboot.org/c/coreboot/+/59976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Gerrit-Change-Number: 59976 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Wed, 08 Dec 2021 14:34:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning
by Bao Zheng (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel, Zheng Bao, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59918 ) Change subject: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59918/comment/e5bb287c_30068e80 PS1, Line 7: tunning > tuning Done https://review.coreboot.org/c/coreboot/+/59918/comment/43d8cc80_cf6ab9bb PS1, Line 7: Cezanne FSP wrapper > Maybe: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac Gerrit-Change-Number: 59918 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 08 Dec 2021 14:27:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Google/Nipperkin: Add board specific value for eDP tuning
by Bao Zheng (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Paul Menzel, Zheng Bao. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59919 ) Change subject: Google/Nipperkin: Add board specific value for eDP tuning ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59919/comment/48088845_5522c6cf PS1, Line 7: tunning > tuning Done File src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/59919/comment/a7c227c9_e24e0870 PS1, Line 97: #bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2, bit3=1: DP3 > Add exactly a space after #. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa8c594d9f5caa6b2523dac079aef89e623c56f Gerrit-Change-Number: 59919 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Wed, 08 Dec 2021 14:26:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Google/Nipperkin: Add board specific value for eDP tuning
by Bao Zheng (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Bao Zheng, Zheng Bao. Hello build bot (Jenkins), Zheng Bao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59919 to look at the new patch set (#2). Change subject: Google/Nipperkin: Add board specific value for eDP tuning ...................................................................... Google/Nipperkin: Add board specific value for eDP tuning BUG=b:203061533 Change-Id: I7aa8c594d9f5caa6b2523dac079aef89e623c56f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/59919/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa8c594d9f5caa6b2523dac079aef89e623c56f Gerrit-Change-Number: 59919 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning
by Bao Zheng (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Marshall Dawson, Zheng Bao, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59918 to look at the new patch set (#2). Change subject: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning ...................................................................... soc/amd/cezanne: FSP: Add UPD entry for eDP tuning BUG=b:203061533 Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fsp_m_params.c M src/vendorcode/amd/fsp/cezanne/FspmUpd.h 3 files changed, 31 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/59918/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac Gerrit-Change-Number: 59918 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Add support for external clock buffer
by Subrata Banik (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: V Sowmya, Subrata Banik, Maulik V Vaghela, Angel Pons, Tim Wawrzynczak, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59976 ) Change subject: mb/intel/adlrvp: Add support for external clock buffer ...................................................................... Patch Set 7: (1 comment) File src/mainboard/intel/adlrvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/59976/comment/e68171c4_b9a7c5f2 PS4, Line 27: /* > I think so. It's better now. Thanks Eric. -- To view, visit https://review.coreboot.org/c/coreboot/+/59976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Gerrit-Change-Number: 59976 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 08 Dec 2021 14:16:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Add support for external clock buffer
by Subrata Banik (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: V Sowmya, Subrata Banik, Maulik V Vaghela, Angel Pons, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59976 ) Change subject: mb/intel/adlrvp: Add support for external clock buffer ...................................................................... Patch Set 5: (1 comment) File src/mainboard/intel/adlrvp/Kconfig: https://review.coreboot.org/c/coreboot/+/59976/comment/2a3f557b_4a763088 PS5, Line 146: config GEN3_EXTERNAL_CLOCK_BUFFER > I'd add `depends on SOC_INTEL_ALDERLAKE_PCH_P` Make sense to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/59976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Gerrit-Change-Number: 59976 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Wed, 08 Dec 2021 14:14:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Store serial number in CMOS
by Sean Rhodes (Code Review) 08 Dec '21

08 Dec '21

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59979 ) Change subject: mb/starlabs/labtop: Store serial number in CMOS ...................................................................... mb/starlabs/labtop: Store serial number in CMOS Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I70c35c8f99f7e3ac8e45e742156dca741a6c6933 --- M src/mainboard/starlabs/labtop/cmos.default M src/mainboard/starlabs/labtop/cmos.layout M src/mainboard/starlabs/labtop/mainboard.c 3 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/59979/1 diff --git a/src/mainboard/starlabs/labtop/cmos.default b/src/mainboard/starlabs/labtop/cmos.default index b4b2d26..96e3e51 100644 --- a/src/mainboard/starlabs/labtop/cmos.default +++ b/src/mainboard/starlabs/labtop/cmos.default @@ -19,3 +19,5 @@ fn_ctrl_swap=Disable # southbridge power_on_after_fail=Disable +# serial number +serial_number=00000 diff --git a/src/mainboard/starlabs/labtop/cmos.layout b/src/mainboard/starlabs/labtop/cmos.layout index 2601e98..7c9a133 100644 --- a/src/mainboard/starlabs/labtop/cmos.layout +++ b/src/mainboard/starlabs/labtop/cmos.layout @@ -50,6 +50,8 @@ 1040 8 h 10 kbl_brightness 1048 8 h 1 kbl_state +# serial number +2000 16 h 0 serial_number # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/starlabs/labtop/mainboard.c b/src/mainboard/starlabs/labtop/mainboard.c index 8babae3..02bdfb8 100644 --- a/src/mainboard/starlabs/labtop/mainboard.c +++ b/src/mainboard/starlabs/labtop/mainboard.c @@ -43,5 +43,5 @@ const char *smbios_chassis_serial_number(void) { - return smbios_mainboard_serial_number(); + return CONFIG_MAINBOARD_FAMILY && get_uint_options("serial_number"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/59979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70c35c8f99f7e3ac8e45e742156dca741a6c6933 Gerrit-Change-Number: 59979 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Add support for external clock buffer
by Angel Pons (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: V Sowmya, Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59976 ) Change subject: mb/intel/adlrvp: Add support for external clock buffer ...................................................................... Patch Set 5: (1 comment) File src/mainboard/intel/adlrvp/Kconfig: https://review.coreboot.org/c/coreboot/+/59976/comment/b1946b67_9f2c2f26 PS5, Line 146: config GEN3_EXTERNAL_CLOCK_BUFFER I'd add `depends on SOC_INTEL_ALDERLAKE_PCH_P` -- To view, visit https://review.coreboot.org/c/coreboot/+/59976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Gerrit-Change-Number: 59976 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Wed, 08 Dec 2021 13:52:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/amd/pi/hudson/early_init: fix setting SPI_USE_SPI100 in SPI100_ENABLE
by Felix Held (Code Review) 08 Dec '21

08 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59934 ) Change subject: sb/amd/pi/hudson/early_init: fix setting SPI_USE_SPI100 in SPI100_ENABLE ...................................................................... sb/amd/pi/hudson/early_init: fix setting SPI_USE_SPI100 in SPI100_ENABLE Use a read modify write sequence when setting the SPI_USE_SPI100 bit in the SPI100_ENABLE register. This avoids clearing other bits in the register which might cause instabilities. Haven't checked the reference code, but the register descriptions suggested that the register in Mullins behaves similar to the one in Stoneyridge. Right now this code is unused, but it's probably still a good idea to fix it. TEST=Booting Debian 11 with kernel 5.10 on apu2 still works when adding a call to hudson_set_spi100 with this patch applied. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifbd960a9509542b28f03326a3066995540260bef Tested-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59934 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/southbridge/amd/pi/hudson/early_setup.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Michał Żygowski: Looks good to me, approved diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 20597d4..2617985 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -215,7 +215,8 @@ (fast << SPI_FAST_SPEED_NEW_SH) | (alt << SPI_ALT_SPEED_NEW_SH) | (tpm << SPI_TPM_SPEED_NEW_SH)); - write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); + write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100 | + read16((void *)(base + SPI100_ENABLE))); } void hudson_disable_4dw_burst(void) 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbd960a9509542b28f03326a3066995540260bef Gerrit-Change-Number: 59934 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2021