coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: IASL: Ignore IASL's "Missing dependency" warning
by HAOUAS Elyes (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Paul Menzel, HAOUAS Elyes. Hello build bot (Jenkins), Martin Roth, Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59880 to look at the new patch set (#2). Change subject: IASL: Ignore IASL's "Missing dependency" warning ...................................................................... IASL: Ignore IASL's "Missing dependency" warning IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects: 1) If _PRS is present, must have _CRS and _SRS 2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS) 3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS) 4) If _SRS is present, probably should have a _DIS (Remark only) IASL will issue a warning for each missing dependency. Ignore this warnings for existing ASL code. Change-Id: I28b437194f08232727623009372327fec15215dd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc M src/mainboard/acer/g43t-am3/Kconfig M src/mainboard/asrock/h81m-hds/Kconfig M src/mainboard/asus/am1i-a/Kconfig M src/mainboard/asus/h61-series/Kconfig M src/mainboard/asus/p5qpl-am/Kconfig M src/mainboard/bap/ode_e20XX/Kconfig M src/mainboard/biostar/am1ml/Kconfig M src/mainboard/dell/optiplex_9010/Kconfig M src/mainboard/facebook/fbg1701/Kconfig M src/mainboard/facebook/monolith/Kconfig M src/mainboard/foxconn/d41s/Kconfig M src/mainboard/foxconn/g41s-k/Kconfig M src/mainboard/gigabyte/ga-d510ud/Kconfig M src/mainboard/google/auron/Kconfig M src/mainboard/google/beltino/Kconfig M src/mainboard/google/brya/Kconfig M src/mainboard/google/butterfly/Kconfig M src/mainboard/google/cyan/Kconfig M src/mainboard/google/dedede/Kconfig M src/mainboard/google/deltaur/Kconfig M src/mainboard/google/drallion/Kconfig M src/mainboard/google/eve/Kconfig M src/mainboard/google/fizz/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/hatch/Kconfig M src/mainboard/google/jecht/Kconfig M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/link/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/google/poppy/Kconfig M src/mainboard/google/rambi/Kconfig M src/mainboard/google/reef/Kconfig M src/mainboard/google/sarien/Kconfig M src/mainboard/google/slippy/Kconfig M src/mainboard/google/stout/Kconfig M src/mainboard/google/volteer/Kconfig M src/mainboard/google/zork/Kconfig M src/mainboard/ibase/mb899/Kconfig M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/baskingridge/Kconfig M src/mainboard/intel/dcp847ske/Kconfig M src/mainboard/intel/dg41wv/Kconfig M src/mainboard/intel/dg43gt/Kconfig M src/mainboard/intel/emeraldlake2/Kconfig M src/mainboard/intel/glkrvp/Kconfig M src/mainboard/intel/jasperlake_rvp/Kconfig M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kunimitsu/Kconfig M src/mainboard/intel/shadowmountain/Kconfig M src/mainboard/intel/strago/Kconfig M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/kontron/986lcd-m/Kconfig M src/mainboard/portwell/m107/Kconfig M src/mainboard/protectli/vault_bsw/Kconfig M src/mainboard/samsung/lumpy/Kconfig M src/mainboard/samsung/stumpy/Kconfig M src/mainboard/supermicro/x10slm-f/Kconfig M src/mainboard/supermicro/x9scl/Kconfig 60 files changed, 212 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/59880/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28b437194f08232727623009372327fec15215dd Gerrit-Change-Number: 59880 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Add support for external clock buffer
by Subrata Banik (Code Review) 08 Dec '21

08 Dec '21

Subrata Banik has uploaded a new patch set (#4) to the change originally created by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/59976 ) Change subject: mb/intel/adlrvp: Add support for external clock buffer ...................................................................... mb/intel/adlrvp: Add support for external clock buffer ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's 3 will be used for CPU. Rests CLK SRC's are for PCH. Now if more than 4 PCH devices connected on the platform, external differential buffer chip needs to be placed at platform level. A mainboard designer can choose to add an external clock chip, and select the SRC CLK using CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER. CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to discrete buffer for further distribution to platform. TEST=Able to detect SD card connected at x4 PCIe Gen 3 Slot. localhost ~ # dmesg | grep mmc [ 4.997840] mmc0: SDHCI controller on PCI [0000:ae:00.0] using ADMA [ 5.460902] mmc0: new ultra high speed DDR50 SDHC card at address aaaa [ 5.473555] mmcblk0: mmc0:aaaa SS08G 7.40 GiB [ 5.494268] mmcblk0: p1 [ 5.496967] audit: type=1400 audit(1638945356.685:2): avc: denied { search } for pid=88 comm="kworker/0:3" name="mmc0:aaaa" dev="debugfs" ino=18919 scontext=u:r:kernel:s0 tcontext=u:object_r:debugfs_mmc:s0 tclass=dir permissive=1 Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Signed-off-by: Subrata Banik <subi.banik(a)gmail.com> --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/romstage_fsp_params.c 2 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59976/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Gerrit-Change-Number: 59976 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: revise SPI NOR GPIO selection
by 9elements QA (Code Review) 08 Dec '21

08 Dec '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59940 ) Change subject: soc/mediatek/mt8186: revise SPI NOR GPIO selection ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 7 / 1 / 8 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/83783 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/83782 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/83781 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/83780 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/83779 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/83778 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/83777 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/83776 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/59940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ideacb797a1dc9999ab6ba00cf33adbbbc24213dc Gerrit-Change-Number: 59940 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 08 Dec 2021 12:00:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Add support for external clock buffer
by Subrata Banik (Code Review) 08 Dec '21

08 Dec '21

Subrata Banik has uploaded a new patch set (#3) to the change originally created by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/59976 ) Change subject: mb/intel/adlrvp: Add support for external clock buffer ...................................................................... mb/intel/adlrvp: Add support for external clock buffer ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's 3 will be used for CPU. Rests CLK SRC's are for PCH. Now if more than 4 PCH devices connected on the platform, external differential buffer chip needs to be placed at platform level. A mainboard designer can choose to add an external clock chip, and select the SRC CLK using CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER. CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to discrete buffer for further distribution to platform. Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Signed-off-by: Subrata Banik <subi.banik(a)gmail.com> --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/romstage_fsp_params.c 2 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59976/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Gerrit-Change-Number: 59976 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: Override EN_SPKR GPIO
by Kenneth Chan (Code Review) 08 Dec '21

08 Dec '21

Kenneth Chan has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/59978 ) Change subject: mb/google/guybrush/var/dewatt: Override EN_SPKR GPIO ...................................................................... mb/google/guybrush/var/dewatt: Override EN_SPKR GPIO Override EN_SPKR GPIO for dewatt. BUG=b:208172493 TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: Idf705e12f30ad145449be8d97cb214c56c02ec33 --- M src/mainboard/google/guybrush/variants/dewatt/Makefile.inc A src/mainboard/google/guybrush/variants/dewatt/gpio.c 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/59978/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf705e12f30ad145449be8d97cb214c56c02ec33 Gerrit-Change-Number: 59978 Gerrit-PatchSet: 2 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: Override SPKR_EN GPIO
by Kenneth Chan (Code Review) 08 Dec '21

08 Dec '21

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59978 ) Change subject: mb/google/guybrush/var/dewatt: Override SPKR_EN GPIO ...................................................................... mb/google/guybrush/var/dewatt: Override SPKR_EN GPIO Override SPKR_EN GPIO for dewatt. BUG=b:208172493 TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: Idf705e12f30ad145449be8d97cb214c56c02ec33 --- M src/mainboard/google/guybrush/variants/dewatt/Makefile.inc A src/mainboard/google/guybrush/variants/dewatt/gpio.c 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/59978/1 diff --git a/src/mainboard/google/guybrush/variants/dewatt/Makefile.inc b/src/mainboard/google/guybrush/variants/dewatt/Makefile.inc index 88e75bd..dcdc83b 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/dewatt/Makefile.inc @@ -1,3 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c +verstage-y += gpio.c + subdirs-y += ./memory + +smm-y += gpio.c diff --git a/src/mainboard/google/guybrush/variants/dewatt/gpio.c b/src/mainboard/google/guybrush/variants/dewatt/gpio.c new file mode 100644 index 0000000..9bf3532 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/dewatt/gpio.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <baseboard/variants.h> +/* This table is used by dewatt*/ +static const struct soc_amd_gpio bid_override_gpio_table[] = { + /* EN_SPKR */ + PAD_GPO(GPIO_70, HIGH), +}; +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(bid_override_gpio_table); + return bid_override_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf705e12f30ad145449be8d97cb214c56c02ec33 Gerrit-Change-Number: 59978 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/corsola: get SKU ID from EC (CBI)
by Hung-Te Lin (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Rex-BC Chen, Paul Menzel. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59944 ) Change subject: mb/google/corsola: get SKU ID from EC (CBI) ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59944/comment/8900d9dc_33822f3c PS6, Line 7: mb/google/corsola: get SKU ID from EC (CBI) : : Retrieve the SKU ID for Corsola via CBI interface. : There is one SKU ID and the ID is logged to the console. give you do have fallback implemented, that should be described. mb/google/corsola: Get SKU ID Retrieve the SKU ID for Corsola via CBI interface. If that failed (or no data found), fallback to ADC channels for SKU ID. -- To view, visit https://review.coreboot.org/c/coreboot/+/59944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2888190d498df28b5ae13cf92cc41d088e8f8ee7 Gerrit-Change-Number: 59944 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 08 Dec 2021 11:35:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/corsola: Configure TPM
by Hung-Te Lin (Code Review) 08 Dec '21

08 Dec '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59943 ) Change subject: mb/google/corsola: Configure TPM ...................................................................... mb/google/corsola: Configure TPM Initialize SPI bus 2 for TPM control. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I8ede68d6eb594890195e8464151c1c0f88aeee43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59943 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/bootblock.c M src/mainboard/google/corsola/chromeos.c 3 files changed, 14 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index 2a935f3..8877f2f 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -24,6 +24,8 @@ select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SPI + select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT + select MAINBOARD_HAS_TPM2 if VBOOT config MAINBOARD_DIR string @@ -43,6 +45,10 @@ bool default n +config DRIVER_TPM_SPI_BUS + hex + default 0x2 + config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 0x1 diff --git a/src/mainboard/google/corsola/bootblock.c b/src/mainboard/google/corsola/bootblock.c index d742074..ea36fed 100644 --- a/src/mainboard/google/corsola/bootblock.c +++ b/src/mainboard/google/corsola/bootblock.c @@ -9,6 +9,8 @@ void bootblock_mainboard_init(void) { mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); + mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); mtk_snfc_init(SPI_NOR_GPIO_SET0); setup_chromeos_gpios(); + gpio_eint_configure(GPIO_GSC_AP_INT, IRQ_TYPE_EDGE_RISING); } diff --git a/src/mainboard/google/corsola/chromeos.c b/src/mainboard/google/corsola/chromeos.c index 84023b7..847569e 100644 --- a/src/mainboard/google/corsola/chromeos.c +++ b/src/mainboard/google/corsola/chromeos.c @@ -3,6 +3,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> +#include <security/tpm/tis.h> #include "gpio.h" @@ -32,3 +33,8 @@ /* EC is trusted if not in RW. This is active low. */ return !!gpio_get(GPIO_EC_IN_RW); } + +int tis_plat_irq_status(void) +{ + return gpio_eint_poll(GPIO_GSC_AP_INT); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ede68d6eb594890195e8464151c1c0f88aeee43 Gerrit-Change-Number: 59943 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/corsola: implement get_ec_is_trusted
by Hung-Te Lin (Code Review) 08 Dec '21

08 Dec '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59942 ) Change subject: mb/google/corsola: implement get_ec_is_trusted ...................................................................... mb/google/corsola: implement get_ec_is_trusted Set VB2_CONTEXT_EC_TRUSTED in verstage_main. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: If2837f5db52f91f5418d222d4dcd1af2aebcc105 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59942 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/corsola/chromeos.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/corsola/chromeos.c b/src/mainboard/google/corsola/chromeos.c index 63c3f4c..84023b7 100644 --- a/src/mainboard/google/corsola/chromeos.c +++ b/src/mainboard/google/corsola/chromeos.c @@ -26,3 +26,9 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. This is active low. */ + return !!gpio_get(GPIO_EC_IN_RW); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2837f5db52f91f5418d222d4dcd1af2aebcc105 Gerrit-Change-Number: 59942 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/corsola: Enable Chrome EC
by Hung-Te Lin (Code Review) 08 Dec '21

08 Dec '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59941 ) Change subject: mb/google/corsola: Enable Chrome EC ...................................................................... mb/google/corsola: Enable Chrome EC Initialize SPI bus 1 for Chrome EC control. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I7d032d595f7ca1dbed3de4dfe308ff4be64333cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59941 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/bootblock.c M src/mainboard/google/corsola/chromeos.c M src/mainboard/google/corsola/reset.c 4 files changed, 17 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index b57e23b..2a935f3 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -6,16 +6,24 @@ if BOARD_GOOGLE_CORSOLA_COMMON +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_VBNV_FLASH + config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_MEDIATEK_MT8186 select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select SPI_FLASH select SPI_FLASH_INCLUDE_ALL_DRIVERS select COMMONLIB_STORAGE select COMMONLIB_STORAGE_MMC + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SPI config MAINBOARD_DIR string @@ -34,4 +42,8 @@ config SDCARD_INIT bool default n + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0x1 endif diff --git a/src/mainboard/google/corsola/bootblock.c b/src/mainboard/google/corsola/bootblock.c index bb76b98..d742074 100644 --- a/src/mainboard/google/corsola/bootblock.c +++ b/src/mainboard/google/corsola/bootblock.c @@ -8,6 +8,7 @@ void bootblock_mainboard_init(void) { + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); mtk_snfc_init(SPI_NOR_GPIO_SET0); setup_chromeos_gpios(); } diff --git a/src/mainboard/google/corsola/chromeos.c b/src/mainboard/google/corsola/chromeos.c index 6a727c9..63c3f4c 100644 --- a/src/mainboard/google/corsola/chromeos.c +++ b/src/mainboard/google/corsola/chromeos.c @@ -26,9 +26,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_recovery_mode_switch(void) -{ - /* TODO: use Chrome EC switches when EC support is added */ - return 0; -} diff --git a/src/mainboard/google/corsola/reset.c b/src/mainboard/google/corsola/reset.c index 3a97ee5..91ee7c0 100644 --- a/src/mainboard/google/corsola/reset.c +++ b/src/mainboard/google/corsola/reset.c @@ -1,7 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <gpio.h> #include <reset.h> +#include "gpio.h" + void do_board_reset(void) { + gpio_output(GPIO_RESET, 1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/59941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d032d595f7ca1dbed3de4dfe308ff4be64333cd Gerrit-Change-Number: 59941 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2021