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Change in coreboot[master]: util/testing: combine code coverage data
by Felix Held (Code Review) 08 Dec '21

08 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59959 ) Change subject: util/testing: combine code coverage data ...................................................................... util/testing: combine code coverage data As part of the `what-jenkins-does` target, combine the code coverage data from all unit tests (currently just coreboot and libpayload). BUG=b:203800199 TEST=`make what-jenkins-does && ls -l coreboot-builds/coverage.info` Signed-off-by: Paul Fagerburg <pfagerburg(a)google.com> Change-Id: Id99615ca8279f80a402d5371221b8fd36fb91d55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59959 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <patrick(a)coreboot.org> --- M util/testing/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index 1411c7e..0830aea 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -105,6 +105,7 @@ $(MAKE) unit-tests JUNIT_OUTPUT=y COV=1 (cd payloads/libpayload; unset COREBOOT_BUILD_DIR; $(MAKE) unit-tests coverage-report JUNIT_OUTPUT=y COV=1) $(MAKE) coverage-report JUNIT_OUTPUT=y COV=1 + find . -name 'tests.info' -exec cat {} + >$(COREBOOT_BUILD_DIR)/coverage.info test-basic: test-lint test-tools test-abuild test-payloads test-cleanup 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id99615ca8279f80a402d5371221b8fd36fb91d55 Gerrit-Change-Number: 59959 Gerrit-PatchSet: 4 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Combine mem_parts_used.txt
by Felix Held (Code Review) 08 Dec '21

08 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59923 ) Change subject: mb/google/guybrush: Combine mem_parts_used.txt ...................................................................... mb/google/guybrush: Combine mem_parts_used.txt Combine guybrush mem_parts_used.txt across guybrush variants. Guybrush reference memory parts is used as the base, then Nipperkin memory parts were appended, followed by DeWatt memory parts. Duplicates were removed. The memory id mapping was not affected on guybrush reference and Nipperkin. DeWatt memory id mapping was affected, DeWatt boards will need to be adjusted. This works around a limitation in APCB, which currently only supports one set of memory SPDs. BUG=b:209486790, b:204151079 BRANCH=None TEST=Boot guybrush and nipperkin Change-Id: Ie17025e092f2b9397afea33fce285e80ef5dc995 Signed-off-by: Rob Barnes <robbarnes(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59923 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc M src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt D src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt M src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc M src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt M src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt M src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc M src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt D src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt 9 files changed, 40 insertions(+), 26 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc index 069b2eb..26f27d5 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc @@ -1,8 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/dewatt/memory src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/dewatt/memory src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B -SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-1/spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1 +SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt index 5ce9e79..6a7b18b 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt @@ -1,10 +1,18 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/dewatt/memory src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/dewatt/memory src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt DRAM Part Name ID to assign -K4U6E3S4AB-MGCL 0 (0000) -H54G46CYRBX267 0 (0000) -MT53E1G32D2NP-046 WT:B 1 (0001) -MT53E512M32D1NP-046 WT:B 0 (0000) +MT53E1G32D2NP-046 WT:A 0 (0000) +MT53E512M32D2NP-046 WT:F 1 (0001) +NT6AP256T32AV-J1 2 (0010) +H9HCNNNBKMMLXR-NEE 1 (0001) +MT53E1G32D2NP-046 WT:B 3 (0011) +MT53E512M32D2NP-046 WT:E 1 (0001) +K4U6E3S4AA-MGCR 1 (0001) +H9HCNNNCPMMLXR-NEE 3 (0011) +K4UBE3D4AA-MGCR 3 (0011) +K4U6E3S4AB-MGCL 1 (0001) +H54G46CYRBX267 1 (0001) +MT53E512M32D1NP-046 WT:B 1 (0001) diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt deleted file mode 100644 index 4b6ba22..0000000 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt +++ /dev/null @@ -1,4 +0,0 @@ -K4U6E3S4AB-MGCL -H54G46CYRBX267 -MT53E1G32D2NP-046 WT:B -MT53E512M32D1NP-046 WT:B diff --git a/src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc index 5af83ad..9c40489 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc @@ -5,6 +5,6 @@ SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B SPD_SOURCES += spd/lp4x/set-1/spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1 -SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt index 02c1bf3..44c16e9 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt +++ b/src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt @@ -9,3 +9,10 @@ NT6AP256T32AV-J1 2 (0010) H9HCNNNBKMMLXR-NEE 1 (0001) MT53E1G32D2NP-046 WT:B 3 (0011) +MT53E512M32D2NP-046 WT:E 1 (0001) +K4U6E3S4AA-MGCR 1 (0001) +H9HCNNNCPMMLXR-NEE 3 (0011) +K4UBE3D4AA-MGCR 3 (0011) +K4U6E3S4AB-MGCL 1 (0001) +H54G46CYRBX267 1 (0001) +MT53E512M32D1NP-046 WT:B 1 (0001) diff --git a/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt index b267e53..a91017c 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt +++ b/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt @@ -3,3 +3,10 @@ NT6AP256T32AV-J1 H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:B +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR +H9HCNNNCPMMLXR-NEE +K4UBE3D4AA-MGCR +K4U6E3S4AB-MGCL +H54G46CYRBX267 +MT53E512M32D1NP-046 WT:B diff --git a/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc index b2a552c..71e59b5 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/nipperkin/memory src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/nipperkin/memory src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B SPD_SOURCES += spd/lp4x/set-1/spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1 SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt index af5e980..7920b43 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt +++ b/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/nipperkin/memory src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/nipperkin/memory src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt DRAM Part Name ID to assign MT53E1G32D2NP-046 WT:A 0 (0000) @@ -13,3 +13,6 @@ K4U6E3S4AA-MGCR 1 (0001) H9HCNNNCPMMLXR-NEE 3 (0011) K4UBE3D4AA-MGCR 3 (0011) +K4U6E3S4AB-MGCL 1 (0001) +H54G46CYRBX267 1 (0001) +MT53E512M32D1NP-046 WT:B 1 (0001) diff --git a/src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt deleted file mode 100644 index eb702a6..0000000 --- a/src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt +++ /dev/null @@ -1,9 +0,0 @@ -MT53E1G32D2NP-046 WT:A -MT53E512M32D2NP-046 WT:F -NT6AP256T32AV-J1 -H9HCNNNBKMMLXR-NEE -MT53E1G32D2NP-046 WT:B -MT53E512M32D2NP-046 WT:E -K4U6E3S4AA-MGCR -H9HCNNNCPMMLXR-NEE -K4UBE3D4AA-MGCR -- To view, visit https://review.coreboot.org/c/coreboot/+/59923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie17025e092f2b9397afea33fce285e80ef5dc995 Gerrit-Change-Number: 59923 Gerrit-PatchSet: 2 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume
by Felix Held (Code Review) 08 Dec '21

08 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59929 ) Change subject: soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume ...................................................................... soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume According to https://uefi.org/specs/ACPI/6.4/04_ACPI_Hardware_Specification/ACPI_Hardwar… > For ACPI/legacy systems, when transitioning from the legacy to the G0 > working state this register is cleared by platform firmware prior to > setting the SCI_EN bit (and thus passing control to OSPM). For ACPI > only platforms (where SCI_EN is always set), when transitioning from > either the mechanical off (G3) or soft-off state to the G0 working > state this register is cleared prior to entering the G0 working state. This means we don't want to clear the PM1 register on resume. By clearing it the linux kernel can't correctly increment the wake count when the power button is pressed. The AMD platforms implement the _SWS ACPI methods, but the linux kernel doesn't actually use these methods. BUG=b:172021431 TEST=suspend zork and push power button and verify power button wake_count increments. Verified other wake sources still work. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59929 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/fch.c M src/soc/amd/common/block/cpu/smm/finalize.c M src/soc/amd/picasso/fch.c M src/soc/amd/stoneyridge/romstage.c 4 files changed, 2 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index dd19c31..8cd1212 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -199,7 +199,6 @@ acpi_pm_gpe_add_events_print_events(); gpio_add_events(); - acpi_clear_pm_gpe_status(); gpp_clk_setup(); fch_clk_output_48Mhz(); diff --git a/src/soc/amd/common/block/cpu/smm/finalize.c b/src/soc/amd/common/block/cpu/smm/finalize.c index ec975be..73b2121 100644 --- a/src/soc/amd/common/block/cpu/smm/finalize.c +++ b/src/soc/amd/common/block/cpu/smm/finalize.c @@ -41,6 +41,8 @@ finalize_cores(); if (!acpi_is_wakeup_s3()) { + acpi_clear_pm_gpe_status(); + if (CONFIG(HAVE_SMI_HANDLER)) acpi_disable_sci(); else diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 44acc81..03ba914 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -225,8 +225,6 @@ acpi_pm_gpe_add_events_print_events(); gpio_add_events(); - acpi_clear_pm_gpe_status(); - al2ahb_clock_gate(); gpp_clk_setup(); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index e316d21..c732f75 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -214,6 +214,5 @@ acpi_fill_pm_gpe_state(&state->gpe_state); acpi_pm_gpe_add_events_print_events(); } - acpi_clear_pm_gpe_status(); } ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561 Gerrit-Change-Number: 59929 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume
by Raul Rangel (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Jason Glenesk, Marshall Dawson. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59929 ) Change subject: soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59929/comment/75c49c83_c048aa50 PS1, Line 13: > setting the SCI_EN bit (and thus passing control to OSPM). For ACPI only > this line seems to be a bit too long. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561 Gerrit-Change-Number: 59929 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 08 Dec 2021 19:36:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume
by Raul Rangel (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59929 to look at the new patch set (#2). Change subject: soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume ...................................................................... soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume According to https://uefi.org/specs/ACPI/6.4/04_ACPI_Hardware_Specification/ACPI_Hardwar… > For ACPI/legacy systems, when transitioning from the legacy to the G0 > working state this register is cleared by platform firmware prior to > setting the SCI_EN bit (and thus passing control to OSPM). For ACPI > only platforms (where SCI_EN is always set), when transitioning from > either the mechanical off (G3) or soft-off state to the G0 working > state this register is cleared prior to entering the G0 working state. This means we don't want to clear the PM1 register on resume. By clearing it the linux kernel can't correctly increment the wake count when the power button is pressed. The AMD platforms implement the _SWS ACPI methods, but the linux kernel doesn't actually use these methods. BUG=b:172021431 TEST=suspend zork and push power button and verify power button wake_count increments. Verified other wake sources still work. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561 --- M src/soc/amd/cezanne/fch.c M src/soc/amd/common/block/cpu/smm/finalize.c M src/soc/amd/picasso/fch.c M src/soc/amd/stoneyridge/romstage.c 4 files changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/59929/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561 Gerrit-Change-Number: 59929 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core
by Sridhar Siricilla (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Arthur Heymans, Nico Huber, Tim Wawrzynczak, Paul Menzel, Ravindra, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59359 ) Change subject: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core ...................................................................... Patch Set 9: (3 comments) Patchset: PS3: > Agree. […] Ack File src/soc/intel/common/block/include/intelblocks/acpi.h: https://review.coreboot.org/c/coreboot/+/59359/comment/79aac9cb_c4a57257 PS7, Line 21: /* It gets scaling factor for small and big core */ > Since this has to be implemented per-SoC, I'd add a comment that mentions that and also prefix it wi […] Ack https://review.coreboot.org/c/coreboot/+/59359/comment/fad6be2b_5a5364de PS7, Line 139: bool cpu_is_nominal_freq_supported(void); > Since this has to be implemented per-SoC, I'd add a comment that mentions that and also prefix it wi […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca Gerrit-Change-Number: 59359 Gerrit-PatchSet: 9 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 08 Dec 2021 19:35:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Allow variants to choose CAR setup configuration
by Subrata Banik (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59272 ) Change subject: mb/google/brya: Allow variants to choose CAR setup configuration ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/59272/comment/4e8dadc0_f1eb8641 PS3, Line 134: BOARD_GOOGLE_BRYA0 > Thanks Tim, that would be good data to have @Tim, Ping! -- To view, visit https://review.coreboot.org/c/coreboot/+/59272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe94e6b82739ec65829859271622d904d75e978d Gerrit-Change-Number: 59272 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 08 Dec 2021 19:22:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/releases: Update 4.16 release notes
by Sean Rhodes (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59564 ) Change subject: Documentation/releases: Update 4.16 release notes ...................................................................... Patch Set 2: (2 comments) Patchset: PS2: Thank you! File Documentation/releases/coreboot-4.16-relnotes.md: https://review.coreboot.org/c/coreboot/+/59564/comment/ffbcbb7a_1b4e26f2 PS1, Line 28: > Trailing whitespace Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9675a6a8960d93ae6de285d8b25ffc48a763483e Gerrit-Change-Number: 59564 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 08 Dec 2021 19:20:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/releases: Update 4.16 release notes
by Angel Pons (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Sean Rhodes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59564 ) Change subject: Documentation/releases: Update 4.16 release notes ...................................................................... Patch Set 1: Code-Review+1 (3 comments) Patchset: PS1: > Hey, any chance you could review this please? No problem! File Documentation/releases/coreboot-4.16-relnotes.md: https://review.coreboot.org/c/coreboot/+/59564/comment/cad82e80_2c76c2fe PS1, Line 15: : New mainboards : -------------- : * StarBook Mk V See bullet point right above. https://review.coreboot.org/c/coreboot/+/59564/comment/60bf10f5_c9db4d0f PS1, Line 28: Trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/59564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9675a6a8960d93ae6de285d8b25ffc48a763483e Gerrit-Change-Number: 59564 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Wed, 08 Dec 2021 19:19:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Fix value of SA_DEVFN_CPU_PCIE1_0
by Subrata Banik (Code Review) 08 Dec '21

08 Dec '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59981 ) Change subject: soc/intel/alderlake: Fix value of SA_DEVFN_CPU_PCIE1_0 ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/soc/intel/alderlake/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/59981/comment/5a7803df_ab206135 PS1, Line 29: SA_DEV_SLOT_CPU_1 oops 😭 Its mostly me! -- To view, visit https://review.coreboot.org/c/coreboot/+/59981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d294d681907c51ac5678c9251364d4d6df4329 Gerrit-Change-Number: 59981 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 08 Dec 2021 19:17:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2021