coreboot-gerrit December 2021

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Change in coreboot[master]: soc/intel/tigerlake: Define soc_get_pcie_rp_type
by Felix Held (Code Review) 13 Dec '21

13 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59853 ) Change subject: soc/intel/tigerlake: Define soc_get_pcie_rp_type ...................................................................... soc/intel/tigerlake: Define soc_get_pcie_rp_type In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for Tiger Lake. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59853 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/pcie_rp.h M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/pcie_rp.c 3 files changed, 56 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index f74706e..ff10c51 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -117,4 +117,8 @@ PCIE_RP_PCH, }; +/* For PCIe RTD3 support, each SoC that uses it must implement this function. */ +struct device; /* Not necessary to include all of device/device.h */ +enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev); + #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */ diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 6da5e00..25a1d65 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -34,6 +34,7 @@ ramstage-y += lpm.c ramstage-y += me.c ramstage-y += p2sb.c +ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += soundwire.c diff --git a/src/soc/intel/tigerlake/pcie_rp.c b/src/soc/intel/tigerlake/pcie_rp.c new file mode 100644 index 0000000..a9a6c7f --- /dev/null +++ b/src/soc/intel/tigerlake/pcie_rp.c @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <intelblocks/pcie_rp.h> +#include <soc/pci_devs.h> + +static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_2, .count = 4 }, + { 0 } +}; + +static const struct pcie_rp_group cpu_rp_groups[] = { + { .slot = SA_DEV_SLOT_PEG, .start = 0, .count = 3 }, + { .slot = SA_DEV_SLOT_CPU_PCIE, .start = 0, .count = 1 }, + { 0 } +}; + +static bool is_part_of_group(const struct device *dev, + const struct pcie_rp_group *groups) +{ + if (dev->path.type != DEVICE_PATH_PCI) + return false; + + const unsigned int slot_to_find = PCI_SLOT(dev->path.pci.devfn); + const unsigned int fn_to_find = PCI_FUNC(dev->path.pci.devfn); + const struct pcie_rp_group *group; + unsigned int i; + unsigned int fn; + + for (group = groups; group->count; ++group) { + for (i = 0, fn = rp_start_fn(group); i < group->count; i++, fn++) { + if (slot_to_find == group->slot && fn_to_find == fn) + return true; + } + } + + return false; +} + +enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev) +{ + if (is_part_of_group(dev, pch_lp_rp_groups)) + return PCIE_RP_PCH; + + if (is_part_of_group(dev, cpu_rp_groups)) + return PCIE_RP_CPU; + + return PCIE_RP_UNKNOWN; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 Gerrit-Change-Number: 59853 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/mipi_camera: Add ACPI entry to provide silicon type info
by Felix Held (Code Review) 13 Dec '21

13 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59869 ) Change subject: drivers/intel/mipi_camera: Add ACPI entry to provide silicon type info ...................................................................... drivers/intel/mipi_camera: Add ACPI entry to provide silicon type info Add entry in ACPI table under IPU device to provide silicon type information to IPU driver. IPU kernel driver can decide the type of firmware to load based on this information. BUG=b:207721978 BRANCH=none TEST=Check for the ACPI entry in the SSDT after booting to kernel Change-Id: I4e0af1dd50b9c014cae5454fcd4f9f76d0e0a85f Cq-Depend: chromium:3319905 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59869 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/intel/mipi_camera/camera.c M src/soc/intel/alderlake/Kconfig 2 files changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Sridhar Siricilla: Looks good to me, but someone else must approve diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index a9af25c..ec7f20b 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -5,7 +5,9 @@ #include <acpi/acpi_device.h> #include <acpi/acpigen.h> #include <acpi/acpigen_pci.h> +#include <arch/cpu.h> #include <console/console.h> +#include <cpu/intel/cpu_ids.h> #include <device/i2c_simple.h> #include <device/device.h> #include <device/path.h> @@ -134,6 +136,14 @@ snprintf(name, sizeof(name), "port%u", i); port_name[i] = strdup(name); + if (CONFIG(ACPI_ADL_IPU_ES_SUPPORT)) { + u32 cpu_id = cpu_get_cpuid(); + if (cpu_id == CPUID_ALDERLAKE_A0 || cpu_id == CPUID_ALDERLAKE_A1) + acpi_dp_add_integer(dsd, "is_es", 1); + else + acpi_dp_add_integer(dsd, "is_es", 0); + } + acpi_dp_add_child(dsd, port_name[i], port_table); } diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 89570b1..9e69663 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -28,6 +28,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_ADL_IPU_ES_SUPPORT select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS @@ -339,6 +340,11 @@ help Enables CrashLog. +config ACPI_ADL_IPU_ES_SUPPORT + def_bool n + help + Enables ACPI entry to provide silicon type information to IPU kernel driver. + if STITCH_ME_BIN config CSE_BPDT_VERSION -- To view, visit https://review.coreboot.org/c/coreboot/+/59869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e0af1dd50b9c014cae5454fcd4f9f76d0e0a85f Gerrit-Change-Number: 59869 Gerrit-PatchSet: 6 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tian Shu Qiu <tian.shu.qiu(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src/arch/x86/exit_car: Fix regression on x86_64
by Felix Held (Code Review) 13 Dec '21

13 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59871 ) Change subject: src/arch/x86/exit_car: Fix regression on x86_64 ...................................................................... src/arch/x86/exit_car: Fix regression on x86_64 The commit d023909b "treewide: Disable R_AMD64_32S relocation support" clflush the address stored in _cbmem_top_ptr, which is the same address cbmem_top() returns, instead of clflush _cbmem_top_ptr itself. Fix that by providing the correct address to clflush. Change-Id: If74591e7753cd9c3c097516430a212d416f53e4d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59871 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/arch/x86/exit_car.S 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 527a3cb..9b89ffb 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -62,7 +62,7 @@ btl $CPUID_FEATURE_CLFLUSH_BIT, %edx jnc skip_clflush #if ENV_X86_64 - movabs _cbmem_top_ptr, %rax + movabs $_cbmem_top_ptr, %rax clflush (%rax) #else clflush _cbmem_top_ptr -- To view, visit https://review.coreboot.org/c/coreboot/+/59871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If74591e7753cd9c3c097516430a212d416f53e4d Gerrit-Change-Number: 59871 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: vc/eltan/security/verified_boot/vboot_check.c: Add cbfs_map_compressed()
by Paul Menzel (Code Review) 13 Dec '21

13 Dec '21

Attention is currently required from: Felix Singer, Michał Żygowski, Frans Hendriks, Julius Werner, Arthur Heymans, Wim Vervoorn. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52025 ) Change subject: vc/eltan/security/verified_boot/vboot_check.c: Add cbfs_map_compressed() ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52025/comment/b800ae22_9bc9c2f8 PS3, Line 9: CB:49334 Additionally, please add the git commit hash and summary. -- To view, visit https://review.coreboot.org/c/coreboot/+/52025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc799f49ee198100deab1ecf66336831d9aed415 Gerrit-Change-Number: 52025 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Mon, 13 Dec 2021 13:30:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Update vboot submodule to upstream master
by Yu-Ping Wu (Code Review) 13 Dec '21

13 Dec '21

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen, Julius Werner. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60078 ) Change subject: Update vboot submodule to upstream master ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife75d21ddfa0b956fdf7a638cd53b55b11f6cb7d Gerrit-Change-Number: 60078 Gerrit-PatchSet: 1 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 13 Dec 2021 13:27:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mainboard/google: Add EC_IN_RW to the early gpio table
by Hsuan-ting Chen (Code Review) 13 Dec '21

13 Dec '21

Hsuan-ting Chen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/58156 ) Change subject: [WIP] mainboard/google: Add EC_IN_RW to the early gpio table ...................................................................... Abandoned merged in other CL -- To view, visit https://review.coreboot.org/c/coreboot/+/58156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1bd26b0ed7c0ff23b5fbfa1b641c092c25f921c Gerrit-Change-Number: 58156 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: [DO-NOT-SUBMIT] 3rdparty uprev
by Hsuan-ting Chen (Code Review) 13 Dec '21

13 Dec '21

Hsuan-ting Chen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/58194 ) Change subject: [DO-NOT-SUBMIT] 3rdparty uprev ...................................................................... Abandoned no need now -- To view, visit https://review.coreboot.org/c/coreboot/+/58194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22b2b2e59acf270b6b4f4442282ea13664169259 Gerrit-Change-Number: 58194 Gerrit-PatchSet: 1 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: chromeos: Add an elog for Chrome OS diagnostic boot
by Hsuan-ting Chen (Code Review) 13 Dec '21

13 Dec '21

Attention is currently required from: Hsuan Ting Chen, Jack Rosenthal, Yu-Ping Wu, Aaron Durbin. Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54948 ) Change subject: chromeos: Add an elog for Chrome OS diagnostic boot ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/54948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb675fc431d4c45e4f432b2d12cac6dcfb2d5e3a Gerrit-Change-Number: 54948 Gerrit-PatchSet: 9 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Mon, 13 Dec 2021 13:24:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Update vboot submodule to upstream master
by Hsuan-ting Chen (Code Review) 13 Dec '21

13 Dec '21

Attention is currently required from: Hsuan Ting Chen. Hello Hsuan Ting Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/60078 to review the following change. Change subject: Update vboot submodule to upstream master ...................................................................... Update vboot submodule to upstream master Updating from commit id 13f601fb: 2021-09-24 12:25:24 +0000 - (vboot: boot from miniOS recovery kernels on disk) to commit id 8028cac3: 2021-12-12 11:18:45 +0000 - (Reland "2api: Add vb2_boot_mode in vb2_context denoted the current boot mode") This brings in 36 new commits. Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org> Change-Id: Ife75d21ddfa0b956fdf7a638cd53b55b11f6cb7d --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/60078/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index 13f601f..8028cac 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 13f601fbd4c1b128f333391e4552082594f0ff25 +Subproject commit 8028cac33c9c408f90de9ceffc714a1a0ca9d583 -- To view, visit https://review.coreboot.org/c/coreboot/+/60078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife75d21ddfa0b956fdf7a638cd53b55b11f6cb7d Gerrit-Change-Number: 60078 Gerrit-PatchSet: 1 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: elogtool: Add a subtype under Chrome OS diagnostics event
by Hsuan-ting Chen (Code Review) 13 Dec '21

13 Dec '21

Hsuan-ting Chen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/59578 ) Change subject: elogtool: Add a subtype under Chrome OS diagnostics event ...................................................................... Abandoned Handle this in OS side instead -- To view, visit https://review.coreboot.org/c/coreboot/+/59578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c52d0cefb1a12597b26545014aa41527e99eb13 Gerrit-Change-Number: 59578 Gerrit-PatchSet: 1 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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coreboot-gerrit December 2021