coreboot-gerrit December 2021

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Change in coreboot[master]: mb/google/octopus: add ALC5682I-VS to be supported in the SSFC
by Felix Held (Code Review) 13 Dec '21

13 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59856 ) Change subject: mb/google/octopus: add ALC5682I-VS to be supported in the SSFC ...................................................................... mb/google/octopus: add ALC5682I-VS to be supported in the SSFC Add ALC5682I-VS codec support. ALC5682I-VD/ALC5682I-VS load different hid name depending on SSFC. BUG=b:198722640 BRANCH=octopus TEST=Set CBI SSFC BIT9-11 to select codec, and test audio works Change-Id: I80be12d88e100ce8586371fc49b36447859e24f8 Signed-off-by: Paul Huang <paul2_huang(a)pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59856 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marco Chen <marcochen(a)google.com> --- M src/mainboard/google/octopus/mainboard.c M src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h M src/mainboard/google/octopus/variants/baseboard/nhlt.c 3 files changed, 24 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Marco Chen: Looks good to me, approved diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index 9ffd633..fbebe57 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -62,6 +62,7 @@ /* For RT5682, GPIO 137 should be set as EDGE_BOTH. */ const struct pad_config rt5682_gpio_137 = PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, EDGE_BOTH, INVERT, HIZCRx1, DISPUPD); + enum ssfc_audio_codec codec = ssfc_get_audio_codec(); if (table == NULL || num == 0) return; @@ -72,7 +73,8 @@ * provide override_table right now so it will be returned earlier since * table above is NULL. */ - if (ssfc_get_audio_codec() != SSFC_AUDIO_CODEC_RT5682) + if ((codec != SSFC_AUDIO_CODEC_RT5682) && + (codec != SSFC_AUDIO_CODEC_RT5682_VS)) return; while (num--) { @@ -192,13 +194,26 @@ continue; } - if ((audio_dev->chip_ops == &drivers_i2c_generic_ops) && - (codec == SSFC_AUDIO_CODEC_RT5682)) { + if (audio_dev->chip_ops == &drivers_i2c_generic_ops) { struct drivers_i2c_generic_config *cfg = audio_dev->chip_info; - if (cfg != NULL && !strcmp(cfg->hid, "10EC5682")) { - printk(BIOS_INFO, "enable RT5682.\n"); + if ((cfg != NULL && !strcmp(cfg->hid, "10EC5682")) && + (codec == SSFC_AUDIO_CODEC_RT5682)) { + printk(BIOS_INFO, "enable RT5682 VD.\n"); + continue; + } + + if ((cfg != NULL && !strcmp(cfg->hid, "10EC5682")) && + (codec == SSFC_AUDIO_CODEC_RT5682_VS)) { + cfg->hid = "RTL5682"; + printk(BIOS_INFO, "enable RT5682 VS.\n"); + continue; + } + + if ((cfg != NULL && !strcmp(cfg->hid, "RTL5682")) && + (codec == SSFC_AUDIO_CODEC_RT5682_VS)) { + printk(BIOS_INFO, "enable RT5682 VS.\n"); continue; } } diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h index cef047a..cd160ba 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h @@ -30,6 +30,7 @@ SSFC_AUDIO_CODEC_DA7219, SSFC_AUDIO_CODEC_RT5682, SSFC_AUDIO_CODEC_CS42L42, + SSFC_AUDIO_CODEC_RT5682_VS, }; #define SSFC_AUDIO_CODEC_OFFSET 9 #define SSFC_AUDIO_CODEC_MASK 0x7 diff --git a/src/mainboard/google/octopus/variants/baseboard/nhlt.c b/src/mainboard/google/octopus/variants/baseboard/nhlt.c index 9c9316c..13a40b3 100644 --- a/src/mainboard/google/octopus/variants/baseboard/nhlt.c +++ b/src/mainboard/google/octopus/variants/baseboard/nhlt.c @@ -28,7 +28,9 @@ printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); } - if (CONFIG(NHLT_RT5682) && codec == SSFC_AUDIO_CODEC_RT5682) { + if (CONFIG(NHLT_RT5682) && + (codec == SSFC_AUDIO_CODEC_RT5682 || + codec == SSFC_AUDIO_CODEC_RT5682_VS)) { /* Realtek for Headset codec */ if (!nhlt_soc_add_rt5682(nhlt, AUDIO_LINK_SSP2)) printk(BIOS_ERR, "Added ALC5682 codec.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/59856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80be12d88e100ce8586371fc49b36447859e24f8 Gerrit-Change-Number: 59856 Gerrit-PatchSet: 12 Gerrit-Owner: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: Add Elan touchscreen
by Rob Barnes (Code Review) 13 Dec '21

13 Dec '21

Attention is currently required from: Paul Menzel, Ren Kuo, Kenneth Chan, Karthik Ramasubramanian, Karthikeyan Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59975 ) Change subject: mb/google/guybrush/var/dewatt: Add Elan touchscreen ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28a7f5891e09ffa393c93881be68641d955efdf8 Gerrit-Change-Number: 59975 Gerrit-PatchSet: 8 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Mon, 13 Dec 2021 14:01:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/shuboz: Add fw_config probe for ALC5682-VD & VS
by Felix Held (Code Review) 13 Dec '21

13 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59558 ) Change subject: mb/google/zork/var/shuboz: Add fw_config probe for ALC5682-VD & VS ...................................................................... mb/google/zork/var/shuboz: Add fw_config probe for ALC5682-VD & VS ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name and machine_dev depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:198689479 BRANCH=zork TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I0c78aa166010ffa4d0cacc8a11d418d5a6906749 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59558 Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/shuboz/overridetree.cb 2 files changed, 89 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kane Chen: Looks good to me, but someone else must approve Kangheui Won: Looks good to me, approved Reka Norman: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c index d6c5e48..7057a48 100644 --- a/src/mainboard/google/zork/variants/baseboard/helpers.c +++ b/src/mainboard/google/zork/variants/baseboard/helpers.c @@ -55,6 +55,9 @@ /* Audio AMP type */ FW_CONFIG_MASK_AUDIO_AMP = 0x1, FW_CONFIG_SHIFT_AUDIO_AMP = 35, + /* Audio codec type */ + FW_CONFIG_MASK_AUDIO_CODEC_SOURCE = 0x3, + FW_CONFIG_SHIFT_AUDIO_CODEC_SOURCE = 36, }; static int get_fw_config(uint64_t *val) diff --git a/src/mainboard/google/zork/variants/shuboz/overridetree.cb b/src/mainboard/google/zork/variants/shuboz/overridetree.cb index c3cc9e6..32a5e76 100644 --- a/src/mainboard/google/zork/variants/shuboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/shuboz/overridetree.cb @@ -1,4 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later +fw_config + field AUDIO_CODEC_SOURCE 36 37 + option AUDIO_CODEC_ALC5682 0 + option AUDIO_CODEC_ALC5682I_VS 1 + end +end chip soc/amd/picasso @@ -51,6 +57,86 @@ # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit + device ref internal_bridge_a on + device ref acp on + chip drivers/amd/i2s_machine_dev + register "hid" = ""AMDI5682"" + # DMIC select GPIO for ACP machine device + # This GPIO is used to select DMIC0 or DMIC1 by the + # kernel driver. It does not really have a polarity + # since low and high control the selection of DMIC and + # hence does not have an active polarity. + # Kernel driver does not use the polarity field and + # instead treats the GPIO selection as follows: + # Set low (0) = Select DMIC0 + # Set high (1) = Select DMIC1 + register "dmic_select_gpio" = "ACPI_GPIO_OUTPUT(GPIO_67)" + device generic 0.0 on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682 + end + end + chip drivers/amd/i2s_machine_dev + register "hid" = ""10029835"" + # DMIC select GPIO for ACP machine device + # This GPIO is used to select DMIC0 or DMIC1 by the + # kernel driver. It does not really have a polarity + # since low and high control the selection of DMIC and + # hence does not have an active polarity. + # Kernel driver does not use the polarity field and + # instead treats the GPIO selection as follows: + # Set low (0) = Select DMIC0 + # Set high (1) = Select DMIC1 + register "dmic_select_gpio" = "ACPI_GPIO_OUTPUT(GPIO_67)" + device generic 1.0 on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS + end + end + end # Audio + end + device ref lpc_bridge on + chip ec/google/chromeec + device pnp 0c09.0 on + chip ec/google/chromeec/i2c_tunnel + device generic 0.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "uid" = "1" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_84)" + register "property_count" = "2" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + register "property_list[1].type" = "ACPI_DP_TYPE_STRING" + register "property_list[1].name" = ""realtek,mclk-name"" + register "property_list[1].string" = ""oscout1"" + device i2c 1a on end + end + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682 + end + device generic 1.0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "uid" = "1" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_84)" + register "property_count" = "2" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + register "property_list[1].type" = "ACPI_DP_TYPE_STRING" + register "property_list[1].name" = ""realtek,mclk-name"" + register "property_list[1].string" = ""oscout1"" + device i2c 1a on end + end + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS + end + end + end + end + end end # domain device ref i2c_2 on -- To view, visit https://review.coreboot.org/c/coreboot/+/59558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c78aa166010ffa4d0cacc8a11d418d5a6906749 Gerrit-Change-Number: 59558 Gerrit-PatchSet: 15 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Randy Wang <ifanw(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Don't select CPU_INFO_V2 explicitly
by Felix Held (Code Review) 13 Dec '21

13 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60014 ) Change subject: soc/amd/cezanne: Don't select CPU_INFO_V2 explicitly ...................................................................... soc/amd/cezanne: Don't select CPU_INFO_V2 explicitly It's already implied by PARALLEL_MP now. Change-Id: Ia76f1a925b2c0ebbba0bf20b094e716708d540c2 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60014 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index df37a82..2535ab7 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -16,7 +16,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH - select CPU_INFO_V2 select DRIVERS_USB_ACPI select DRIVERS_I2C_DESIGNWARE select DRIVERS_USB_PCI_XHCI -- To view, visit https://review.coreboot.org/c/coreboot/+/60014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia76f1a925b2c0ebbba0bf20b094e716708d540c2 Gerrit-Change-Number: 60014 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Don't select CPU_INFO_V2 explicitly
by Felix Held (Code Review) 13 Dec '21

13 Dec '21

Attention is currently required from: Jason Glenesk, Nico Huber, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60014 ) Change subject: soc/amd/cezanne: Don't select CPU_INFO_V2 explicitly ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia76f1a925b2c0ebbba0bf20b094e716708d540c2 Gerrit-Change-Number: 60014 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Mon, 13 Dec 2021 14:00:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Add PSP_S0I3_RESUME_VERSTAGE Kconfig option
by Rob Barnes (Code Review) 13 Dec '21

13 Dec '21

Attention is currently required from: Jason Glenesk, Nico Huber, Raul Rangel, Marshall Dawson, Felix Held. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60024 ) Change subject: mb/google/guybrush: Add PSP_S0I3_RESUME_VERSTAGE Kconfig option ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Ah, so there's hardware init because verstage runs before the bootblock, […] bootblock is not running during s0i3 resume, just verstage. On AMD, S0i3 is only entered after explicit request from Kernel. The kernel needs to send a shutdown command to the TPM before reset is asserted so the TPM state can be preserved and restored. -- To view, visit https://review.coreboot.org/c/coreboot/+/60024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c185f787c1e77bd09f6cbbb1f47deb665ed0c79 Gerrit-Change-Number: 60024 Gerrit-PatchSet: 2 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 13 Dec 2021 13:59:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Implement function to map physical port to EC port
by Felix Held (Code Review) 13 Dec '21

13 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59666 ) Change subject: soc/intel/alderlake: Implement function to map physical port to EC port ...................................................................... soc/intel/alderlake: Implement function to map physical port to EC port Currently coreboot and EC had different logic to interpret TCSS port number which would break retimer update functionality since coreboot would pass wrong port information to EC. To correct this, coreboot has implemented function which converts coreboot physical port mapping to EC's abstract port mapping. Each SoC needs to implement this weak function since only SoC will have correct physical port mapping data. This function should resolve issue of port mismatch since coreboot will count only enabled ports and provide correct EC port number in return. BUG=b:207057940 BRANCH=None TEST=Check if retimer update works on Redrix and correct port information is passed to EC. Change-Id: I3735b7c7794b46123aba3beac8c0268ce72d658c Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59666 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/retimer.c 2 files changed, 33 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 6962ab2..d2c48b7 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -39,6 +39,7 @@ ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += reset.c +ramstage-y += retimer.c ramstage-y += soundwire.c ramstage-y += systemagent.c ramstage-y += vr_config.c diff --git a/src/soc/intel/alderlake/retimer.c b/src/soc/intel/alderlake/retimer.c new file mode 100644 index 0000000..09bf112 --- /dev/null +++ b/src/soc/intel/alderlake/retimer.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <device/device.h> +#include <drivers/intel/usb4/retimer/retimer.h> +#include <intelblocks/tcss.h> + +int retimer_get_index_for_typec(uint8_t typec_port) +{ + int ec_port = 0; + + const struct device *tcss_port_arr[] = { + DEV_PTR(tcss_usb3_port1), + DEV_PTR(tcss_usb3_port2), + DEV_PTR(tcss_usb3_port3), + DEV_PTR(tcss_usb3_port4), + }; + + for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) { + if (i == typec_port) { + printk(BIOS_ERR, "USB Type-C %d mapped to EC port %d\n", typec_port, + ec_port); + return ec_port; + } + + if (is_dev_enabled(tcss_port_arr[i])) + ec_port++; + } + + // Code should not come here if typec_port input is correct + return -1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3735b7c7794b46123aba3beac8c0268ce72d658c Gerrit-Change-Number: 59666 Gerrit-PatchSet: 16 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/usb4/retimer: Add function to correct EC port mapping
by Felix Held (Code Review) 13 Dec '21

13 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59665 ) Change subject: drivers/intel/usb4/retimer: Add function to correct EC port mapping ...................................................................... drivers/intel/usb4/retimer: Add function to correct EC port mapping Currently coreboot interprets TCSS port number as per physical port number while EC abstracts port number and provides indices as port number. For example, if TCSS port 1 and 3 are enabled on the board, coreboot will interpret port numbers as 0 and 2, but since only 2 ports are enabled in the system EC will assign port numbers as 0 and 1. This creates a port number mismatch while communicating between EC and coreboot. This patch addresses issue where SoC can implement function to map correct EC port as per port enabled in mainboard. BUG=b:207057940 BRANCH=None TEST=Check if code compiles successfully. Functionality will work once function is implemented in SoC code. Change-Id: Ia7a5e63838e6529196bd211516e4d665b084f79e Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59665 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/intel/usb4/retimer/retimer.c M src/drivers/intel/usb4/retimer/retimer.h 2 files changed, 36 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c index e549525..8a20ebe 100644 --- a/src/drivers/intel/usb4/retimer/retimer.c +++ b/src/drivers/intel/usb4/retimer/retimer.c @@ -341,6 +341,7 @@ static char dfp[DEVICE_PATH_MAX]; struct acpi_pld pld; uint8_t dfp_port, usb_port; + int ec_port = 0; usb4_retimer_scope = acpi_device_scope(dev); if (!usb4_retimer_scope || !config) @@ -365,8 +366,14 @@ usb_device = config->dfp[dfp_port].typec_port; usb_port = usb_device->path.usb.port_id; + ec_port = retimer_get_index_for_typec(usb_port); + if (ec_port == -1) { + printk(BIOS_ERR, "%s: No relative EC port found for TC port %d\n", + __func__, usb_port); + continue; + } /* DFPx */ - snprintf(dfp, sizeof(dfp), "DFP%1d", usb_port); + snprintf(dfp, sizeof(dfp), "DFP%1d", ec_port); acpigen_write_device(dfp); /* _ADR part is for the lane adapter */ acpigen_write_ADR(dfp_port*2 + 1); @@ -396,7 +403,7 @@ /* Return (Buffer (One) { 0x0 }) */ acpigen_write_return_singleton_buffer(0x0); acpigen_pop_len(); - usb4_retimer_write_dsm(usb_port, INTEL_USB4_RETIMER_DSM_UUID, + usb4_retimer_write_dsm(ec_port, INTEL_USB4_RETIMER_DSM_UUID, usb4_retimer_callbacks, ARRAY_SIZE(usb4_retimer_callbacks), (void *)&config->dfp[dfp_port].power_gpio); /* Default case: Return (Buffer (One) { 0x0 }) */ @@ -436,3 +443,20 @@ __weak void ec_retimer_fw_update(uint8_t data) { } + +/* + * This function will convert CPU physical port mapping to abstract + * EC port mapping. + * For example, board might have enabled TCSS port 1 and 3 as per physical + * port mapping. Since only 2 TCSS ports are enabled EC will index it as port 0 + * and port 1. So there will be an issue when coreboot sends command to EC for + * port 3 (with coreboot index of 2). EC will produce an error due to wrong index. + * + * Note: Each SoC code using retimer driver needs to implement this function + * since SoC will have physical port details. + */ +__weak int retimer_get_index_for_typec(uint8_t typec_port) +{ + /* By default assume that retimer port index = Type C port */ + return (int)typec_port; +} diff --git a/src/drivers/intel/usb4/retimer/retimer.h b/src/drivers/intel/usb4/retimer/retimer.h index 5a040a0..ff87c19 100644 --- a/src/drivers/intel/usb4/retimer/retimer.h +++ b/src/drivers/intel/usb4/retimer/retimer.h @@ -30,5 +30,15 @@ const char *ec_retimer_fw_update_path(void); void ec_retimer_fw_update(uint8_t data); +/* + * This function will convert CPU physical port mapping to abstract + * EC port mapping. For example, board might have enabled TCSS port 1 + * and 3 as per physical port mapping. Since only 2 TCSS ports are enabled + * EC will name it as port 0 and port 1. So there will be mismatch when + * coreboot sends index for port 3. + * Each SoC code using retimer driver needs to implement this function + * since SoC will have physical port details. + */ +int retimer_get_index_for_typec(uint8_t typec_port); #endif /* _DRIVERS_INTEL_USB4_RETIMER_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7a5e63838e6529196bd211516e4d665b084f79e Gerrit-Change-Number: 59665 Gerrit-PatchSet: 11 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3
by Felix Held (Code Review) 13 Dec '21

13 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59855 ) Change subject: soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3 ...................................................................... soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3 For additional power savings during RTD3, the PMC can power-gate the ModPHY lanes that are used by the PCH PCIe root ports. Therefore, using the previous PCIe RP-type detection functions, implement ModPHY PG support for the PCH PCIe RPs. This involves: 1) Adding a mutex so only one power resource accesses the PMC registers at a time 2) OperationRegions to access the PMC's PG registers 3) Adding ModPHY PG enable sequence to _OFF 4) Adding ModPHY PG disable sequence to _ON BUG=b:197983574 TEST=50 S0ix suspend/resume cycles on brya0 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I19cb05a74acfa3ded7867b1cac32c161a83b4f7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59855 Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Cliff Huang <cliff.huang(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/pcie/rtd3/rtd3.c 1 file changed, 79 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Cliff Huang: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index 816df05..507c3c8 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -9,6 +9,8 @@ #include <device/pci.h> #include <intelblocks/pmc.h> #include <intelblocks/pmc_ipc.h> +#include <intelblocks/pcie_rp.h> +#include <soc/iomap.h> #include "chip.h" /* @@ -42,6 +44,14 @@ #define ACPI_REG_PCI_L23_RDY_DETECT "L23R" /* L23_Rdy Detect Transition */ #define ACPI_REG_PCI_L23_SAVE_STATE "NCB7" /* Scratch bit to save L23 state */ +/* ACPI path to the mutex that protects accesses to PMC ModPhy power gating registers */ +#define RTD3_MUTEX_PATH "\\_SB.PCI0.R3MX" + +enum modphy_pg_state { + PG_DISABLE = 0, + PG_ENABLE = 1, +}; + /* Called from _ON to get PCIe link back to active state. */ static void pcie_rtd3_acpi_l23_exit(void) { @@ -74,12 +84,33 @@ acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_SAVE_STATE); } +/* Called from _ON/_OFF to disable/enable ModPHY power gating */ +static void pcie_rtd3_enable_modphy_pg(unsigned int pcie_rp, enum modphy_pg_state state) +{ + /* Enter the critical section */ + acpigen_emit_ext_op(ACQUIRE_OP); + acpigen_emit_namestring(RTD3_MUTEX_PATH); + acpigen_emit_word(ACPI_MUTEX_NO_TIMEOUT); + + acpigen_write_store_int_to_namestr(state, "EMPG"); + acpigen_write_delay_until_namestr_int(100, "AMPG", state); + + /* Exit the critical section */ + acpigen_emit_ext_op(RELEASE_OP); + acpigen_emit_namestring(RTD3_MUTEX_PATH); +} + static void pcie_rtd3_acpi_method_on(unsigned int pcie_rp, - const struct soc_intel_common_block_pcie_rtd3_config *config) + const struct soc_intel_common_block_pcie_rtd3_config *config, + enum pcie_rp_type rp_type) { acpigen_write_method_serialized("_ON", 0); + /* Disable modPHY power gating for PCH RPs. */ + if (rp_type == PCIE_RP_PCH) + pcie_rtd3_enable_modphy_pg(pcie_rp, PG_DISABLE); + /* Assert enable GPIO to turn on device power. */ if (config->enable_gpio.pin_count) { acpigen_enable_tx_gpio(&config->enable_gpio); @@ -98,7 +129,7 @@ acpigen_write_sleep(config->reset_delay_ms); } - /* Trigger L23 ready exit flow unless disabld by config. */ + /* Trigger L23 ready exit flow unless disabled by config. */ if (!config->disable_l23) pcie_rtd3_acpi_l23_exit(); @@ -107,7 +138,8 @@ static void pcie_rtd3_acpi_method_off(int pcie_rp, - const struct soc_intel_common_block_pcie_rtd3_config *config) + const struct soc_intel_common_block_pcie_rtd3_config *config, + enum pcie_rp_type rp_type) { acpigen_write_method_serialized("_OFF", 0); @@ -122,6 +154,10 @@ acpigen_write_sleep(config->reset_off_delay_ms); } + /* Enable modPHY power gating for PCH RPs */ + if (rp_type == PCIE_RP_PCH) + pcie_rtd3_enable_modphy_pg(pcie_rp, PG_ENABLE); + /* Disable SRCCLK for this root port if pin is defined. */ if (config->srcclk_pin >= 0) pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, false); @@ -165,8 +201,31 @@ acpigen_pop_len(); /* Method */ } +static void write_modphy_opregion(unsigned int pcie_rp) +{ + /* The register containing the Power Gate enable sequence bits is at + PCH_PWRM_BASE + 0x10D0, and the bits to check for sequence completion are at + PCH_PWRM_BASE + 0x10D4. */ + const struct opregion opregion = OPREGION("PMCP", SYSTEMMEMORY, + PCH_PWRM_BASE_ADDRESS + 0x1000, 0xff); + const struct fieldlist fieldlist[] = { + FIELDLIST_OFFSET(0xD0), + FIELDLIST_RESERVED(pcie_rp), + FIELDLIST_NAMESTR("EMPG", 1), /* Enable ModPHY Power Gate */ + FIELDLIST_OFFSET(0xD4), + FIELDLIST_RESERVED(pcie_rp), + FIELDLIST_NAMESTR("AMPG", 1), /* Is ModPHY Power Gate active? */ + }; + + acpigen_write_opregion(&opregion); + acpigen_write_field("PMCP", fieldlist, ARRAY_SIZE(fieldlist), + FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE); +} + static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) { + static bool mutex_created = false; + const struct soc_intel_common_block_pcie_rtd3_config *config = config_of(dev); static const char *const power_res_states[] = {"_PR0"}; const struct device *parent = dev->bus->dev; @@ -206,6 +265,8 @@ return; } + const enum pcie_rp_type rp_type = soc_get_pcie_rp_type(parent); + /* Read port number of root port that this device is attached to. */ pcie_rp = pci_read_config8(parent, PCH_PCIE_CFG_LCAP_PN); if (pcie_rp == 0 || pcie_rp > CONFIG_MAX_ROOT_PORTS) { @@ -218,21 +279,34 @@ printk(BIOS_INFO, "%s: Enable RTD3 for %s (%s)\n", scope, dev_path(parent), config->desc ?: dev->chip_ops->name); + /* Create a mutex for exclusive access to the PMC registers. */ + if (rp_type == PCIE_RP_PCH && !mutex_created) { + acpigen_write_scope("\\_SB.PCI0"); + acpigen_write_mutex("R3MX", 0); + acpigen_write_scope_end(); + mutex_created = true; + } + /* The RTD3 power resource is added to the root port, not the device. */ acpigen_write_scope(scope); if (config->desc) acpigen_write_name_string("_DDN", config->desc); + /* Create OpRegions for MMIO accesses. */ acpigen_write_opregion(&opregion); acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist), FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); + /* Create the OpRegion to access the ModPHY PG registers (PCH RPs only) */ + if (rp_type == PCIE_RP_PCH) + write_modphy_opregion(pcie_rp); + /* ACPI Power Resource for controlling the attached device power. */ acpigen_write_power_res("RTD3", 0, 0, power_res_states, ARRAY_SIZE(power_res_states)); pcie_rtd3_acpi_method_status(pcie_rp, config); - pcie_rtd3_acpi_method_on(pcie_rp, config); - pcie_rtd3_acpi_method_off(pcie_rp, config); + pcie_rtd3_acpi_method_on(pcie_rp, config, rp_type); + pcie_rtd3_acpi_method_off(pcie_rp, config, rp_type); acpigen_pop_len(); /* PowerResource */ /* Indicate to the OS that device supports hotplug in D3. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19cb05a74acfa3ded7867b1cac32c161a83b4f7d Gerrit-Change-Number: 59855 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Define soc_get_pcie_rp_type
by Felix Held (Code Review) 13 Dec '21

13 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59854 ) Change subject: soc/intel/alderlake: Define soc_get_pcie_rp_type ...................................................................... soc/intel/alderlake: Define soc_get_pcie_rp_type In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for Alder Lake. While we're here, add PCIe RP group definitions for PCH-M chipsets. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59854 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/pcie_rp.c 3 files changed, 62 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 3ab4d9d..6962ab2 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -22,6 +22,7 @@ romstage-y += meminit.c romstage-y += pcie_rp.c romstage-y += reset.c +romstage-y += cpu.c ramstage-y += acpi.c ramstage-y += chip.c diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index be11527..41b69ef 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -34,7 +34,7 @@ { msr_t msr; - config_t *conf = config_of_soc(); + const config_t *conf = config_of_soc(); msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c index 4ec24c2..dd0cfbc 100644 --- a/src/soc/intel/alderlake/pcie_rp.c +++ b/src/soc/intel/alderlake/pcie_rp.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <device/device.h> #include <intelblocks/pcie_rp.h> +#include <soc/cpu.h> #include <soc/pci_devs.h> #include <soc/pcie.h> @@ -10,9 +12,18 @@ { 0 } }; +static const struct pcie_rp_group pch_m_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 2 }, + { 0 } +}; + const struct pcie_rp_group *get_pch_pcie_rp_table(void) { - return pch_lp_rp_groups; + if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M)) + return pch_m_rp_groups; + + return pch_lp_rp_groups; /* Valid for PCH-P and PCH-N */ } /* @@ -28,7 +39,55 @@ { 0 } }; +static const struct pcie_rp_group cpu_m_rp_groups[] = { + { .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1 }, + { 0 } +}; + +static const struct pcie_rp_group cpu_n_rp_groups[] = { + { 0 } +}; + const struct pcie_rp_group *get_cpu_pcie_rp_table(void) { + if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M)) + return cpu_m_rp_groups; + + if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)) + return cpu_n_rp_groups; + return cpu_rp_groups; } + +static bool is_part_of_group(const struct device *dev, + const struct pcie_rp_group *groups) +{ + if (dev->path.type != DEVICE_PATH_PCI) + return false; + + const unsigned int slot_to_find = PCI_SLOT(dev->path.pci.devfn); + const unsigned int fn_to_find = PCI_FUNC(dev->path.pci.devfn); + const struct pcie_rp_group *group; + unsigned int i; + unsigned int fn; + + for (group = groups; group->count; ++group) { + for (i = 0, fn = rp_start_fn(group); i < group->count; i++, fn++) { + if (slot_to_find == group->slot && fn_to_find == fn) + return true; + } + } + + return false; +} + +enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev) +{ + if (is_part_of_group(dev, pch_lp_rp_groups)) + return PCIE_RP_PCH; + + if (CONFIG_MAX_CPU_ROOT_PORTS && is_part_of_group(dev, cpu_rp_groups)) + return PCIE_RP_CPU; + + return PCIE_RP_UNKNOWN; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 Gerrit-Change-Number: 59854 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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