coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/brya/variants/primus: remove board_id check for ALC5682I-VS
by Tim Wawrzynczak (Code Review) 15 Dec '21

15 Dec '21

Attention is currently required from: Malik Hsu, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60128 ) Change subject: mb/google/brya/variants/primus: remove board_id check for ALC5682I-VS ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60128/comment/104d86cf_1e9946ba PS1, Line 9: Remove the board id check, just keep using fw_config. suggestion: `The board ID check for audio codec is no longer required, therefore remove it.` -- To view, visit https://review.coreboot.org/c/coreboot/+/60128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbe838186da2e64737a9ffb557cf324124e79a9d Gerrit-Change-Number: 60128 Gerrit-PatchSet: 1 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 15 Dec 2021 16:54:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/brask: Disable autonomous GPIO power management
by Tim Wawrzynczak (Code Review) 15 Dec '21

15 Dec '21

Attention is currently required from: Nick Vaccaro, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60100 ) Change subject: mb/google/brya/variants/brask: Disable autonomous GPIO power management ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f18fea5bc28493107c6d4951805de640a0b8ae5 Gerrit-Change-Number: 60100 Gerrit-PatchSet: 2 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Wed, 15 Dec 2021 16:48:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Do not trigger crashlog on all resets by default
by Tim Wawrzynczak (Code Review) 15 Dec '21

15 Dec '21

Attention is currently required from: Francois Toguo Fotso, Paul Menzel, Curtis Chen, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59951 ) Change subject: soc/intel/common: Do not trigger crashlog on all resets by default ...................................................................... Patch Set 4: Code-Review+1 (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59951/comment/2002f0b0_db2e59c9 PS1, Line 9: This feature should : not be enabled by default. > If this feature is enabled, each PMC reset would trigger crashlog. […] Done https://review.coreboot.org/c/coreboot/+/59951/comment/218de70c_ae252d41 PS1, Line 13: apreset > ec command "apreset" suggestion: ``` ls /var/spool/crash/*.bertdump` should be empty after a warm reset ``` Patchset: PS2: > > Do you mind splitting this into two commits, one for the Kconfig, and the other to enable it for A […] I see, this seems OK. File src/soc/intel/common/Kconfig.common: https://review.coreboot.org/c/coreboot/+/59951/comment/0e991d14_12b39416 PS4, Line 87: CrashLog nit: `Crashlog` https://review.coreboot.org/c/coreboot/+/59951/comment/d83dc349_7d326b44 PS4, Line 92: Enable PMC reset crashlog record. suggestion: ``` Enables the PMC to collect crashlog records on every reset event. NOTE: This will result in a BERT table being populated containing a PMC crashlog record on every boot. ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/59951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ec4ff3c8a3799156de030f4556fe6ce61305139 Gerrit-Change-Number: 59951 Gerrit-PatchSet: 4 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 15 Dec 2021 16:47:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Curtis Chen <curtis.chen(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/var/scout: improve USB2 port 4 strengh
by Joe Tessler (Code Review) 15 Dec '21

15 Dec '21

Attention is currently required from: Tim Wawrzynczak, Kenneth Chan. Joe Tessler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60131 ) Change subject: mb/google/hatch/var/scout: improve USB2 port 4 strengh ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: LGTM as the device owner -- To view, visit https://review.coreboot.org/c/coreboot/+/60131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8 Gerrit-Change-Number: 60131 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Joe Tessler <jrt(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 15 Dec 2021 16:39:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: MAINTAINERS: Add libpayload unit-tests to TESTS section
by Felix Singer (Code Review) 15 Dec '21

15 Dec '21

Attention is currently required from: Jakub Czapiga. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60138 ) Change subject: MAINTAINERS: Add libpayload unit-tests to TESTS section ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09aca01d9bb2624983e0d62628aef617c10eba9c Gerrit-Change-Number: 60138 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Comment-Date: Wed, 15 Dec 2021 16:35:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: MAINTAINERS: Add libpayload unit-tests to TESTS section
by Angel Pons (Code Review) 15 Dec '21

15 Dec '21

Attention is currently required from: Jakub Czapiga. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60138 ) Change subject: MAINTAINERS: Add libpayload unit-tests to TESTS section ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09aca01d9bb2624983e0d62628aef617c10eba9c Gerrit-Change-Number: 60138 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Comment-Date: Wed, 15 Dec 2021 16:35:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Denverton-NS boards: Drop useless `thermal.asl`
by Felix Held (Code Review) 15 Dec '21

15 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60103 ) Change subject: Denverton-NS boards: Drop useless `thermal.asl` ...................................................................... Denverton-NS boards: Drop useless `thermal.asl` The code in these files is meaningless, and can be dropped. Change-Id: I11571885059e8d5f930f741172c74b25faa09a15 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60103 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- D src/mainboard/intel/harcuvar/acpi/thermal.asl M src/mainboard/intel/harcuvar/dsdt.asl D src/mainboard/scaleway/tagada/acpi/thermal.asl M src/mainboard/scaleway/tagada/dsdt.asl 4 files changed, 0 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Felix Singer: Looks good to me, approved diff --git a/src/mainboard/intel/harcuvar/acpi/thermal.asl b/src/mainboard/intel/harcuvar/acpi/thermal.asl deleted file mode 100644 index 7425afb..0000000 --- a/src/mainboard/intel/harcuvar/acpi/thermal.asl +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - // Thermal Zone - -Scope (\_TZ) -{ -} diff --git a/src/mainboard/intel/harcuvar/dsdt.asl b/src/mainboard/intel/harcuvar/dsdt.asl index e8dcb78..9eae08e 100644 --- a/src/mainboard/intel/harcuvar/dsdt.asl +++ b/src/mainboard/intel/harcuvar/dsdt.asl @@ -15,9 +15,6 @@ #include "acpi/platform.asl" #include "acpi/mainboard.asl" - // Thermal Handler - #include "acpi/thermal.asl" - // global NVS and variables #include <soc/intel/denverton_ns/acpi/globalnvs.asl> diff --git a/src/mainboard/scaleway/tagada/acpi/thermal.asl b/src/mainboard/scaleway/tagada/acpi/thermal.asl deleted file mode 100644 index 7425afb..0000000 --- a/src/mainboard/scaleway/tagada/acpi/thermal.asl +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - // Thermal Zone - -Scope (\_TZ) -{ -} diff --git a/src/mainboard/scaleway/tagada/dsdt.asl b/src/mainboard/scaleway/tagada/dsdt.asl index e8dcb78..9eae08e 100644 --- a/src/mainboard/scaleway/tagada/dsdt.asl +++ b/src/mainboard/scaleway/tagada/dsdt.asl @@ -15,9 +15,6 @@ #include "acpi/platform.asl" #include "acpi/mainboard.asl" - // Thermal Handler - #include "acpi/thermal.asl" - // global NVS and variables #include <soc/intel/denverton_ns/acpi/globalnvs.asl> 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11571885059e8d5f930f741172c74b25faa09a15 Gerrit-Change-Number: 60103 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/primus{4es}: Configure Acoustic noise mitigation
by Felix Held (Code Review) 15 Dec '21

15 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60071 ) Change subject: mb/google/brya/var/primus{4es}: Configure Acoustic noise mitigation ...................................................................... mb/google/brya/var/primus{4es}: Configure Acoustic noise mitigation - Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to 8 BUG=b:204844399 TEST=USE="project_primus emerge-brya coreboot" and verified the setting meets the audible noise specification Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: I0e0baf78a841278efda912cc5e4e9970329aacf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60071 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb 2 files changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index ef5ad98..58c52a7 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -35,6 +35,12 @@ register "gpio_pm[COMM_5]" = "0" register "SaGv" = "SaGv_Enabled" register "MaxDramSpeed" = "3733" + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb index ce06d30..22d61b0 100644 --- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb @@ -35,6 +35,12 @@ register "gpio_pm[COMM_5]" = "0" register "SaGv" = "SaGv_Enabled" register "MaxDramSpeed" = "3733" + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" # Intel Common SoC Config #+-------------------+---------------------------+ 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e0baf78a841278efda912cc5e4e9970329aacf6 Gerrit-Change-Number: 60071 Gerrit-PatchSet: 3 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mainboard/starlabs/labtop: Hook up Thunderbolt to CMOS
by Felix Held (Code Review) 15 Dec '21

15 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59705 ) Change subject: mainboard/starlabs/labtop: Hook up Thunderbolt to CMOS ...................................................................... mainboard/starlabs/labtop: Hook up Thunderbolt to CMOS Hook up Thunderbolt and related settings to CMOS value of `thunderbolt`. Changes TcssXhciEn, UsbTcPortEn and the relevant PCI devices. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ibadc7464831242ae51982610b410ccf0a6811edd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59705 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Andy Pont <andy.pont(a)sdcsystems.com> --- M src/mainboard/starlabs/labtop/cmos.default M src/mainboard/starlabs/labtop/cmos.layout M src/mainboard/starlabs/labtop/variants/tgl/devtree.c M src/mainboard/starlabs/labtop/variants/tgl/romstage.c 4 files changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Andy Pont: Looks good to me, but someone else must approve diff --git a/src/mainboard/starlabs/labtop/cmos.default b/src/mainboard/starlabs/labtop/cmos.default index b4b2d26..589189f 100644 --- a/src/mainboard/starlabs/labtop/cmos.default +++ b/src/mainboard/starlabs/labtop/cmos.default @@ -14,6 +14,7 @@ microphone=Enable legacy_8254_timer=Enable usb_always_on=Disable +thunderbolt=Disable # EC kbl_timeout=30 seconds fn_ctrl_swap=Disable diff --git a/src/mainboard/starlabs/labtop/cmos.layout b/src/mainboard/starlabs/labtop/cmos.layout index 2601e98..85ec477 100644 --- a/src/mainboard/starlabs/labtop/cmos.layout +++ b/src/mainboard/starlabs/labtop/cmos.layout @@ -30,6 +30,7 @@ 520 1 e 1 microphone 528 1 e 1 legacy_8254_timer 536 1 e 1 usb_always_on +544 1 e 1 thunderbolt # coreboot config options: EC 600 3 e 4 kbl_timeout diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devtree.c b/src/mainboard/starlabs/labtop/variants/tgl/devtree.c index 034877c..42a5aff 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devtree.c +++ b/src/mainboard/starlabs/labtop/variants/tgl/devtree.c @@ -19,6 +19,9 @@ &cfg->power_limits_config[POWER_LIMITS_U_4_CORE]; struct device *nic_dev = pcidev_on_root(0x14, 3); + struct device *tbt_pci_dev = pcidev_on_root(0x07, 0); + struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2); + /* Update PL1 & PL2 based on CMOS settings */ switch (get_uint_option("power_profile", 0)) { @@ -50,4 +53,13 @@ /* Enable/Disable Webcam based on CMOS settings */ if (get_uint_option("webcam", 1) == 0) cfg->usb2_ports[3].enable = 0; + + /* Enable/Disable Thunderbolt based on CMOS settings */ + if (get_uint_option("thunderbolt", 1) == 0) { + cfg->UsbTcPortEn = 0; + cfg->TcssXhciEn = 0; + cfg->TcssD3ColdDisable = 0; + tbt_pci_dev->enabled = 0; + tbt_dma_dev->enabled = 0; + } } diff --git a/src/mainboard/starlabs/labtop/variants/tgl/romstage.c b/src/mainboard/starlabs/labtop/variants/tgl/romstage.c index dae2142..1d65c61 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/romstage.c +++ b/src/mainboard/starlabs/labtop/variants/tgl/romstage.c @@ -33,4 +33,12 @@ const uint8_t ht = get_uint_option("hyper_threading", mupd->FspmConfig.HyperThreading); mupd->FspmConfig.HyperThreading = ht; + + /* Enable/Disable Thunderbolt based on CMOS settings */ + if (get_uint_option("thunderbolt", 1) == 0) { + mupd->FspmConfig.VtdItbtEnable = 0; + mupd->FspmConfig.VtdBaseAddress[3] = 0; + mupd->FspmConfig.TcssDma0En = 0; + mupd->FspmConfig.TcssItbtPcie0En = 0; + } }; -- To view, visit https://review.coreboot.org/c/coreboot/+/59705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibadc7464831242ae51982610b410ccf0a6811edd Gerrit-Change-Number: 59705 Gerrit-PatchSet: 17 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush/var/nipperkin: update LPDDR4X DRAM table
by Felix Held (Code Review) 15 Dec '21

15 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60075 ) Change subject: mb/google/guybrush/var/nipperkin: update LPDDR4X DRAM table ...................................................................... mb/google/guybrush/var/nipperkin: update LPDDR4X DRAM table add Hynix H54G56CYRBX247 support BUG=b:210365851 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage power on successfully Change-Id: I99bed32025d10f62e63ace8f7f23e7cc3a740e93 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60075 Reviewed-by: Rob Barnes <robbarnes(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt M src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc M src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt 3 files changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Rob Barnes: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt index a91017c..361e3f5 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt +++ b/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt @@ -10,3 +10,4 @@ K4U6E3S4AB-MGCL H54G46CYRBX267 MT53E512M32D1NP-046 WT:B +H54G56CYRBX247 diff --git a/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc index 71e59b5..bf8462d 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc @@ -7,4 +7,4 @@ SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B SPD_SOURCES += spd/lp4x/set-1/spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1 -SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR +SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, H54G56CYRBX247 diff --git a/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt index 7920b43..3c38550 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt +++ b/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt @@ -16,3 +16,4 @@ K4U6E3S4AB-MGCL 1 (0001) H54G46CYRBX267 1 (0001) MT53E512M32D1NP-046 WT:B 1 (0001) +H54G56CYRBX247 3 (0011) -- To view, visit https://review.coreboot.org/c/coreboot/+/60075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99bed32025d10f62e63ace8f7f23e7cc3a740e93 Gerrit-Change-Number: 60075 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2021