coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

1 participants
5525 discussions

Change in coreboot[master]: soc/amd/common/block/spi/fch_spi_ctrl: handle failure in execute_command
by Felix Held (Code Review) 15 Dec '21

15 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60119 ) Change subject: soc/amd/common/block/spi/fch_spi_ctrl: handle failure in execute_command ...................................................................... soc/amd/common/block/spi/fch_spi_ctrl: handle failure in execute_command When wait_for_ready returned a timeout, execute_command still ended up returning success. Fix this be returning a failure in this case. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id012e74e26065c12d003793322dcdd448df758b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60119 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/common/block/spi/fch_spi_ctrl.c 1 file changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index aad8de7..33e1139 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -97,9 +97,10 @@ spi_write8(SPI_CMD_TRIGGER, SPI_CMD_TRIGGER_EXECUTE); - if (wait_for_ready()) - printk(BIOS_ERR, - "FCH_SC Error: Timeout executing command\n"); + if (wait_for_ready()) { + printk(BIOS_ERR, "FCH_SC Error: Timeout executing command\n"); + return -1; + } dump_state(SPI_DUMP_STATE_AFTER_CMD); -- To view, visit https://review.coreboot.org/c/coreboot/+/60119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id012e74e26065c12d003793322dcdd448df758b0 Gerrit-Change-Number: 60119 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/amd/common/block/spi/fch_spi_ctrl: rework dump_state
by Felix Held (Code Review) 15 Dec '21

15 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60118 ) Change subject: soc/amd/common/block/spi/fch_spi_ctrl: rework dump_state ...................................................................... soc/amd/common/block/spi/fch_spi_ctrl: rework dump_state Introduce and use enum spi_dump_state_phase to indicate from which phase of the SPI transfer dump_state gets called to print the relevant debug information for that phase. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2f54d4a7eb2f3b9756b77a01533f7c99e8597bfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/60118 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/common/block/spi/fch_spi_ctrl.c 1 file changed, 25 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index d95b642..aad8de7 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -30,7 +30,12 @@ #define SPI_FIFO_RD_PTR_SHIFT 16 #define SPI_FIFO_RD_PTR_MASK 0x7f -static void dump_state(const char *str, u8 phase) +enum spi_dump_state_phase { + SPI_DUMP_STATE_BEFORE_CMD, + SPI_DUMP_STATE_AFTER_CMD, +}; + +static void dump_state(enum spi_dump_state_phase phase) { u8 dump_size; u32 addr; @@ -38,19 +43,33 @@ if (!CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)) return; - printk(BIOS_DEBUG, "SPI: %s\n", str); + switch (phase) { + case SPI_DUMP_STATE_BEFORE_CMD: + printk(BIOS_DEBUG, "SPI: Before execute\n"); + break; + case SPI_DUMP_STATE_AFTER_CMD: + printk(BIOS_DEBUG, "SPI: Transaction finished\n"); + break; + default: /* We shouldn't reach this */ + return; + } + printk(BIOS_DEBUG, "Cntrl0: %x\n", spi_read32(SPI_CNTRL0)); printk(BIOS_DEBUG, "Status: %x\n", spi_read32(SPI_STATUS)); addr = spi_get_bar() + SPI_FIFO; - if (phase == 0) { + + switch (phase) { + case SPI_DUMP_STATE_BEFORE_CMD: dump_size = spi_read8(SPI_TX_BYTE_COUNT); printk(BIOS_DEBUG, "TxByteCount: %x\n", dump_size); printk(BIOS_DEBUG, "CmdCode: %x\n", spi_read8(SPI_CMD_CODE)); - } else { + break; + case SPI_DUMP_STATE_AFTER_CMD: dump_size = spi_read8(SPI_RX_BYTE_COUNT); printk(BIOS_DEBUG, "RxByteCount: %x\n", dump_size); addr += spi_read8(SPI_TX_BYTE_COUNT); + break; } if (dump_size > 0) @@ -74,7 +93,7 @@ static int execute_command(void) { - dump_state("Before execute", 0); + dump_state(SPI_DUMP_STATE_BEFORE_CMD); spi_write8(SPI_CMD_TRIGGER, SPI_CMD_TRIGGER_EXECUTE); @@ -82,7 +101,7 @@ printk(BIOS_ERR, "FCH_SC Error: Timeout executing command\n"); - dump_state("Transaction finished", 1); + dump_state(SPI_DUMP_STATE_AFTER_CMD); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/60118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f54d4a7eb2f3b9756b77a01533f7c99e8597bfa Gerrit-Change-Number: 60118 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/amd/common/include/spi: add Cezanne-specific comment
by Felix Held (Code Review) 15 Dec '21

15 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60117 ) Change subject: soc/amd/common/include/spi: add Cezanne-specific comment ...................................................................... soc/amd/common/include/spi: add Cezanne-specific comment The Cezanne PPR #56569 Rev 3.03 has one more SPI FIFO bytes defined compared to the previous generations. It is unclear if adding some special handling for Cezanne would be worth the effort, since the current code just doesn't use the last byte which should be safe to do, since this only affects the maximum number of bytes that can be used for one SPI transaction. Having another byte to use on Cezanne wouldn't reduce the number of SPI transactions to write a 256 byte data block. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic730f4fe838f59066120c811833995c132c84c1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/60117 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/common/block/include/amdblocks/spi.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index 4efed68..4be3739 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -71,7 +71,7 @@ #define SPI_RD4DW_EN_HOST BIT(15) #define SPI_FIFO 0x80 -#define SPI_FIFO_LAST_BYTE 0xc6 +#define SPI_FIFO_LAST_BYTE 0xc6 /* 0xc7 for Cezanne */ #define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO + 1) struct spi_config { -- To view, visit https://review.coreboot.org/c/coreboot/+/60117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic730f4fe838f59066120c811833995c132c84c1c Gerrit-Change-Number: 60117 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/amd/common/include/spi: fix SPI_FIFO_LAST_BYTE define
by Felix Held (Code Review) 15 Dec '21

15 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60116 ) Change subject: soc/amd/common/include/spi: fix SPI_FIFO_LAST_BYTE define ...................................................................... soc/amd/common/include/spi: fix SPI_FIFO_LAST_BYTE define The last byte of the SPI FIFO SPI_FIFO_LAST_BYTE is at offset 0xc6 of the SPI controller's MMIO region for Stoneyridge and Picasso. Both SPI_FIFO_LAST_BYTE and SPI_FIFO_DEPTH had an off-by-one error that ended up cancelling out each other, so the resulting value for SPI_FIFO_DEPTH isn't changed. TEST=Timeless build results in identical image for Mandolin. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I1676be902ccf57e2e9f69d81251b4315866a0628 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60116 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/common/block/include/amdblocks/spi.h 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index 5c3bd0e..4efed68 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -71,8 +71,8 @@ #define SPI_RD4DW_EN_HOST BIT(15) #define SPI_FIFO 0x80 -#define SPI_FIFO_LAST_BYTE 0xc7 -#define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO) +#define SPI_FIFO_LAST_BYTE 0xc6 +#define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO + 1) struct spi_config { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/60116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1676be902ccf57e2e9f69d81251b4315866a0628 Gerrit-Change-Number: 60116 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: [UNTESTED] soc/amd/cezanne/fch: disable 48MHz output in S0i3
by Felix Held (Code Review) 15 Dec '21

15 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60125 ) Change subject: [UNTESTED] soc/amd/cezanne/fch: disable 48MHz output in S0i3 ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60125/comment/521b6401_39cc3c2b PS1, Line 7: S0i3 > Does this save power? yes, this should save some power in s0i3. see b:210722314 for a bit more context; i mainly pushed this patch in the current state so it can be tested if this helps lowering the s0i3 power consumption -- To view, visit https://review.coreboot.org/c/coreboot/+/60125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If445f5825dc7b795c95d73c061156cc485421ada Gerrit-Change-Number: 60125 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 15 Dec 2021 22:36:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/stoneyridge: split southbridge code
by Felix Held (Code Review) 15 Dec '21

15 Dec '21

Attention is currently required from: Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60142 ) Change subject: soc/amd/stoneyridge: split southbridge code ...................................................................... soc/amd/stoneyridge: split southbridge code Split the southbridge code into a bootblock and a ramstage part to align it more with Picasso and Cezanne. Also move the implementation of fch_clk_output_48Mhz to the end of early_fch.c since it's not really related to the functions that were previously around it. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib660fbef8dc25ba0fab803ccd82b3408878d1588 --- M src/soc/amd/stoneyridge/Makefile.inc A src/soc/amd/stoneyridge/early_fch.c A src/soc/amd/stoneyridge/fch.c D src/soc/amd/stoneyridge/southbridge.c 4 files changed, 373 insertions(+), 369 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/60142/1 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 32c862e..bd009e5 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -8,12 +8,12 @@ bootblock-y += uart.c bootblock-y += BiosCallOuts.c bootblock-y += bootblock.c +bootblock-y += early_fch.c bootblock-y += gpio.c bootblock-y += i2c.c bootblock-y += enable_usbdebug.c bootblock-y += monotonic_timer.c bootblock-y += tsc_freq.c -bootblock-y += southbridge.c romstage-y += BiosCallOuts.c romstage-y += i2c.c @@ -47,10 +47,10 @@ ramstage-y += mca.c ramstage-y += enable_usbdebug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-y += fch.c ramstage-y += fch_agesa.c ramstage-y += gpio.c ramstage-y += monotonic_timer.c -ramstage-y += southbridge.c ramstage-y += northbridge.c ramstage-y += sata.c ramstage-y += memmap.c diff --git a/src/soc/amd/stoneyridge/early_fch.c b/src/soc/amd/stoneyridge/early_fch.c new file mode 100644 index 0000000..1f038f6 --- /dev/null +++ b/src/soc/amd/stoneyridge/early_fch.c @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpimmio.h> +#include <amdblocks/lpc.h> +#include <amdblocks/pmlib.h> +#include <amdblocks/reset.h> +#include <amdblocks/smbus.h> +#include <amdblocks/spi.h> +#include <soc/southbridge.h> +#include <types.h> + +static void sb_enable_lpc(void) +{ + u8 byte; + + /* Enable LPC controller */ + byte = pm_io_read8(PM_LPC_GATING); + byte |= PM_LPC_ENABLE; + pm_io_write8(PM_LPC_GATING, byte); +} + +static void sb_lpc_decode(void) +{ + u32 tmp = 0; + + /* Enable I/O decode to LPC bus */ + tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 + | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 + | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 + | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 + | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 + | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 + | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 + | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 + | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 + | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT + | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT + | DECODE_ENABLE_ADLIB_PORT; + + /* Decode SIOs at 2E/2F and 4E/4F */ + if (CONFIG(STONEYRIDGE_LEGACY_FREE)) + tmp |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE; + + lpc_enable_decode(tmp); +} + +static void setup_spread_spectrum(int *reboot) +{ + uint16_t rstcfg = pm_read16(PWR_RESET_CFG); + + rstcfg &= ~TOGGLE_ALL_PWR_GOOD; + pm_write16(PWR_RESET_CFG, rstcfg); + + uint32_t cntl1 = misc_read32(MISC_CLK_CNTL1); + + if (cntl1 & CG1PLL_FBDIV_TEST) { + printk(BIOS_DEBUG, "Spread spectrum is ready\n"); + misc_write32(MISC_CGPLL_CONFIG1, + misc_read32(MISC_CGPLL_CONFIG1) | + CG1PLL_SPREAD_SPECTRUM_ENABLE); + + return; + } + + printk(BIOS_DEBUG, "Setting up spread spectrum\n"); + + uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6); + cfg6 &= ~CG1PLL_LF_MODE_MASK; + cfg6 |= (0x0f8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK; + misc_write32(MISC_CGPLL_CONFIG6, cfg6); + + uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3); + cfg3 &= ~CG1PLL_REFDIV_MASK; + cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK; + cfg3 &= ~CG1PLL_FBDIV_MASK; + cfg3 |= (0x04b << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK; + misc_write32(MISC_CGPLL_CONFIG3, cfg3); + + uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5); + cfg5 &= ~SS_AMOUNT_NFRAC_SLIP_MASK; + cfg5 |= (0x2 << SS_AMOUNT_NFRAC_SLIP_SHIFT) & SS_AMOUNT_NFRAC_SLIP_MASK; + misc_write32(MISC_CGPLL_CONFIG5, cfg5); + + uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4); + cfg4 &= ~SS_AMOUNT_DSFRAC_MASK; + cfg4 |= (0xd000 << SS_AMOUNT_DSFRAC_SHIFT) & SS_AMOUNT_DSFRAC_MASK; + cfg4 &= ~SS_STEP_SIZE_DSFRAC_MASK; + cfg4 |= (0x02d5 << SS_STEP_SIZE_DSFRAC_SHIFT) + & SS_STEP_SIZE_DSFRAC_MASK; + misc_write32(MISC_CGPLL_CONFIG4, cfg4); + + rstcfg |= TOGGLE_ALL_PWR_GOOD; + pm_write16(PWR_RESET_CFG, rstcfg); + + cntl1 |= CG1PLL_FBDIV_TEST; + misc_write32(MISC_CLK_CNTL1, cntl1); + + *reboot = 1; +} + +static void setup_misc(int *reboot) +{ + /* Undocumented register */ + uint32_t reg = misc_read32(0x50); + if (!(reg & BIT(16))) { + reg |= BIT(16); + + misc_write32(0x50, reg); + *reboot = 1; + } +} + +/* Before console init */ +void bootblock_fch_early_init(void) +{ + int reboot = 0; + + /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access + the GPIO registers. */ + enable_acpimmio_decode_pm04(); + lpc_enable_rom(); + sb_enable_lpc(); + lpc_enable_port80(); + sb_lpc_decode(); + /* Make sure the base address is predictable */ + lpc_set_spibase(SPI_BASE_ADDRESS); + fch_spi_early_init(); + fch_smbus_init(); + fch_enable_cf9_io(); + setup_spread_spectrum(&reboot); + setup_misc(&reboot); + + if (reboot) + warm_reset(); + + fch_enable_legacy_io(); + enable_aoac_devices(); + + /* disable the keyboard reset function before mainboard GPIO setup */ + if (CONFIG(DISABLE_KEYBOARD_RESET_PIN)) + fch_disable_kb_rst(); +} + +/* After console init */ +void bootblock_fch_init(void) +{ + pm_set_power_failure_state(); + fch_print_pmxc0_status(); + show_spi_speeds_and_modes(); +} + +void fch_clk_output_48Mhz(u32 osc) +{ + u32 ctrl; + + /* + * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M) + * or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz. + */ + ctrl = misc_read32(MISC_CLK_CNTL1); + + switch (osc) { + case 1: + ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB; + break; + case 2: + ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB; + break; + default: + return; /* do nothing if invalid */ + } + misc_write32(MISC_CLK_CNTL1, ctrl); +} diff --git a/src/soc/amd/stoneyridge/fch.c b/src/soc/amd/stoneyridge/fch.c new file mode 100644 index 0000000..16802ef --- /dev/null +++ b/src/soc/amd/stoneyridge/fch.c @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <bootstate.h> +#include <cpu/x86/smm.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <cbmem.h> +#include <acpi/acpi_gnvs.h> +#include <amdblocks/amd_pci_util.h> +#include <amdblocks/aoac.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/acpi.h> +#include <amdblocks/smi.h> +#include <soc/southbridge.h> +#include <soc/smi.h> +#include <soc/amd_pci_int_defs.h> +#include <soc/pci_devs.h> +#include <agesa_headers.h> +#include <soc/acpi.h> +#include <soc/aoac_defs.h> +#include <soc/nvs.h> +#include <types.h> + +/* + * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME + * provides a visible association with the index, therefore helping + * maintainability of table. If a new index/name is defined in + * amd_pci_int_defs.h, just add the pair at the end of this table. + * Order is not important. + */ +static const struct irq_idx_name irq_association[] = { + { PIRQ_A, "INTA#" }, + { PIRQ_B, "INTB#" }, + { PIRQ_C, "INTC#" }, + { PIRQ_D, "INTD#" }, + { PIRQ_E, "INTE#" }, + { PIRQ_F, "INTF#" }, + { PIRQ_G, "INTG#" }, + { PIRQ_H, "INTH#" }, + { PIRQ_MISC, "Misc" }, + { PIRQ_MISC0, "Misc0" }, + { PIRQ_MISC1, "Misc1" }, + { PIRQ_MISC2, "Misc2" }, + { PIRQ_SIRQA, "Ser IRQ INTA" }, + { PIRQ_SIRQB, "Ser IRQ INTB" }, + { PIRQ_SIRQC, "Ser IRQ INTC" }, + { PIRQ_SIRQD, "Ser IRQ INTD" }, + { PIRQ_SCI, "SCI" }, + { PIRQ_SMBUS, "SMBUS" }, + { PIRQ_ASF, "ASF" }, + { PIRQ_HDA, "HDA" }, + { PIRQ_FC, "FC" }, + { PIRQ_PMON, "PerMon" }, + { PIRQ_SD, "SD" }, + { PIRQ_SDIO, "SDIOt" }, + { PIRQ_EHCI, "EHCI" }, + { PIRQ_XHCI, "XHCI" }, + { PIRQ_SATA, "SATA" }, + { PIRQ_GPIO, "GPIO" }, + { PIRQ_I2C0, "I2C0" }, + { PIRQ_I2C1, "I2C1" }, + { PIRQ_I2C2, "I2C2" }, + { PIRQ_I2C3, "I2C3" }, + { PIRQ_UART0, "UART0" }, + { PIRQ_UART1, "UART1" }, +}; + +const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) +{ + *size = ARRAY_SIZE(irq_association); + return irq_association; +} + +static void fch_init_acpi_ports(void) +{ + u32 reg; + + /* We use some of these ports in SMM regardless of whether or not + * ACPI tables are generated. Enable these ports indiscriminately. + */ + + pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); + pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); + pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); + pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); + /* CpuControl is in \_SB.CP00, 6 bytes */ + pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); + + if (CONFIG(HAVE_SMI_HANDLER)) { + /* APMC - SMI Command Port */ + pm_write16(PM_ACPI_SMI_CMD, APM_CNT); + configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); + + /* SMI on SlpTyp requires sending SMI before completion + * response of the I/O write. The BKDG also specifies + * clearing ForceStpClkRetry for SMI trapping. + */ + reg = pm_read32(PM_PCI_CTRL); + reg |= FORCE_SLPSTATE_RETRY; + reg &= ~FORCE_STPCLK_RETRY; + pm_write32(PM_PCI_CTRL, reg); + + /* Disable SlpTyp feature */ + reg = pm_read8(PM_RST_CTRL1); + reg &= ~SLPTYPE_CONTROL_EN; + pm_write8(PM_RST_CTRL1, reg); + + configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI); + } else { + pm_write16(PM_ACPI_SMI_CMD, 0); + } + + /* Decode ACPI registers and enable standard features */ + pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD | + PM_ACPI_GLOBAL_EN | + PM_ACPI_RTC_EN_EN | + PM_ACPI_TIMER_EN_EN); +} + +void fch_init(void *chip_info) +{ + fch_init_acpi_ports(); +} + +static void set_sb_aoac(struct aoac_devs *aoac) +{ + const struct device *sd, *sata; + + aoac->ic0e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C0); + aoac->ic1e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C1); + aoac->ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2); + aoac->ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3); + aoac->ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0); + aoac->ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1); + aoac->ehce = is_aoac_device_enabled(FCH_AOAC_DEV_USB2); + aoac->xhce = is_aoac_device_enabled(FCH_AOAC_DEV_USB3); + + /* Rely on these being in sync with devicetree */ + sd = pcidev_path_on_root(SD_DEVFN); + aoac->sd_e = sd && sd->enabled ? 1 : 0; + sata = pcidev_path_on_root(SATA_DEVFN); + aoac->st_e = sata && sata->enabled ? 1 : 0; + aoac->espi = 1; +} + +static void set_sb_gnvs(struct global_nvs *gnvs) +{ + uintptr_t amdfw_rom; + uintptr_t xhci_fw; + uintptr_t fwaddr; + size_t fwsize; + + amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); + xhci_fw = read32((void *)(amdfw_rom + XHCI_FW_SIG_OFFSET)); + + fwaddr = 2 + read16((void *)(xhci_fw + XHCI_FW_ADDR_OFFSET + + XHCI_FW_BOOTRAM_SIZE)); + fwsize = read16((void *)(xhci_fw + XHCI_FW_SIZE_OFFSET + + XHCI_FW_BOOTRAM_SIZE)); + gnvs->fw00 = 0; + gnvs->fw01 = ((32 * KiB) << 16) + 0; + gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE; + gnvs->fw03 = fwsize << 16; + + gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0) + & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; +} + +void fch_final(void *chip_info) +{ + struct global_nvs *gnvs = acpi_get_gnvs(); + if (gnvs) { + set_sb_aoac(&gnvs->aoac); + set_sb_gnvs(gnvs); + } +} + +/* + * Update the PCI devices with a valid IRQ number + * that is set in the mainboard PCI_IRQ structures. + */ +static void set_pci_irqs(void *unused) +{ + /* Write PCI_INTR regs 0xC00/0xC01 */ + write_pci_int_table(); + + /* Write IRQs for all devicetree enabled devices */ + write_pci_cfg_irqs(); +} + +/* + * Hook this function into the PCI state machine + * on entry into BS_DEV_ENABLE. + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c deleted file mode 100644 index f0442e5..0000000 --- a/src/soc/amd/stoneyridge/southbridge.c +++ /dev/null @@ -1,367 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/spi.h> -#include <console/console.h> -#include <device/mmio.h> -#include <bootstate.h> -#include <cpu/x86/smm.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <cbmem.h> -#include <acpi/acpi_gnvs.h> -#include <amdblocks/amd_pci_util.h> -#include <amdblocks/aoac.h> -#include <amdblocks/reset.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/lpc.h> -#include <amdblocks/acpi.h> -#include <amdblocks/pmlib.h> -#include <amdblocks/smbus.h> -#include <amdblocks/smi.h> -#include <soc/southbridge.h> -#include <soc/smi.h> -#include <soc/amd_pci_int_defs.h> -#include <soc/pci_devs.h> -#include <agesa_headers.h> -#include <soc/acpi.h> -#include <soc/aoac_defs.h> -#include <soc/lpc.h> -#include <soc/nvs.h> -#include <types.h> - -/* - * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME - * provides a visible association with the index, therefore helping - * maintainability of table. If a new index/name is defined in - * amd_pci_int_defs.h, just add the pair at the end of this table. - * Order is not important. - */ -static const struct irq_idx_name irq_association[] = { - { PIRQ_A, "INTA#" }, - { PIRQ_B, "INTB#" }, - { PIRQ_C, "INTC#" }, - { PIRQ_D, "INTD#" }, - { PIRQ_E, "INTE#" }, - { PIRQ_F, "INTF#" }, - { PIRQ_G, "INTG#" }, - { PIRQ_H, "INTH#" }, - { PIRQ_MISC, "Misc" }, - { PIRQ_MISC0, "Misc0" }, - { PIRQ_MISC1, "Misc1" }, - { PIRQ_MISC2, "Misc2" }, - { PIRQ_SIRQA, "Ser IRQ INTA" }, - { PIRQ_SIRQB, "Ser IRQ INTB" }, - { PIRQ_SIRQC, "Ser IRQ INTC" }, - { PIRQ_SIRQD, "Ser IRQ INTD" }, - { PIRQ_SCI, "SCI" }, - { PIRQ_SMBUS, "SMBUS" }, - { PIRQ_ASF, "ASF" }, - { PIRQ_HDA, "HDA" }, - { PIRQ_FC, "FC" }, - { PIRQ_PMON, "PerMon" }, - { PIRQ_SD, "SD" }, - { PIRQ_SDIO, "SDIOt" }, - { PIRQ_EHCI, "EHCI" }, - { PIRQ_XHCI, "XHCI" }, - { PIRQ_SATA, "SATA" }, - { PIRQ_GPIO, "GPIO" }, - { PIRQ_I2C0, "I2C0" }, - { PIRQ_I2C1, "I2C1" }, - { PIRQ_I2C2, "I2C2" }, - { PIRQ_I2C3, "I2C3" }, - { PIRQ_UART0, "UART0" }, - { PIRQ_UART1, "UART1" }, -}; - -const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) -{ - *size = ARRAY_SIZE(irq_association); - return irq_association; -} - -static void sb_enable_lpc(void) -{ - u8 byte; - - /* Enable LPC controller */ - byte = pm_io_read8(PM_LPC_GATING); - byte |= PM_LPC_ENABLE; - pm_io_write8(PM_LPC_GATING, byte); -} - -static void sb_lpc_decode(void) -{ - u32 tmp = 0; - - /* Enable I/O decode to LPC bus */ - tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 - | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 - | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 - | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 - | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 - | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 - | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 - | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 - | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 - | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT - | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT - | DECODE_ENABLE_ADLIB_PORT; - - /* Decode SIOs at 2E/2F and 4E/4F */ - if (CONFIG(STONEYRIDGE_LEGACY_FREE)) - tmp |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE; - - lpc_enable_decode(tmp); -} - -void fch_clk_output_48Mhz(u32 osc) -{ - u32 ctrl; - - /* - * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M) - * or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz. - */ - ctrl = misc_read32(MISC_CLK_CNTL1); - - switch (osc) { - case 1: - ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB; - break; - case 2: - ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB; - break; - default: - return; /* do nothing if invalid */ - } - misc_write32(MISC_CLK_CNTL1, ctrl); -} - -static void setup_spread_spectrum(int *reboot) -{ - uint16_t rstcfg = pm_read16(PWR_RESET_CFG); - - rstcfg &= ~TOGGLE_ALL_PWR_GOOD; - pm_write16(PWR_RESET_CFG, rstcfg); - - uint32_t cntl1 = misc_read32(MISC_CLK_CNTL1); - - if (cntl1 & CG1PLL_FBDIV_TEST) { - printk(BIOS_DEBUG, "Spread spectrum is ready\n"); - misc_write32(MISC_CGPLL_CONFIG1, - misc_read32(MISC_CGPLL_CONFIG1) | - CG1PLL_SPREAD_SPECTRUM_ENABLE); - - return; - } - - printk(BIOS_DEBUG, "Setting up spread spectrum\n"); - - uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6); - cfg6 &= ~CG1PLL_LF_MODE_MASK; - cfg6 |= (0x0f8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK; - misc_write32(MISC_CGPLL_CONFIG6, cfg6); - - uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3); - cfg3 &= ~CG1PLL_REFDIV_MASK; - cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK; - cfg3 &= ~CG1PLL_FBDIV_MASK; - cfg3 |= (0x04b << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK; - misc_write32(MISC_CGPLL_CONFIG3, cfg3); - - uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5); - cfg5 &= ~SS_AMOUNT_NFRAC_SLIP_MASK; - cfg5 |= (0x2 << SS_AMOUNT_NFRAC_SLIP_SHIFT) & SS_AMOUNT_NFRAC_SLIP_MASK; - misc_write32(MISC_CGPLL_CONFIG5, cfg5); - - uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4); - cfg4 &= ~SS_AMOUNT_DSFRAC_MASK; - cfg4 |= (0xd000 << SS_AMOUNT_DSFRAC_SHIFT) & SS_AMOUNT_DSFRAC_MASK; - cfg4 &= ~SS_STEP_SIZE_DSFRAC_MASK; - cfg4 |= (0x02d5 << SS_STEP_SIZE_DSFRAC_SHIFT) - & SS_STEP_SIZE_DSFRAC_MASK; - misc_write32(MISC_CGPLL_CONFIG4, cfg4); - - rstcfg |= TOGGLE_ALL_PWR_GOOD; - pm_write16(PWR_RESET_CFG, rstcfg); - - cntl1 |= CG1PLL_FBDIV_TEST; - misc_write32(MISC_CLK_CNTL1, cntl1); - - *reboot = 1; -} - -static void setup_misc(int *reboot) -{ - /* Undocumented register */ - uint32_t reg = misc_read32(0x50); - if (!(reg & BIT(16))) { - reg |= BIT(16); - - misc_write32(0x50, reg); - *reboot = 1; - } -} - -/* Before console init */ -void bootblock_fch_early_init(void) -{ - int reboot = 0; - - /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access - the GPIO registers. */ - enable_acpimmio_decode_pm04(); - lpc_enable_rom(); - sb_enable_lpc(); - lpc_enable_port80(); - sb_lpc_decode(); - /* Make sure the base address is predictable */ - lpc_set_spibase(SPI_BASE_ADDRESS); - fch_spi_early_init(); - fch_smbus_init(); - fch_enable_cf9_io(); - setup_spread_spectrum(&reboot); - setup_misc(&reboot); - - if (reboot) - warm_reset(); - - fch_enable_legacy_io(); - enable_aoac_devices(); - - /* disable the keyboard reset function before mainboard GPIO setup */ - if (CONFIG(DISABLE_KEYBOARD_RESET_PIN)) - fch_disable_kb_rst(); -} - -/* After console init */ -void bootblock_fch_init(void) -{ - pm_set_power_failure_state(); - fch_print_pmxc0_status(); - show_spi_speeds_and_modes(); -} - -static void fch_init_acpi_ports(void) -{ - u32 reg; - - /* We use some of these ports in SMM regardless of whether or not - * ACPI tables are generated. Enable these ports indiscriminately. - */ - - pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); - pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); - pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); - pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); - /* CpuControl is in \_SB.CP00, 6 bytes */ - pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); - - if (CONFIG(HAVE_SMI_HANDLER)) { - /* APMC - SMI Command Port */ - pm_write16(PM_ACPI_SMI_CMD, APM_CNT); - configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); - - /* SMI on SlpTyp requires sending SMI before completion - * response of the I/O write. The BKDG also specifies - * clearing ForceStpClkRetry for SMI trapping. - */ - reg = pm_read32(PM_PCI_CTRL); - reg |= FORCE_SLPSTATE_RETRY; - reg &= ~FORCE_STPCLK_RETRY; - pm_write32(PM_PCI_CTRL, reg); - - /* Disable SlpTyp feature */ - reg = pm_read8(PM_RST_CTRL1); - reg &= ~SLPTYPE_CONTROL_EN; - pm_write8(PM_RST_CTRL1, reg); - - configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI); - } else { - pm_write16(PM_ACPI_SMI_CMD, 0); - } - - /* Decode ACPI registers and enable standard features */ - pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD | - PM_ACPI_GLOBAL_EN | - PM_ACPI_RTC_EN_EN | - PM_ACPI_TIMER_EN_EN); -} - -void fch_init(void *chip_info) -{ - fch_init_acpi_ports(); -} - -static void set_sb_aoac(struct aoac_devs *aoac) -{ - const struct device *sd, *sata; - - aoac->ic0e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C0); - aoac->ic1e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C1); - aoac->ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2); - aoac->ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3); - aoac->ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0); - aoac->ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1); - aoac->ehce = is_aoac_device_enabled(FCH_AOAC_DEV_USB2); - aoac->xhce = is_aoac_device_enabled(FCH_AOAC_DEV_USB3); - - /* Rely on these being in sync with devicetree */ - sd = pcidev_path_on_root(SD_DEVFN); - aoac->sd_e = sd && sd->enabled ? 1 : 0; - sata = pcidev_path_on_root(SATA_DEVFN); - aoac->st_e = sata && sata->enabled ? 1 : 0; - aoac->espi = 1; -} - -static void set_sb_gnvs(struct global_nvs *gnvs) -{ - uintptr_t amdfw_rom; - uintptr_t xhci_fw; - uintptr_t fwaddr; - size_t fwsize; - - amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); - xhci_fw = read32((void *)(amdfw_rom + XHCI_FW_SIG_OFFSET)); - - fwaddr = 2 + read16((void *)(xhci_fw + XHCI_FW_ADDR_OFFSET - + XHCI_FW_BOOTRAM_SIZE)); - fwsize = read16((void *)(xhci_fw + XHCI_FW_SIZE_OFFSET - + XHCI_FW_BOOTRAM_SIZE)); - gnvs->fw00 = 0; - gnvs->fw01 = ((32 * KiB) << 16) + 0; - gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE; - gnvs->fw03 = fwsize << 16; - - gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0) - & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; -} - -void fch_final(void *chip_info) -{ - struct global_nvs *gnvs = acpi_get_gnvs(); - if (gnvs) { - set_sb_aoac(&gnvs->aoac); - set_sb_gnvs(gnvs); - } -} - -/* - * Update the PCI devices with a valid IRQ number - * that is set in the mainboard PCI_IRQ structures. - */ -static void set_pci_irqs(void *unused) -{ - /* Write PCI_INTR regs 0xC00/0xC01 */ - write_pci_int_table(); - - /* Write IRQs for all devicetree enabled devices */ - write_pci_cfg_irqs(); -} - -/* - * Hook this function into the PCI state machine - * on entry into BS_DEV_ENABLE. - */ -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/60142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib660fbef8dc25ba0fab803ccd82b3408878d1588 Gerrit-Change-Number: 60142 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/stonyridge: factor out AGESA-wrapper related FCH functions
by Felix Held (Code Review) 15 Dec '21

15 Dec '21

Attention is currently required from: Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60141 ) Change subject: soc/amd/stonyridge: factor out AGESA-wrapper related FCH functions ...................................................................... soc/amd/stonyridge: factor out AGESA-wrapper related FCH functions Split the code that gets called from the AGESA wrapper from the rest of the FCH/southbridge code that directly interacts with the hardware. Since the remaining parts of southbridge.c aren't used in romstage, drop it from the list of build targets for romstage. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6197add0e1396a82545735653110e1e17bf9c303 --- M src/soc/amd/stoneyridge/Makefile.inc A src/soc/amd/stoneyridge/fch_agesa.c M src/soc/amd/stoneyridge/southbridge.c 3 files changed, 62 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/60141/1 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 9f36b4d..32c862e 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -19,13 +19,13 @@ romstage-y += i2c.c romstage-y += romstage.c romstage-y += enable_usbdebug.c +romstage-y += fch_agesa.c romstage-y += gpio.c romstage-y += monotonic_timer.c romstage-y += smbus_spd.c romstage-y += memmap.c romstage-y += uart.c romstage-y += tsc_freq.c -romstage-y += southbridge.c romstage-y += psp.c verstage-y += gpio.c @@ -47,6 +47,7 @@ ramstage-y += mca.c ramstage-y += enable_usbdebug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-y += fch_agesa.c ramstage-y += gpio.c ramstage-y += monotonic_timer.c ramstage-y += southbridge.c diff --git a/src/soc/amd/stoneyridge/fch_agesa.c b/src/soc/amd/stoneyridge/fch_agesa.c new file mode 100644 index 0000000..ee6ab91 --- /dev/null +++ b/src/soc/amd/stoneyridge/fch_agesa.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/agesawrapper.h> +#include <device/device.h> +#include <soc/pci_devs.h> + +static int is_sata_config(void) +{ + return !((SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) + || (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE)); +} + +static inline int sb_sata_enable(void) +{ + /* True if IDE or AHCI. */ + return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || + (SataAhci == CONFIG_STONEYRIDGE_SATA_MODE); +} + +static inline int sb_ide_enable(void) +{ + /* True if IDE or LEGACY IDE. */ + return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || + (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE); +} + +void SetFchResetParams(FCH_RESET_INTERFACE *params) +{ + const struct device *dev = pcidev_path_on_root(SATA_DEVFN); + params->Xhci0Enable = CONFIG(STONEYRIDGE_XHCI_ENABLE); + if (dev && dev->enabled) { + params->SataEnable = sb_sata_enable(); + params->IdeEnable = sb_ide_enable(); + } else { + params->SataEnable = FALSE; + params->IdeEnable = FALSE; + } +} + +void SetFchEnvParams(FCH_INTERFACE *params) +{ + const struct device *dev = pcidev_path_on_root(SATA_DEVFN); + params->AzaliaController = AzEnable; + params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE; + if (dev && dev->enabled) { + params->SataEnable = is_sata_config(); + params->IdeEnable = !params->SataEnable; + params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == + SataLegacyIde); + } else { + params->SataEnable = FALSE; + params->IdeEnable = FALSE; + params->SataIdeMode = FALSE; + } +} + +void SetFchMidParams(FCH_INTERFACE *params) +{ + SetFchEnvParams(params); +} diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index a5cbb10..f0442e5 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -11,7 +11,6 @@ #include <cbmem.h> #include <acpi/acpi_gnvs.h> #include <amdblocks/amd_pci_util.h> -#include <amdblocks/agesawrapper.h> #include <amdblocks/aoac.h> #include <amdblocks/reset.h> #include <amdblocks/acpimmio.h> @@ -31,61 +30,6 @@ #include <soc/nvs.h> #include <types.h> -static int is_sata_config(void) -{ - return !((SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) - || (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE)); -} - -static inline int sb_sata_enable(void) -{ - /* True if IDE or AHCI. */ - return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || - (SataAhci == CONFIG_STONEYRIDGE_SATA_MODE); -} - -static inline int sb_ide_enable(void) -{ - /* True if IDE or LEGACY IDE. */ - return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || - (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE); -} - -void SetFchResetParams(FCH_RESET_INTERFACE *params) -{ - const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - params->Xhci0Enable = CONFIG(STONEYRIDGE_XHCI_ENABLE); - if (dev && dev->enabled) { - params->SataEnable = sb_sata_enable(); - params->IdeEnable = sb_ide_enable(); - } else { - params->SataEnable = FALSE; - params->IdeEnable = FALSE; - } -} - -void SetFchEnvParams(FCH_INTERFACE *params) -{ - const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - params->AzaliaController = AzEnable; - params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE; - if (dev && dev->enabled) { - params->SataEnable = is_sata_config(); - params->IdeEnable = !params->SataEnable; - params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == - SataLegacyIde); - } else { - params->SataEnable = FALSE; - params->IdeEnable = FALSE; - params->SataIdeMode = FALSE; - } -} - -void SetFchMidParams(FCH_INTERFACE *params) -{ - SetFchEnvParams(params); -} - /* * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME * provides a visible association with the index, therefore helping -- To view, visit https://review.coreboot.org/c/coreboot/+/60141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6197add0e1396a82545735653110e1e17bf9c303 Gerrit-Change-Number: 60141 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/stoneyridge: factor out early AOAC initialization
by Felix Held (Code Review) 15 Dec '21

15 Dec '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60140 ) Change subject: soc/amd/stoneyridge: factor out early AOAC initialization ...................................................................... soc/amd/stoneyridge: factor out early AOAC initialization Factor out enable_aoac_devices out of southbridge.c to aoac.c to align Stoneyridge more with Picasso and Cezanne. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ied4d821138507639cad1794f6c5017b5873b761f --- M src/soc/amd/stoneyridge/Makefile.inc A src/soc/amd/stoneyridge/aoac.c M src/soc/amd/stoneyridge/southbridge.c 3 files changed, 40 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/60140/1 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 7d0b86d..9f36b4d 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -4,6 +4,7 @@ subdirs-y += ../../../cpu/amd/mtrr/ +bootblock-y += aoac.c bootblock-y += uart.c bootblock-y += BiosCallOuts.c bootblock-y += bootblock.c diff --git a/src/soc/amd/stoneyridge/aoac.c b/src/soc/amd/stoneyridge/aoac.c new file mode 100644 index 0000000..7c1d12d --- /dev/null +++ b/src/soc/amd/stoneyridge/aoac.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/aoac.h> +#include <delay.h> +#include <soc/aoac_defs.h> +#include <soc/southbridge.h> +#include <types.h> + +/* + * Table of devices that need their AOAC registers enabled and waited + * upon (usually about .55 milliseconds). Instead of individual delays + * waiting for each device to become available, a single delay will be + * executed. + */ +static const unsigned int aoac_devs[] = { + FCH_AOAC_DEV_UART0 + CONFIG_UART_FOR_CONSOLE * 2, + FCH_AOAC_DEV_AMBA, + FCH_AOAC_DEV_I2C0, + FCH_AOAC_DEV_I2C1, + FCH_AOAC_DEV_I2C2, + FCH_AOAC_DEV_I2C3, +}; + +void enable_aoac_devices(void) +{ + bool status; + int i; + + for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) + power_on_aoac_device(aoac_devs[i]); + + /* Wait for AOAC devices to indicate power and clock OK */ + do { + udelay(100); + status = true; + for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) + status &= is_aoac_device_enabled(aoac_devs[i]); + } while (!status); +} diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 2ffbc92..a5cbb10 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -23,7 +23,6 @@ #include <soc/southbridge.h> #include <soc/smi.h> #include <soc/amd_pci_int_defs.h> -#include <delay.h> #include <soc/pci_devs.h> #include <agesa_headers.h> #include <soc/acpi.h> @@ -32,21 +31,6 @@ #include <soc/nvs.h> #include <types.h> -/* - * Table of devices that need their AOAC registers enabled and waited - * upon (usually about .55 milliseconds). Instead of individual delays - * waiting for each device to become available, a single delay will be - * executed. - */ -static const unsigned int aoac_devs[] = { - FCH_AOAC_DEV_UART0 + CONFIG_UART_FOR_CONSOLE * 2, - FCH_AOAC_DEV_AMBA, - FCH_AOAC_DEV_I2C0, - FCH_AOAC_DEV_I2C1, - FCH_AOAC_DEV_I2C2, - FCH_AOAC_DEV_I2C3, -}; - static int is_sata_config(void) { return !((SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) @@ -152,23 +136,6 @@ return irq_association; } -void enable_aoac_devices(void) -{ - bool status; - int i; - - for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) - power_on_aoac_device(aoac_devs[i]); - - /* Wait for AOAC devices to indicate power and clock OK */ - do { - udelay(100); - status = true; - for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) - status &= is_aoac_device_enabled(aoac_devs[i]); - } while (!status); -} - static void sb_enable_lpc(void) { u8 byte; -- To view, visit https://review.coreboot.org/c/coreboot/+/60140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4d821138507639cad1794f6c5017b5873b761f Gerrit-Change-Number: 60140 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: libpayload/libc/fmap: Implement new FlashMap API
by Julius Werner (Code Review) 15 Dec '21

15 Dec '21

Attention is currently required from: Jakub Czapiga. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59494 ) Change subject: libpayload/libc/fmap: Implement new FlashMap API ...................................................................... Patch Set 7: (4 comments) Patchset: PS7: > I am wondering, why payloads: coreinfo and nvramcui are failing. […] I guess that means that something isn't working right with that include path yet? Have you tried building those payloads locally? Can you repro the issue? File payloads/libpayload/libc/fmap.c: https://review.coreboot.org/c/coreboot/+/59494/comment/e80ae0b7_38a40018 PS6, Line 53: -1 > CB_CBFS_NOT_FOUND has description: "File not found in directory", which indicates, that we are looki […] Okay, probably good enough to just use CB_ERR. File payloads/libpayload/tests/libc/fmap_locate_area-test.c: https://review.coreboot.org/c/coreboot/+/59494/comment/e2dbe51c_dcf2c46d PS6, Line 98: _fmap_cache = NULL; > Because _fmap_cache will be pointing to fmap_buffer, which is allocated on the stack. Hmm... yeah... why does it call free() anyway? I don't see you malloc() it anywhere. File payloads/libpayload/tests/libc/fmap_locate_area-test.c: https://review.coreboot.org/c/coreboot/+/59494/comment/acf1375e_edccad03 PS7, Line 78: u8 fmap_buffer2[sizeof(struct fmap) + 3 * sizeof(struct fmap_area)]; Is this still used? -- To view, visit https://review.coreboot.org/c/coreboot/+/59494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbf9016ce73aa58e17f3ee19920ab83dc6c25abb Gerrit-Change-Number: 59494 Gerrit-PatchSet: 7 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Comment-Date: Wed, 15 Dec 2021 22:00:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: UPSTREAM: google/trogdor: Enable Parade ps8640 edp bridge for pazquel
by Julius Werner (Code Review) 15 Dec '21

15 Dec '21

Attention is currently required from: Henry Sun, Yunlong Jia, Bob Moragues. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60130 ) Change subject: UPSTREAM: google/trogdor: Enable Parade ps8640 edp bridge for pazquel ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60130/comment/744e2e12_035504da PS1, Line 7: UPSTREAM This *is* upstream. You don't need to write UPSTREAM: in front of patch subjects here. File src/mainboard/google/trogdor/mainboard.c: https://review.coreboot.org/c/coreboot/+/60130/comment/a8f4ac47_b824c7f4 PS1, Line 87: 4 Please write as either 0x4 or BIT(2). Also, please put the (... & ...) expression in parenthesis to clarify ordering. -- To view, visit https://review.coreboot.org/c/coreboot/+/60130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6130ee00a0e6f469142f5416627e38c7b5076071 Gerrit-Change-Number: 60130 Gerrit-PatchSet: 1 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kelsey Wang <peihwang(a)qualcomm.corp-partner.google.com> Gerrit-CC: Patrick Chang <changp(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Attention: Bob Moragues <moragues(a)google.com> Gerrit-Comment-Date: Wed, 15 Dec 2021 21:50:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2021