coreboot-gerrit December 2021

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Change in coreboot[master]: mb/intel/adlrvp_n: Add initial code for adl-n variant board
by Felix Held (Code Review) 16 Dec '21

16 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59915 ) Change subject: mb/intel/adlrvp_n: Add initial code for adl-n variant board ...................................................................... mb/intel/adlrvp_n: Add initial code for adl-n variant board This patch adds the following list of changes: 1. Create a new devicetree for adlrvp-n and copy contents of adlrvp-p devictree. 2. Add support for 2 mainboards as ADL-N board with default EC (Windows SKU) and Chrome EC (Chrome SKU) and copy overridetree contents from adlrvp-p. 3. Add mainboard Kconfig to Kconfig.name file 4. Handle mainboard names in Kconfig file for ADLRVP N 5. Add config options to pick the adlrvp_n devicetree Change-Id: I4abf3bf62ec0398ae75e21575a2fab0d44b5c7ad Signed-off-by: Usha P <usha.p(a)intel.com> Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59915 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/Kconfig.name A src/mainboard/intel/adlrvp/devicetree_n.cb A src/mainboard/intel/adlrvp/variants/adlrvp_n/overridetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_n_ext_ec/overridetree.cb 5 files changed, 516 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 498fbc2..cddea56 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -58,6 +58,18 @@ select SOC_INTEL_ALDERLAKE_PCH_M select SPI_TPM +config BOARD_INTEL_ADLRVP_N + select BOARD_INTEL_ADLRVP_COMMON + select DRIVERS_UART_8250IO + select MAINBOARD_USES_IFD_EC_REGION + select SOC_INTEL_ALDERLAKE_PCH_N + +config BOARD_INTEL_ADLRVP_N_EXT_EC + select BOARD_INTEL_ADLRVP_COMMON + select DRIVERS_INTEL_PMC + select INTEL_LPSS_UART_FOR_CONSOLE + select SOC_INTEL_ALDERLAKE_PCH_N + if BOARD_INTEL_ADLRVP_COMMON config CHROMEOS @@ -77,11 +89,14 @@ default "adlrvp_p_mchp" if BOARD_INTEL_ADLRVP_P_MCHP default "adlrvp_m" if BOARD_INTEL_ADLRVP_M default "adlrvp_m_ext_ec" if BOARD_INTEL_ADLRVP_M_EXT_EC + default "adlrvp_n" if BOARD_INTEL_ADLRVP_N + default "adlrvp_n_ext_ec" if BOARD_INTEL_ADLRVP_N_EXT_EC config GBB_HWID string depends on CHROMEOS default "ADLRVPM" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC + default "ADLRVPN" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC default "ADLRVPP" config MAINBOARD_PART_NUMBER @@ -97,6 +112,7 @@ config DEVICETREE default "devicetree_m.cb" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC + default "devicetree_n.cb" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC default "devicetree.cb" config OVERRIDE_DEVICETREE @@ -107,8 +123,8 @@ choice prompt "ON BOARD EC" - default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_M - default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP + default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_N + default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP || BOARD_INTEL_ADLRVP_N_EXT_EC help This option allows you to select the on board EC to use. Select whether the board has Intel EC or Chrome EC diff --git a/src/mainboard/intel/adlrvp/Kconfig.name b/src/mainboard/intel/adlrvp/Kconfig.name index 7ee2c13..c9c56fa 100644 --- a/src/mainboard/intel/adlrvp/Kconfig.name +++ b/src/mainboard/intel/adlrvp/Kconfig.name @@ -12,3 +12,9 @@ config BOARD_INTEL_ADLRVP_M_EXT_EC bool "Alderlake-M RVP with Chrome EC" + +config BOARD_INTEL_ADLRVP_N + bool "Alderlake-N RVP" + +config BOARD_INTEL_ADLRVP_N_EXT_EC + bool "Alderlake-N RVP with Chrome EC" diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb new file mode 100644 index 0000000..cec0422 --- /dev/null +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -0,0 +1,427 @@ +chip soc/intel/alderlake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # Enable HECI1 interface + register "HeciEnabled" = "1" + + # FSP configuration + + # Enable CNVi BT + register "CnviBtCore" = "true" + + # Sagv Configuration + register "SaGv" = "SaGv_Enabled" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port4 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # Enable PCH PCIE RP 5 using CLK 2 + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + # Enable PCH PCIE RP 6 using CLK 5 + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + # Enable PCH PCIE RP 8 using free running CLK (0x80) + # Clock source is shared with LAN and hence marked as free running. + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + + # Enable PCH PCIE RP 9 using CLK 1 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + # Enable PCH PCIE RP 11 for optane + register "pch_pcie_rp[PCH_RP(11)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + + # Hybrid storage mode + register "HybridStorageMode" = "1" + + register "SataSalpSupport" = "1" + + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + + register "SataPortsDevSlp" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + + # Enable EDP in PortA + register "DdiPortAConfig" = "1" + # Enable HDMI in Port B + register "ddi_ports_config" = "{ + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + # TCSS USB3 + register "TcssAuxOri" = "0" + + register "s0ix_enable" = "1" + register "dptf_enable" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" + register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" + register "PchHdaIDispCodecEnable" = "1" + + register "CnviBtAudioOffload" = "true" + + # Intel Common SoC Config + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device ref pcie5 on end + device ref igpu on end + device ref dtt on + chip drivers/intel/dptf + + ## sensor information + register "options.tsr[0].desc" = ""Ambient"" + register "options.tsr[1].desc" = ""Battery"" + register "options.tsr[2].desc" = ""DDR"" + register "options.tsr[3].desc" = ""Skin"" + + ## Active Policy + # TODO: below values are initial reference values only + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(95, 90), + TEMP_PCT(90, 80), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(80, 90), + TEMP_PCT(70, 80), + } + } + }" + + ## Passive Policy + # TODO: below values are initial reference values only + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 50000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 50000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 50000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 85, 50000), + }" + + ## Critical Policy + # TODO: below values are initial reference values only + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN), + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 35000, + .max_power = 45000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 56000, + .max_power = 56000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{2,2}" + register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1"" + register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0"" + register "cio2_prt[0]" = "2" + register "cio2_prt[1]" = "1" + device generic 0 on end + end + end + device ref pcie4_0 on end + device ref pcie4_1 on end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 on end + device ref crashlog off end + device ref tcss_xhci on end + device ref tcss_dma0 on end + device ref tcss_dma1 on end + device ref xhci on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on end + device ref i2c1 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "450000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF VCM"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on end + end + end + device ref i2c2 on end + device ref i2c3 on end + device ref heci1 on end + device ref sata on end + device ref i2c5 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "450000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + end + device ref pcie_rp1 on end + device ref pcie_rp3 on end # W/A to FSP issue + device ref pcie_rp4 on end # W/A to FSP issue + device ref pcie_rp5 on end + device ref pcie_rp6 on end + device ref pcie_rp8 on end + device ref pcie_rp9 on end + device ref pcie_rp11 on end + device ref uart0 on end + device ref gspi0 on end + device ref p2sb on end + device ref hda on + chip drivers/intel/soundwire + device generic 0 on + chip drivers/soundwire/alc711 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on end + end + end + end + end + device ref smbus on end + end +end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_n/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_n/overridetree.cb new file mode 100644 index 0000000..e58e9fb --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_n/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/alderlake + + device domain 0 on end +end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_n_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_n_ext_ec/overridetree.cb new file mode 100644 index 0000000..e78d00f --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_n_ext_ec/overridetree.cb @@ -0,0 +1,61 @@ +chip soc/intel/alderlake + + device domain 0 on + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + use conn2 as mux_conn[2] + device pnp 0c09.0 on end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""TypeC Port 1"" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""TypeC Port 2"" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""TypeC Port 3"" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "1" + register "usb3_port_number" = "1" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "2" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "3" + register "usb3_port_number" = "3" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 2 alias conn2 on end + end + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/59915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4abf3bf62ec0398ae75e21575a2fab0d44b5c7ad Gerrit-Change-Number: 59915 Gerrit-PatchSet: 8 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: [UNTESTED] soc/amd/cezanne/fch: disable 48MHz output in S0i3
by Paul Menzel (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60125 ) Change subject: [UNTESTED] soc/amd/cezanne/fch: disable 48MHz output in S0i3 ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60125/comment/65a54eb9_59bebdec PS1, Line 8: Please add the motivation. -- To view, visit https://review.coreboot.org/c/coreboot/+/60125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If445f5825dc7b795c95d73c061156cc485421ada Gerrit-Change-Number: 60125 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 15 Dec 2021 23:09:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/i8042: Use 'INFO' instead of 'ERROR' when probing failed
by Paul Menzel (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Nico Huber, Nick Vaccaro, Zhuohao Lee. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60129 ) Change subject: libpayload/i8042: Use 'INFO' instead of 'ERROR' when probing failed ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60129/comment/65295ad0_f9d0b671 PS1, Line 9: The probe should output the 'INFO' instead of 'ERROR' when : the i8042 module can't be probed. For the x86 device, which : enables the PC_I8042 by default, the 'ERROR' message will be : outputted if the device doesn't connect to an i8042 keyboard controller. : This is an unexpected error when doing the autotest. Please reflow for 72 characters per line. -- To view, visit https://review.coreboot.org/c/coreboot/+/60129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2880c854b873a2a00aa0d8b1cbb4f86fa8139255 Gerrit-Change-Number: 60129 Gerrit-PatchSet: 1 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Wed, 15 Dec 2021 23:08:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/libc/fmap: Implement new FlashMap API
by Julius Werner (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Jakub Czapiga. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59494 ) Change subject: libpayload/libc/fmap: Implement new FlashMap API ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > No, I cannot reproduce it on my setup. […] Well, the patch is landed now so it should definitely be included in Jenkins builds. Maybe try running `make what-jenkins-does`, see if you can repro it that way? It will take forever but it should try to build everything in the same environment that Jenkins uses. -- To view, visit https://review.coreboot.org/c/coreboot/+/59494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbf9016ce73aa58e17f3ee19920ab83dc6c25abb Gerrit-Change-Number: 59494 Gerrit-PatchSet: 7 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Comment-Date: Wed, 15 Dec 2021 23:04:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Upgrade "relative address" to four address modes
by Felix Held (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Paul Menzel, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59308 ) Change subject: amdfwtool: Upgrade "relative address" to four address modes ...................................................................... Patch Set 12: Code-Review+2 (1 comment) Patchset: PS12: verified that timeless builds result in identical images for guybrush (cezanne), ezkinil (picasso) and barla (stoneyridge) -- To view, visit https://review.coreboot.org/c/coreboot/+/59308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Gerrit-Change-Number: 59308 Gerrit-PatchSet: 12 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Wed, 15 Dec 2021 23:00:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/libc/fmap: Implement new FlashMap API
by Jakub Czapiga (Code Review) 15 Dec '21

15 Dec '21

Attention is currently required from: Julius Werner. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59494 ) Change subject: libpayload/libc/fmap: Implement new FlashMap API ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > I guess that means that something isn't working right with that include path yet? Have you tried bui […] No, I cannot reproduce it on my setup. It looks like patch with commonlib/bsd include paths is not checked out correctly or ignored because of gerrit dependencies somehow. I will look further into that. -- To view, visit https://review.coreboot.org/c/coreboot/+/59494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbf9016ce73aa58e17f3ee19920ab83dc6c25abb Gerrit-Change-Number: 59494 Gerrit-PatchSet: 7 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 15 Dec 2021 22:41:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/psp: move psp_notify_dram to psp_gen1.c
by Felix Held (Code Review) 15 Dec '21

15 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60124 ) Change subject: soc/amd/common/block/psp: move psp_notify_dram to psp_gen1.c ...................................................................... soc/amd/common/block/psp: move psp_notify_dram to psp_gen1.c The MBOX_BIOS_CMD_DRAM_INFO PSP mailbox command is only available on the first generation of PSP mailbox interface and not on the second generation. The second generation of the PSP mailbox interface was introduced with the AMD family 17h SoCs on which the DRAM is already initialized before the x86 cores are released from reset. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I97b29fdc4a71d6493ec63fa60f580778f026ec0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60124 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/psp/psp.c M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_gen1.c 4 files changed, 27 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index e749d75..c9986ca 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -51,6 +51,8 @@ #define PSPSTS_INVALID_NAME 8 #define PSPSTS_INVALID_BLOB 9 +/* PSP gen1-only. SoCs with PSP gen2 already have the DRAM initialized when + the x86 cores are released from reset. */ int psp_notify_dram(void); int psp_notify_smm(void); diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index b955459..66f7d59 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -56,29 +56,6 @@ } /* - * Notify the PSP that DRAM is present. Upon receiving this command, the PSP - * will load its OS into fenced DRAM that is not accessible to the x86 cores. - */ -int psp_notify_dram(void) -{ - int cmd_status; - struct mbox_default_buffer buffer = { - .header = { - .size = sizeof(buffer) - } - }; - - printk(BIOS_DEBUG, "PSP: Notify that DRAM is available... "); - - cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer); - - /* buffer's status shouldn't change but report it if it does */ - psp_print_cmd_status(cmd_status, &buffer.header); - - return cmd_status; -} - -/* * Notify the PSP that the system is completing the boot process. Upon * receiving this command, the PSP will only honor commands where the buffer * is in SMM space. diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index 4d3aca5..5baa064 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -8,7 +8,6 @@ #include <amdblocks/psp.h> /* x86 to PSP commands */ -#define MBOX_BIOS_CMD_DRAM_INFO 0x01 #define MBOX_BIOS_CMD_SMM_INFO 0x02 #define MBOX_BIOS_CMD_SX_INFO 0x03 #define MBOX_BIOS_CMD_SX_INFO_SLEEP_TYPE_MAX 0x07 @@ -19,7 +18,8 @@ #define MBOX_BIOS_CMD_S3_DATA_INFO 0x08 #define MBOX_BIOS_CMD_NOP 0x09 #define MBOX_BIOS_CMD_ABORT 0xfe -/* x86 to PSP commands, v1 */ +/* x86 to PSP commands, v1-only */ +#define MBOX_BIOS_CMD_DRAM_INFO 0x01 #define MBOX_BIOS_CMD_SMU_FW 0x19 #define MBOX_BIOS_CMD_SMU_FW2 0x1a diff --git a/src/soc/amd/common/block/psp/psp_gen1.c b/src/soc/amd/common/block/psp/psp_gen1.c index 55070f2..37257ba 100644 --- a/src/soc/amd/common/block/psp/psp_gen1.c +++ b/src/soc/amd/common/block/psp/psp_gen1.c @@ -170,3 +170,26 @@ cbfs_unmap(blob); return cmd_status; } + +/* + * Notify the PSP that DRAM is present. Upon receiving this command, the PSP + * will load its OS into fenced DRAM that is not accessible to the x86 cores. + */ +int psp_notify_dram(void) +{ + int cmd_status; + struct mbox_default_buffer buffer = { + .header = { + .size = sizeof(buffer) + } + }; + + printk(BIOS_DEBUG, "PSP: Notify that DRAM is available... "); + + cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer); + + /* buffer's status shouldn't change but report it if it does */ + psp_print_cmd_status(cmd_status, &buffer.header); + + return cmd_status; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/60124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97b29fdc4a71d6493ec63fa60f580778f026ec0b Gerrit-Change-Number: 60124 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/spi/spi-generic: document SPI_CNTRLR_DEDUCT_CMD_LEN better
by Felix Held (Code Review) 15 Dec '21

15 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60122 ) Change subject: drivers/spi/spi-generic: document SPI_CNTRLR_DEDUCT_CMD_LEN better ...................................................................... drivers/spi/spi-generic: document SPI_CNTRLR_DEDUCT_CMD_LEN better This should make it a bit clearer what the differences between SPI_CNTRLR_DEDUCT_OPCODE_LEN and SPI_CNTRLR_DEDUCT_CMD_LEN and the corresponding functionality in spi_crop_chunk are. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I809adebb182fc0866b93372b5b486117176da388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60122 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/drivers/spi/spi-generic.c M src/include/spi-generic.h 2 files changed, 6 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 9796663..e6ec7bd 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -98,6 +98,10 @@ if (deduct_opcode_len) cmd_len--; + /* Subtract command length from useable buffer size. If + deduct_opcode_len is set, only subtract the number command bytes + after the opcode. If the adjusted cmd_len is larger than ctrlr_max + return 0 to inidicate an error. */ if (deduct_cmd_len) { if (ctrlr_max >= cmd_len) { ctrlr_max -= cmd_len; diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index 77a3c09..acb22ec 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -111,7 +111,8 @@ enum { /* Deduct the command length from the spi_crop_chunk() calculation for - sizing a transaction. */ + sizing a transaction. If SPI_CNTRLR_DEDUCT_OPCODE_LEN is set, only + the bytes after the command byte will be deducted. */ SPI_CNTRLR_DEDUCT_CMD_LEN = 1 << 0, /* Remove the opcode size from the command length used in the spi_crop_chunk() calculation. Controllers which have a dedicated -- To view, visit https://review.coreboot.org/c/coreboot/+/60122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I809adebb182fc0866b93372b5b486117176da388 Gerrit-Change-Number: 60122 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/spi/spi-generic: fix edge case in spi_crop_chunk
by Felix Held (Code Review) 15 Dec '21

15 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60121 ) Change subject: drivers/spi/spi-generic: fix edge case in spi_crop_chunk ...................................................................... drivers/spi/spi-generic: fix edge case in spi_crop_chunk In the case of deduct_cmd_len being set and the adjusted cmd_len >= ctrlr_max, ctrlr_max wasn't being adjusted and still had the value of ctrlr->max_xfer_size. Handle this edge case (which we should never run into) by setting ctrlr_max to 0 and printing a warning to the console. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9941b2947bb0a44dfae8ee69f509795dfb0cb241 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60121 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/drivers/spi/spi-generic.c 1 file changed, 8 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 116daf9..9796663 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -98,8 +98,14 @@ if (deduct_opcode_len) cmd_len--; - if (deduct_cmd_len && (ctrlr_max > cmd_len)) - ctrlr_max -= cmd_len; + if (deduct_cmd_len) { + if (ctrlr_max >= cmd_len) { + ctrlr_max -= cmd_len; + } else { + ctrlr_max = 0; + printk(BIOS_WARNING, "%s: Command longer than buffer\n", __func__); + } + } return MIN(ctrlr_max, buf_len); } -- To view, visit https://review.coreboot.org/c/coreboot/+/60121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9941b2947bb0a44dfae8ee69f509795dfb0cb241 Gerrit-Change-Number: 60121 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/spi/fch_spi_ctrl: improve printk messages
by Felix Held (Code Review) 15 Dec '21

15 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60120 ) Change subject: soc/amd/common/block/spi/fch_spi_ctrl: improve printk messages ...................................................................... soc/amd/common/block/spi/fch_spi_ctrl: improve printk messages Replace FCH_SC with FCH SPI in the printk messages to make those a bit clearer and also remove an unneeded line break in another printk call. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6ff02163e6a48a2cc8b7fe89b15826e154715d29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60120 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/common/block/spi/fch_spi_ctrl.c 1 file changed, 3 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index 33e1139..f790247 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -98,7 +98,7 @@ spi_write8(SPI_CMD_TRIGGER, SPI_CMD_TRIGGER_EXECUTE); if (wait_for_ready()) { - printk(BIOS_ERR, "FCH_SC Error: Timeout executing command\n"); + printk(BIOS_ERR, "FCH SPI Error: Timeout executing command\n"); return -1; } @@ -121,8 +121,7 @@ const uint8_t *bufout = dout; if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)) - printk(BIOS_DEBUG, "%s(%zx, %zx)\n", __func__, bytesout, - bytesin); + printk(BIOS_DEBUG, "%s(%zx, %zx)\n", __func__, bytesout, bytesin); /* First byte is cmd which cannot be sent through FIFO */ cmd = bufout[0]; @@ -136,7 +135,7 @@ * and followed by other SPI commands. */ if (bytesout + bytesin > SPI_FIFO_DEPTH) { - printk(BIOS_WARNING, "FCH_SC: Too much to transfer, code error!\n"); + printk(BIOS_WARNING, "FCH SPI: Too much to transfer, code error!\n"); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/60120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ff02163e6a48a2cc8b7fe89b15826e154715d29 Gerrit-Change-Number: 60120 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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