coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: drivers/intel/pmc_mux/conn: Change usb{23}_port_number fields to devi...
by Nico Huber (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Reka Norman, Jeremy Soller, Nick Vaccaro, Angel Pons, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60143 ) Change subject: drivers/intel/pmc_mux/conn: Change usb{23}_port_number fields to device pointers ...................................................................... Patch Set 2: (1 comment) File src/drivers/intel/pmc_mux/conn/conn.c: https://review.coreboot.org/c/coreboot/+/60143/comment/83a49504_06cdd960 PS2, Line 60: path.usb.port_id + 1 > Idea: Put this into a helper function: […] NB. I'm wondering though, why are they off-by-one in the first place? IOW why do we put the wrong numbers in the chipset devicetree? -- To view, visit https://review.coreboot.org/c/coreboot/+/60143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5045b8ea57e8ca6f9ebd7d68a19486736b7e2809 Gerrit-Change-Number: 60143 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 17 Dec 2021 13:58:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/block/cse: Move EOP early in boot sequence
by Maulik V Vaghela (Code Review) 17 Dec '21

17 Dec '21

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60195 ) Change subject: intel/common/block/cse: Move EOP early in boot sequence ...................................................................... intel/common/block/cse: Move EOP early in boot sequence Earlier while trying to optimize boot time EOP time kept increasing when boot time reduced.This was because CSE was busy. When EOP was moved later in boot stage it again created issue since CSE was busy with loading other payload, it delayed response to EOP command. In order to meet timing requirement, coreboot has to send EOP in stage when CSE is done with firmware init and it will be ready to serve EOP as soon as possible.This also aligns with previous flow where FSP used to send EOP once silicon init is done and coreboot used to rely on FSP to send this message. Moving EOP to BS_DEV_INIT boot state meets this requirement and CSE EOP time reduces from ~60 ms to ~20 ms on Brya QS board. Also removing commands to set CSE active/idle state since now EOP is being sent before HECI disable. BUG=b:211085685 BRANCH=None TEST=Tested on Brya system before and after the changes. Observed ~40ms savings in boot time. Change-Id: I9c7fe6f8f3fadb68310d4a09692f51f82c737c35 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/common/block/cse/cse_eop.c 1 file changed, 8 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/60195/1 diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 4e1c563..321f918 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -196,26 +196,19 @@ return; } - set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE); timestamp_add_now(TS_ME_BEFORE_END_OF_POST); handle_cse_eop_result(cse_send_eop()); timestamp_add_now(TS_ME_AFTER_END_OF_POST); - - set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE); } /* - * Ideally, to give coreboot maximum flexibility, sending EOP would be done as - * late possible. If HECI_DISABLE_USING_SMM is selected, then sending EOP must - * be performed before the HECI bus is disabled, so these boards use - * BS_PAYLOAD_LOAD, which happens before the HECI_DISABLE_USING_SMM Kconfig takes - * effect (EOP is sent using the HECI bus). - * Otherwise, EOP can be pushed a little later, and can be performed in - * BS_PAYLOAD_BOOT instead. + * Earlier when coreboot used to send EOP at late as possible caused issue + * of delayed response from CSE since CSE was busy loading other payloads. + * To resolve the issue, EOP should be sent early in the boot sequence at + * BS_DEV_INIT or BS_DEV_ENABLE. + * Sending it early meets timing requirement where CSE has not started + * loading payload and serves EOP first. + * This method reduces time to send EOP from ~60 ms to ~20 ms. */ -#if !CONFIG(HECI_DISABLE_USING_SMM) -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, set_cse_end_of_post, NULL); -#else -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, set_cse_end_of_post, NULL); -#endif +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, set_cse_end_of_post, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/60195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c7fe6f8f3fadb68310d4a09692f51f82c737c35 Gerrit-Change-Number: 60195 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/common/rcba_pirq: Use correct size_t length modifier
by Paul Menzel (Code Review) 17 Dec '21

17 Dec '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60194 ) Change subject: sb/intel/common/rcba_pirq: Use correct size_t length modifier ...................................................................... sb/intel/common/rcba_pirq: Use correct size_t length modifier Building an image for the Lenovo T60 with `x86_64-linux-gnu-gcc-11` fails with the format warning below. CC ramstage/southbridge/intel/common/rcba_pirq.o src/southbridge/intel/common/rcba_pirq.c: In function 'intel_acpi_gen_def_acpi_pirq': src/southbridge/intel/common/rcba_pirq.c:86:69: error: format '%ld' expects argument of type 'long int', but argument 5 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] 86 | printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%ld\n", | ~~^ | | | long int | %d 87 | dev_path(dev), int_pin - PCI_INT_A, 88 | pirq_idx(pin_irq_map[map_count].pic_pirq)); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | size_t {aka unsigned int} The return value of `pirq_idx()` is of type `size_t`, so use the appropriate length modifier `z`. Change-Id: I7af24cee536b81e4825b77942bcac75afeb9f476 Found-by: gcc (Debian 11.2.0-13) 11.2.0 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/southbridge/intel/common/rcba_pirq.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/60194/1 diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c index 75dad0d..c9f1518 100644 --- a/src/southbridge/intel/common/rcba_pirq.c +++ b/src/southbridge/intel/common/rcba_pirq.c @@ -83,7 +83,7 @@ pin_irq_map[map_count].pic_pirq = pirq; /* PIRQs are mapped to GSIs starting at 16 */ pin_irq_map[map_count].apic_gsi = 16 + pirq_idx(pirq); - printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%ld\n", + printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%zd\n", dev_path(dev), int_pin - PCI_INT_A, pirq_idx(pin_irq_map[map_count].pic_pirq)); map_count++; -- To view, visit https://review.coreboot.org/c/coreboot/+/60194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7af24cee536b81e4825b77942bcac75afeb9f476 Gerrit-Change-Number: 60194 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/taeko4es: Fix PLD group order (W/A)
by Paul Menzel (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Joey Peng, Tim Wawrzynczak. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60187 ) Change subject: mb/google/brya/var/taeko4es: Fix PLD group order (W/A) ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Please mention the relations to the Linux kernel. -- To view, visit https://review.coreboot.org/c/coreboot/+/60187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff1302fa758bcde1ce8b03c16f7cc6eac807e5c9 Gerrit-Change-Number: 60187 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 17 Dec 2021 12:09:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/acpi: Add support for RTC workaround
by Paul Menzel (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Raul Rangel, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60172 ) Change subject: soc/amd/cezanne/acpi: Add support for RTC workaround ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f14d14df5d30d48d244416f2ec8c10ac5c8040e Gerrit-Change-Number: 60172 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mario Limonciello <mario.limonciello(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 17 Dec 2021 12:08:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/fch: disable 48MHz output in S0i3
by Paul Menzel (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Raul Rangel, Marshall Dawson, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60125 ) Change subject: soc/amd/cezanne/fch: disable 48MHz output in S0i3 ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If445f5825dc7b795c95d73c061156cc485421ada Gerrit-Change-Number: 60125 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 17 Dec 2021 12:06:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/acpimmio/print_reset_status: add missing status bit
by Paul Menzel (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Marshall Dawson, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60184 ) Change subject: soc/amd/common/block/acpimmio/print_reset_status: add missing status bit ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida8b13fe62b16c18fc9924520b83220e73eca624 Gerrit-Change-Number: 60184 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 17 Dec 2021 12:06:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/bugzzy: Initialize display signals on user mode
by Paul Menzel (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: shkim, Henry Sun, SH Kim, Edward Doan, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60190 ) Change subject: mb/google/dedede/var/bugzzy: Initialize display signals on user mode ...................................................................... Patch Set 4: (10 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60190/comment/30f6aee3_bf3da396 PS4, Line 19: new touch screen firmware Which version exactly? https://review.coreboot.org/c/coreboot/+/60190/comment/b82336cc_0b45853c PS4, Line 20: Please add the delay the current code adds. Seems like over 100 ms? File src/mainboard/google/dedede/variants/bugzzy/ramstage.c: https://review.coreboot.org/c/coreboot/+/60190/comment/90a62cbf_cbea63c7 PS4, Line 17: * Bugzzy uses panel-built-in touch screen, it needs : * to set panel power and reset signal to high for touch : * screen to work. : * On user mode, coreboot doesn't initialize graphics : * since there is no screen display before OS. We would : * add this WA to initialize required signals on user mode. Please reflow for 80 (or 96) characters per line. https://review.coreboot.org/c/coreboot/+/60190/comment/6d7d556c_44c16c9f PS4, Line 33: addr32 = 0xc0010000; // IGD MMIO BASE Add define or enum? https://review.coreboot.org/c/coreboot/+/60190/comment/bdc6920a_1aac7598 PS4, Line 37: // clear bit3 ~ bit0 Not needed. https://review.coreboot.org/c/coreboot/+/60190/comment/150e55b7_6a9a3866 PS4, Line 47: udelay(20 * 1000); // delay 20ms Please mention the datasheet name, revision and section requiring this. The current comment is not needed. https://review.coreboot.org/c/coreboot/+/60190/comment/197a94d9_bcfa91b9 PS4, Line 47: udelay(20 * 1000); mdelay(20) https://review.coreboot.org/c/coreboot/+/60190/comment/b71e0bdb_82c8e748 PS4, Line 49: //reset high Space after //. https://review.coreboot.org/c/coreboot/+/60190/comment/cbf7a5ae_82e5e797 PS4, Line 59: //reset low Ditto. https://review.coreboot.org/c/coreboot/+/60190/comment/3ca2293a_6014e871 PS4, Line 69: //reset high Ditto. -- To view, visit https://review.coreboot.org/c/coreboot/+/60190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4d16deb932f43ae1ab33ff5b4e74120ab670db Gerrit-Change-Number: 60190 Gerrit-PatchSet: 4 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Edward Doan <edoan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: shkim <sh_.kim(a)samsung.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Edward Doan <edoan(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 17 Dec 2021 12:02:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/var/scout: improve USB2 port 4 strength
by Kenneth Chan (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Rehan Ghori. Hello build bot (Jenkins), Tim Wawrzynczak, Joe Tessler, Rehan Ghori, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60131 to look at the new patch set (#7). Change subject: mb/google/hatch/var/scout: improve USB2 port 4 strength ...................................................................... mb/google/hatch/var/scout: improve USB2 port 4 strength Set USB2 port 4 pre emphasis to 15mV for passing USB2 port 4 SI (margin eye diagram). BUG=b:210755120 TEST=emerge-ambassadorcoreboot chromeos-bootimage; Build local fw and pass to HW for measuring USB2 port 4 eye diagram. Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8 --- M src/mainboard/google/hatch/variants/scout/overridetree.cb 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/60131/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/60131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8 Gerrit-Change-Number: 60131 Gerrit-PatchSet: 7 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Joe Tessler <jrt(a)google.com> Gerrit-Reviewer: Rehan Ghori <rehang(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rehan Ghori <rehang(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/hatch/var/scout: improve USB2 port 4 strength
by Kenneth Chan (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Rehan Ghori. Kenneth Chan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60131 ) Change subject: mb/google/hatch/var/scout: improve USB2 port 4 strength ...................................................................... Patch Set 6: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60131/comment/e8d6abfc_662aea78 PS1, Line 7: strengh > strength Done https://review.coreboot.org/c/coreboot/+/60131/comment/a02b9ef3_4154e23b PS1, Line 8: > What is the problem? What devices do not work? USB2 port4 SI eye diagram measuring. https://review.coreboot.org/c/coreboot/+/60131/comment/c6499476_aa9d94cf PS1, Line 9: to 15mv > From what value? (What was it before?) […] Default USB2_PORT_LONG is 3mV. I builded several testing BIOS for HW measuring USB2 P4 eye diagram. It's from HW's feedback. https://review.coreboot.org/c/coreboot/+/60131/comment/73204495_84db66f4 PS1, Line 9: mv > mV Done File src/mainboard/google/hatch/variants/scout/overridetree.cb: https://review.coreboot.org/c/coreboot/+/60131/comment/766e7d2c_6a0b4e90 PS1, Line 50: ,, > this is causing a compilation failure Done -- To view, visit https://review.coreboot.org/c/coreboot/+/60131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8 Gerrit-Change-Number: 60131 Gerrit-PatchSet: 6 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Joe Tessler <jrt(a)google.com> Gerrit-Reviewer: Rehan Ghori <rehang(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rehan Ghori <rehang(a)google.com> Gerrit-Comment-Date: Fri, 17 Dec 2021 11:22:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit December 2021