coreboot-gerrit December 2021

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Change in coreboot[master]: mb/google/zork: use full path of SoC's chip.h
by Felix Held (Code Review) 17 Dec '21

17 Dec '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60202 ) Change subject: mb/google/zork: use full path of SoC's chip.h ...................................................................... mb/google/zork: use full path of SoC's chip.h Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I50d8c45e711dc62afe6f80e0f66422bcc9924dfd --- M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/shuboz/variant.c M src/mainboard/google/zork/variants/vilboz/variant.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/60202/1 diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 38c5d4a..09d5786 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -7,8 +7,8 @@ #include <boardid.h> #include <ec/google/chromeec/ec.h> #include <FspmUpd.h> +#include <soc/amd/picasso/chip.h> #include <soc/platform_descriptors.h> -#include "chip.h" const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); /* diff --git a/src/mainboard/google/zork/variants/shuboz/variant.c b/src/mainboard/google/zork/variants/shuboz/variant.c index 9907c72..b0a6b7e 100644 --- a/src/mainboard/google/zork/variants/shuboz/variant.c +++ b/src/mainboard/google/zork/variants/shuboz/variant.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <soc/amd/picasso/chip.h> #include <soc/pci_devs.h> -#include "chip.h" uint32_t usb_oc_map_override[USB_PORT_COUNT] = { USB_OC_PIN_0, diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c index 43ca0e5..ddfce69 100644 --- a/src/mainboard/google/zork/variants/vilboz/variant.c +++ b/src/mainboard/google/zork/variants/vilboz/variant.c @@ -4,7 +4,7 @@ #include <soc/pci_devs.h> #include <fw_config.h> #include <sar.h> -#include "chip.h" +#include <soc/amd/picasso/chip.h> static const fsp_ddi_descriptor hdmi_ddi_descriptors[] = { { // DDI0, DP0, eDP -- To view, visit https://review.coreboot.org/c/coreboot/+/60202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50d8c45e711dc62afe6f80e0f66422bcc9924dfd Gerrit-Change-Number: 60202 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/bilby,mandolin: use full path of SoC's chip.h
by Felix Held (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Aaron Durbin. Hello Jason Glenesk, Marshall Dawson, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60200 to look at the new patch set (#2). Change subject: mb/amd/bilby,mandolin: use full path of SoC's chip.h ...................................................................... mb/amd/bilby,mandolin: use full path of SoC's chip.h This is taken from CB:41355 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iba1948ae2332788b7e0ec9b4e3cea35c6608b152 --- M src/mainboard/amd/bilby/mainboard.c M src/mainboard/amd/mandolin/mainboard.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/60200/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba1948ae2332788b7e0ec9b4e3cea35c6608b152 Gerrit-Change-Number: 60200 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush/dewatt: update DRAM ID table
by Paul Menzel (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Kenneth Chan. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60090 ) Change subject: mb/google/guybrush/dewatt: update DRAM ID table ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt: https://review.coreboot.org/c/coreboot/+/60090/comment/2f0a862c_a0c153c9 PS2, Line 19: H54G56CYRBX247 This is not mentioned? Add it (fix it up) in a separate commit? -- To view, visit https://review.coreboot.org/c/coreboot/+/60090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5ece849a86c75be5af9bc0393090b5f1e33bfed Gerrit-Change-Number: 60090 Gerrit-PatchSet: 2 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 17 Dec 2021 18:39:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: remove root of SoC directory from include path
by Felix Held (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Aaron Durbin. Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/60201 to review the following change. Change subject: soc/amd: remove root of SoC directory from include path ...................................................................... soc/amd: remove root of SoC directory from include path We shouldn't be providing -I include paths to the root of the soc specific directory. It allows for lazy includes that can collide, but there's no way of knowing the winning path since the winning path is determined by Makefile.inc parsing order. This is taken from CB:41355 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I45ed219e4e0cccf3d4f04cc70dc1ef77c518afff --- M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Makefile.inc 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/60201/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 7db4719..de16da4 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -54,7 +54,6 @@ smm-y += gpio.c smm-y += smu.c -CPPFLAGS_common += -I$(src)/soc/amd/picasso CPPFLAGS_common += -I$(src)/soc/amd/picasso/include CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 7d0b86d..16d1eaa 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -66,7 +66,6 @@ smm-y += gpio.c smm-y += psp.c -CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/60201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45ed219e4e0cccf3d4f04cc70dc1ef77c518afff Gerrit-Change-Number: 60201 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/bilby,mandolin: use full path of SoC's chip.h
by Felix Held (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Aaron Durbin. Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/60200 to review the following change. Change subject: mb/amd/bilby,mandolin: use full path of SoC's chip.h ...................................................................... mb/amd/bilby,mandolin: use full path of SoC's chip.h This is taken from CB:41355 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iba1948ae2332788b7e0ec9b4e3cea35c6608b152 --- M src/mainboard/amd/bilby/mainboard.c M src/mainboard/amd/mandolin/mainboard.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/60200/1 diff --git a/src/mainboard/amd/bilby/mainboard.c b/src/mainboard/amd/bilby/mainboard.c index bc91630..009d3c3 100644 --- a/src/mainboard/amd/bilby/mainboard.c +++ b/src/mainboard/amd/bilby/mainboard.c @@ -12,7 +12,7 @@ #include <soc/platform_descriptors.h> #include <types.h> #include <commonlib/helpers.h> -#include <chip.h> +#include <soc/amd/stoneyridge/chip.h> #include "gpio.h" #include "mainboard.h" diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c index a66db78..3f9a3c9 100644 --- a/src/mainboard/amd/mandolin/mainboard.c +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -10,7 +10,7 @@ #include <soc/pci_devs.h> #include <types.h> #include <commonlib/helpers.h> -#include <chip.h> +#include <soc/amd/stoneyridge/chip.h> #include "gpio.h" /* TODO: recheck IRQ tables */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba1948ae2332788b7e0ec9b4e3cea35c6608b152 Gerrit-Change-Number: 60200 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/stoneyridge/include/southbridge: remove unneeded chip.h include
by Felix Held (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60199 ) Change subject: soc/amd/stoneyridge/include/southbridge: remove unneeded chip.h include ...................................................................... soc/amd/stoneyridge/include/southbridge: remove unneeded chip.h include Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9b37efc89e505c2de99536b59e7d7e2bb1d54bff --- M src/soc/amd/stoneyridge/include/soc/southbridge.h 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/60199/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 2773751..e00bf8e 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -7,7 +7,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <soc/iomap.h> -#include "chip.h" /* * AcpiMmio Region -- To view, visit https://review.coreboot.org/c/coreboot/+/60199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b37efc89e505c2de99536b59e7d7e2bb1d54bff Gerrit-Change-Number: 60199 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/gardenia,padmelon;mb/google/kahlee: use full path of SoC's chip.h
by Felix Held (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Aaron Durbin. Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/60198 to review the following change. Change subject: mb/amd/gardenia,padmelon;mb/google/kahlee: use full path of SoC's chip.h ...................................................................... mb/amd/gardenia,padmelon;mb/google/kahlee: use full path of SoC's chip.h This is taken from CB:41355 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I10a18efb92ac0c3cad31044156e32aa6afe1d4d1 --- M src/mainboard/amd/gardenia/OemCustomize.c M src/mainboard/amd/padmelon/OemCustomize.c M src/mainboard/google/kahlee/OemCustomize.c M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/60198/1 diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c index 210a05b..d86313f 100644 --- a/src/mainboard/amd/gardenia/OemCustomize.c +++ b/src/mainboard/amd/gardenia/OemCustomize.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <chip.h> +#include <soc/amd/stoneyridge/chip.h> #include <amdblocks/agesawrapper.h> #define DIMMS_PER_CHANNEL 2 diff --git a/src/mainboard/amd/padmelon/OemCustomize.c b/src/mainboard/amd/padmelon/OemCustomize.c index 7ea46f8..e65f750 100644 --- a/src/mainboard/amd/padmelon/OemCustomize.c +++ b/src/mainboard/amd/padmelon/OemCustomize.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <chip.h> +#include <soc/amd/stoneyridge/chip.h> #include <amdblocks/agesawrapper.h> #define DIMMS_PER_CHANNEL 1 diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 349fe34..9f37a46 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <chip.h> +#include <soc/amd/stoneyridge/chip.h> #include <amdblocks/agesawrapper.h> #include <gpio.h> #include <console/console.h> diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c index 79fd478..a3dfa15 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c +++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c @@ -2,7 +2,7 @@ #include <amdblocks/agesawrapper.h> #include <variant/gpio.h> -#include <chip.h> +#include <soc/amd/stoneyridge/chip.h> #include <soc/pci_devs.h> static const PCIe_PORT_DESCRIPTOR PortList[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/60198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10a18efb92ac0c3cad31044156e32aa6afe1d4d1 Gerrit-Change-Number: 60198 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/gardenia,padmelon;mb/google/kahlee: add missing soc/gpio includes
by Felix Held (Code Review) 17 Dec '21

17 Dec '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60197 ) Change subject: mb/amd/gardenia,padmelon;mb/google/kahlee: add missing soc/gpio includes ...................................................................... mb/amd/gardenia,padmelon;mb/google/kahlee: add missing soc/gpio includes Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie716633bd7602d5e4a7e186aa9e444b7f70dab56 --- M src/mainboard/amd/gardenia/bootblock/bootblock.c M src/mainboard/amd/gardenia/gpio.h M src/mainboard/amd/gardenia/mainboard.c M src/mainboard/amd/padmelon/bootblock/bootblock.c M src/mainboard/amd/padmelon/gpio.c M src/mainboard/amd/padmelon/mainboard.c M src/mainboard/google/kahlee/mainboard.c 7 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/60197/1 diff --git a/src/mainboard/amd/gardenia/bootblock/bootblock.c b/src/mainboard/amd/gardenia/bootblock/bootblock.c index a480f36..0543c31 100644 --- a/src/mainboard/amd/gardenia/bootblock/bootblock.c +++ b/src/mainboard/amd/gardenia/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <soc/gpio.h> #include <soc/southbridge.h> #include "../gpio.h" diff --git a/src/mainboard/amd/gardenia/gpio.h b/src/mainboard/amd/gardenia/gpio.h index 3e9500d..d01bdfd 100644 --- a/src/mainboard/amd/gardenia/gpio.h +++ b/src/mainboard/amd/gardenia/gpio.h @@ -3,6 +3,8 @@ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H +#include <soc/gpio.h> + const struct soc_amd_gpio *early_gpio_table(size_t *size); const struct soc_amd_gpio *gpio_table(size_t *size); diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index ae72b33..459aeba 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -4,6 +4,7 @@ #include <device/device.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/amd_pci_util.h> +#include <soc/gpio.h> #include <soc/southbridge.h> #include "gpio.h" diff --git a/src/mainboard/amd/padmelon/bootblock/bootblock.c b/src/mainboard/amd/padmelon/bootblock/bootblock.c index c93ef52..f1b6822 100644 --- a/src/mainboard/amd/padmelon/bootblock/bootblock.c +++ b/src/mainboard/amd/padmelon/bootblock/bootblock.c @@ -4,6 +4,7 @@ #include <soc/southbridge.h> #include <amdblocks/lpc.h> #include <device/pci_ops.h> +#include <soc/gpio.h> #include <soc/pci_devs.h> #include <drivers/uart/uart8250reg.h> #include <arch/io.h> diff --git a/src/mainboard/amd/padmelon/gpio.c b/src/mainboard/amd/padmelon/gpio.c index 9c18d30..0de2c0a 100644 --- a/src/mainboard/amd/padmelon/gpio.c +++ b/src/mainboard/amd/padmelon/gpio.c @@ -2,6 +2,7 @@ #include <amdblocks/agesawrapper.h> #include <amdblocks/BiosCallOuts.h> +#include <soc/gpio.h> #include <soc/southbridge.h> #include "gpio.h" diff --git a/src/mainboard/amd/padmelon/mainboard.c b/src/mainboard/amd/padmelon/mainboard.c index 51b0f90..017a1fb 100644 --- a/src/mainboard/amd/padmelon/mainboard.c +++ b/src/mainboard/amd/padmelon/mainboard.c @@ -5,6 +5,7 @@ #include <acpi/acpi.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/amd_pci_util.h> +#include <soc/gpio.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index ffec6a5..e54ac74 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -11,6 +11,7 @@ #include <baseboard/variants.h> #include <boardid.h> #include <smbios.h> +#include <soc/gpio.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> #include <amdblocks/acpimmio.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/60197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie716633bd7602d5e4a7e186aa9e444b7f70dab56 Gerrit-Change-Number: 60197 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Disable GPIO export for Goodix Touchscreen
by Rob Barnes (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Raul Rangel, Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60173 ) Change subject: mb/google/guybrush: Disable GPIO export for Goodix Touchscreen ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d2af41e1d04b98f0e3e19a95d7b91d08ecdf17b Gerrit-Change-Number: 60173 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 17 Dec 2021 17:31:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/dewatt: update DRAM ID table
by Rob Barnes (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Kenneth Chan. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60090 ) Change subject: mb/google/guybrush/dewatt: update DRAM ID table ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5ece849a86c75be5af9bc0393090b5f1e33bfed Gerrit-Change-Number: 60090 Gerrit-PatchSet: 2 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 17 Dec 2021 17:30:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2021