coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

1 participants
5525 discussions

Change in coreboot[master]: soc/amd/common/lpc/espi_util: use enum cb_err type for return values
by Felix Held (Code Review) 18 Dec '21

18 Dec '21

1 0

Change in coreboot[master]: soc/amd/common/lpc/espi_util: use enum cb_err type for return values
by Felix Held (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60207 ) Change subject: soc/amd/common/lpc/espi_util: use enum cb_err type for return values ...................................................................... soc/amd/common/lpc/espi_util: use enum cb_err type for return values Use enum cb_err as return type of all functions that aren't exposed outside of this compilation unit. The checks if a function has returned a failure are replaced with checks if the return value isn't CB_SUCCESS which is equivalent if only those two values are used, but also detects a failure if any unexpected value would be returned. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If8c703f62babac31948d0878e91bd31b31bebc01 --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 70 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/60207/1 diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index d495a0e..e27167a 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -426,7 +426,7 @@ } __packed; /* Wait up to ESPI_CMD_TIMEOUT_US for hardware to clear DNCMD_STATUS bit. */ -static int espi_wait_ready(void) +static enum cb_err espi_wait_ready(void) { struct stopwatch sw; union espi_txhdr0 hdr0; @@ -435,10 +435,10 @@ do { hdr0.val = espi_read32(ESPI_DN_TX_HDR0); if (!hdr0.cmd_sts) - return 0; + return CB_SUCCESS; } while (!stopwatch_expired(&sw)); - return -1; + return CB_ERR; } /* Clear interrupt status register */ @@ -453,7 +453,7 @@ * Wait up to ESPI_CMD_TIMEOUT_US for interrupt status register to update after sending a * command. */ -static int espi_poll_status(uint32_t *status) +static enum cb_err espi_poll_status(uint32_t *status) { struct stopwatch sw; @@ -461,12 +461,12 @@ do { *status = espi_read32(ESPI_SLAVE0_INT_STS); if (*status) - return 0; + return CB_SUCCESS; } while (!stopwatch_expired(&sw)); printk(BIOS_ERR, "Error: eSPI timed out waiting for status update.\n"); - return -1; + return CB_ERR; } static void espi_show_failure(const struct espi_cmd *cmd, const char *str, uint32_t status) @@ -476,7 +476,7 @@ printk(BIOS_ERR, "%s (Status = 0x%x)\n", str, status); } -static int espi_send_command(const struct espi_cmd *cmd) +static enum cb_err espi_send_command(const struct espi_cmd *cmd) { uint32_t status; @@ -484,9 +484,9 @@ printk(BIOS_DEBUG, "eSPI cmd0-cmd2: %08x %08x %08x data: %08x.\n", cmd->hdr0.val, cmd->hdr1.val, cmd->hdr2.val, cmd->data.val); - if (espi_wait_ready() == -1) { + if (espi_wait_ready() != CB_SUCCESS) { espi_show_failure(cmd, "Error: eSPI was not ready to accept a command", 0); - return -1; + return CB_ERR; } espi_clear_status(); @@ -498,36 +498,36 @@ /* Dword 0 must be last as this write triggers the transaction */ espi_write32(ESPI_DN_TX_HDR0, cmd->hdr0.val); - if (espi_wait_ready() == -1) { + if (espi_wait_ready() != CB_SUCCESS) { espi_show_failure(cmd, "Error: eSPI timed out waiting for command to complete", 0); - return -1; + return CB_ERR; } - if (espi_poll_status(&status) == -1) { + if (espi_poll_status(&status) != CB_SUCCESS) { espi_show_failure(cmd, "Error: eSPI poll status failed", 0); - return -1; + return CB_ERR; } /* If command did not complete downstream, return error. */ if (!(status & ESPI_STATUS_DNCMD_COMPLETE)) { espi_show_failure(cmd, "Error: eSPI downstream command completion failure", status); - return -1; + return CB_ERR; } if (status & ~(ESPI_STATUS_DNCMD_COMPLETE | cmd->expected_status_codes)) { espi_show_failure(cmd, "Error: unexpected eSPI status register bits set", status); - return -1; + return CB_ERR; } espi_write32(ESPI_SLAVE0_INT_STS, status); - return 0; + return CB_SUCCESS; } -static int espi_send_reset(void) +static enum cb_err espi_send_reset(void) { struct espi_cmd cmd = { .hdr0 = { @@ -566,7 +566,7 @@ return espi_send_command(&cmd); } -static int espi_send_pltrst(const struct espi_config *mb_cfg, bool assert) +static enum cb_err espi_send_pltrst(const struct espi_config *mb_cfg, bool assert) { struct espi_cmd cmd = { .hdr0 = { @@ -582,7 +582,7 @@ }; if (!mb_cfg->vw_ch_en) - return 0; + return CB_SUCCESS; return espi_send_command(&cmd); } @@ -594,7 +594,7 @@ #define ESPI_CONFIGURATION_HDATA0(a) (((a) >> 8) & 0xff) #define ESPI_CONFIGURATION_HDATA1(a) ((a) & 0xff) -static int espi_get_configuration(uint16_t slave_reg_addr, uint32_t *config) +static enum cb_err espi_get_configuration(uint16_t slave_reg_addr, uint32_t *config) { struct espi_cmd cmd = { .hdr0 = { @@ -607,8 +607,8 @@ *config = 0; - if (espi_send_command(&cmd)) - return -1; + if (espi_send_command(&cmd) != CB_SUCCESS) + return CB_ERR; *config = espi_read32(ESPI_DN_TX_HDR1); @@ -616,10 +616,10 @@ printk(BIOS_DEBUG, "Get configuration for slave register(0x%x): 0x%x\n", slave_reg_addr, *config); - return 0; + return CB_SUCCESS; } -static int espi_set_configuration(uint16_t slave_reg_addr, uint32_t config) +static enum cb_err espi_set_configuration(uint16_t slave_reg_addr, uint32_t config) { struct espi_cmd cmd = { .hdr0 = { @@ -636,13 +636,13 @@ return espi_send_command(&cmd); } -static int espi_get_general_configuration(uint32_t *config) +static enum cb_err espi_get_general_configuration(uint32_t *config) { - if (espi_get_configuration(ESPI_SLAVE_GENERAL_CFG, config) == -1) - return -1; + if (espi_get_configuration(ESPI_SLAVE_GENERAL_CFG, config) != CB_SUCCESS) + return CB_ERR; espi_show_slave_general_configuration(*config); - return 0; + return CB_SUCCESS; } static void espi_set_io_mode_config(enum espi_io_mode mb_io_mode, uint32_t slave_caps, @@ -737,7 +737,7 @@ } } -static int espi_set_general_configuration(const struct espi_config *mb_cfg, uint32_t slave_caps) +static enum cb_err espi_set_general_configuration(const struct espi_config *mb_cfg, uint32_t slave_caps) { uint32_t slave_config = 0; uint32_t ctrlr_config = 0; @@ -757,14 +757,14 @@ espi_show_slave_general_configuration(slave_config); - if (espi_set_configuration(ESPI_SLAVE_GENERAL_CFG, slave_config) == -1) - return -1; + if (espi_set_configuration(ESPI_SLAVE_GENERAL_CFG, slave_config) != CB_SUCCESS) + return CB_ERR; espi_write32(ESPI_SLAVE0_CONFIG, ctrlr_config); - return 0; + return CB_SUCCESS; } -static int espi_wait_channel_ready(uint16_t slave_reg_addr) +static enum cb_err espi_wait_channel_ready(uint16_t slave_reg_addr) { struct stopwatch sw; uint32_t config; @@ -773,12 +773,12 @@ do { espi_get_configuration(slave_reg_addr, &config); if (espi_slave_is_channel_ready(config)) - return 0; + return CB_SUCCESS; } while (!stopwatch_expired(&sw)); printk(BIOS_ERR, "Error: Channel is not ready after %d usec (slave addr: 0x%x)\n", ESPI_CH_READY_TIMEOUT_US, slave_reg_addr); - return -1; + return CB_ERR; } @@ -791,23 +791,23 @@ espi_write32(ESPI_SLAVE0_CONFIG, reg); } -static int espi_set_channel_configuration(uint32_t slave_config, uint32_t slave_reg_addr, +static enum cb_err espi_set_channel_configuration(uint32_t slave_config, uint32_t slave_reg_addr, uint32_t ctrlr_enable) { - if (espi_set_configuration(slave_reg_addr, slave_config) == -1) - return -1; + if (espi_set_configuration(slave_reg_addr, slave_config) != CB_SUCCESS) + return CB_ERR; if (!(slave_config & ESPI_SLAVE_CHANNEL_ENABLE)) - return 0; + return CB_SUCCESS; - if (espi_wait_channel_ready(slave_reg_addr) == -1) - return -1; + if (espi_wait_channel_ready(slave_reg_addr) != CB_SUCCESS) + return CB_ERR; espi_enable_ctrlr_channel(ctrlr_enable); - return 0; + return CB_SUCCESS; } -static int espi_setup_vw_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) +static enum cb_err espi_setup_vw_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) { uint32_t slave_vw_caps; uint32_t ctrlr_vw_caps; @@ -817,15 +817,15 @@ uint32_t slave_config; if (!mb_cfg->vw_ch_en) - return 0; + return CB_SUCCESS; if (!espi_slave_supports_vw_channel(slave_caps)) { printk(BIOS_ERR, "Error: eSPI slave doesn't support VW channel!\n"); - return -1; + return CB_ERR; } - if (espi_get_configuration(ESPI_SLAVE_VW_CFG, &slave_vw_caps) == -1) - return -1; + if (espi_get_configuration(ESPI_SLAVE_VW_CFG, &slave_vw_caps) != CB_SUCCESS) + return CB_ERR; ctrlr_vw_caps = espi_read32(ESPI_MASTER_CAP); ctrlr_vw_count_supp = (ctrlr_vw_caps & ESPI_VW_MAX_SIZE_MASK) >> ESPI_VW_MAX_SIZE_SHIFT; @@ -837,15 +837,15 @@ return espi_set_channel_configuration(slave_config, ESPI_SLAVE_VW_CFG, ESPI_VW_CH_EN); } -static int espi_setup_periph_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) +static enum cb_err espi_setup_periph_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) { uint32_t slave_config; /* Peripheral channel requires BME bit to be set when enabling the channel. */ const uint32_t slave_en_mask = ESPI_SLAVE_CHANNEL_ENABLE | ESPI_SLAVE_PERIPH_BUS_MASTER_ENABLE; - if (espi_get_configuration(ESPI_SLAVE_PERIPH_CFG, &slave_config) == -1) - return -1; + if (espi_get_configuration(ESPI_SLAVE_PERIPH_CFG, &slave_config) != CB_SUCCESS) + return CB_ERR; /* * Peripheral channel is the only one which is enabled on reset. So, if the mainboard @@ -855,7 +855,7 @@ if (mb_cfg->periph_ch_en) { if (!espi_slave_supports_periph_channel(slave_caps)) { printk(BIOS_ERR, "Error: eSPI slave doesn't support periph channel!\n"); - return -1; + return CB_ERR; } slave_config |= slave_en_mask; } else { @@ -868,20 +868,20 @@ ESPI_PERIPH_CH_EN); } -static int espi_setup_oob_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) +static enum cb_err espi_setup_oob_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) { uint32_t slave_config; if (!mb_cfg->oob_ch_en) - return 0; + return CB_SUCCESS; if (!espi_slave_supports_oob_channel(slave_caps)) { printk(BIOS_ERR, "Error: eSPI slave doesn't support OOB channel!\n"); - return -1; + return CB_ERR; } - if (espi_get_configuration(ESPI_SLAVE_OOB_CFG, &slave_config) == -1) - return -1; + if (espi_get_configuration(ESPI_SLAVE_OOB_CFG, &slave_config) != CB_SUCCESS) + return CB_ERR; slave_config |= ESPI_SLAVE_CHANNEL_ENABLE; @@ -889,20 +889,20 @@ ESPI_OOB_CH_EN); } -static int espi_setup_flash_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) +static enum cb_err espi_setup_flash_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) { uint32_t slave_config; if (!mb_cfg->flash_ch_en) - return 0; + return CB_SUCCESS; if (!espi_slave_supports_flash_channel(slave_caps)) { printk(BIOS_ERR, "Error: eSPI slave doesn't support flash channel!\n"); - return -1; + return CB_ERR; } - if (espi_get_configuration(ESPI_SLAVE_FLASH_CFG, &slave_config) == -1) - return -1; + if (espi_get_configuration(ESPI_SLAVE_FLASH_CFG, &slave_config) != CB_SUCCESS) + return CB_ERR; slave_config |= ESPI_SLAVE_CHANNEL_ENABLE; @@ -968,7 +968,7 @@ * Send in-band reset * The resets affects both host and slave devices, so set initial config again. */ - if (espi_send_reset() == -1) { + if (espi_send_reset() != CB_SUCCESS) { printk(BIOS_ERR, "Error: In-band reset failed!\n"); return -1; } @@ -978,7 +978,7 @@ * Boot sequence: Step 3 * Get configuration of slave device. */ - if (espi_get_general_configuration(&slave_caps) == -1) { + if (espi_get_general_configuration(&slave_caps) != CB_SUCCESS) { printk(BIOS_ERR, "Error: Slave GET_CONFIGURATION failed!\n"); return -1; } @@ -988,7 +988,7 @@ * Step 4: Write slave device general config * Step 5: Set host slave config */ - if (espi_set_general_configuration(cfg, slave_caps) == -1) { + if (espi_set_general_configuration(cfg, slave_caps) != CB_SUCCESS) { printk(BIOS_ERR, "Error: Slave SET_CONFIGURATION failed!\n"); return -1; } @@ -1004,34 +1004,34 @@ * Channel setup */ /* Set up VW first so we can deassert PLTRST#. */ - if (espi_setup_vw_channel(cfg, slave_caps) == -1) { + if (espi_setup_vw_channel(cfg, slave_caps) != CB_SUCCESS) { printk(BIOS_ERR, "Error: Setup VW channel failed!\n"); return -1; } /* Assert PLTRST# if VW channel is enabled by mainboard. */ - if (espi_send_pltrst(cfg, true) == -1) { + if (espi_send_pltrst(cfg, true) != CB_SUCCESS) { printk(BIOS_ERR, "Error: PLTRST# assertion failed!\n"); return -1; } /* De-assert PLTRST# if VW channel is enabled by mainboard. */ - if (espi_send_pltrst(cfg, false) == -1) { + if (espi_send_pltrst(cfg, false) != CB_SUCCESS) { printk(BIOS_ERR, "Error: PLTRST# deassertion failed!\n"); return -1; } - if (espi_setup_periph_channel(cfg, slave_caps) == -1) { + if (espi_setup_periph_channel(cfg, slave_caps) != CB_SUCCESS) { printk(BIOS_ERR, "Error: Setup Periph channel failed!\n"); return -1; } - if (espi_setup_oob_channel(cfg, slave_caps) == -1) { + if (espi_setup_oob_channel(cfg, slave_caps) != CB_SUCCESS) { printk(BIOS_ERR, "Error: Setup OOB channel failed!\n"); return -1; } - if (espi_setup_flash_channel(cfg, slave_caps) == -1) { + if (espi_setup_flash_channel(cfg, slave_caps) != CB_SUCCESS) { printk(BIOS_ERR, "Error: Setup Flash channel failed!\n"); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/60207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8c703f62babac31948d0878e91bd31b31bebc01 Gerrit-Change-Number: 60207 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/common/lpc/espi_util: simplify espi_configure_decodes
by Felix Held (Code Review) 18 Dec '21

18 Dec '21

1 0

Change in coreboot[master]: soc/amd/common/lpc/espi_util: simplify espi_get_general_configuration
by Felix Held (Code Review) 18 Dec '21

18 Dec '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60205 ) Change subject: soc/amd/common/lpc/espi_util: simplify espi_get_general_configuration ...................................................................... soc/amd/common/lpc/espi_util: simplify espi_get_general_configuration The intermediate ret variable isn't needed. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4e6747cf468c5ba8da6c1a3b20022851e32ad951 --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/60205/1 diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 4eb700b..7261bb9 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -639,8 +639,7 @@ static int espi_get_general_configuration(uint32_t *config) { - int ret = espi_get_configuration(ESPI_SLAVE_GENERAL_CFG, config); - if (ret == -1) + if (espi_get_configuration(ESPI_SLAVE_GENERAL_CFG, config) == -1) return -1; espi_show_slave_general_configuration(*config); -- To view, visit https://review.coreboot.org/c/coreboot/+/60205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e6747cf468c5ba8da6c1a3b20022851e32ad951 Gerrit-Change-Number: 60205 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/cannonlake: Hook up DPTF device to devicetree
by Felix Singer (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Tim Crawford, Nico Huber, Patrick Rudolph, Jeremy Soller, Christian Walter, Tim Wawrzynczak, Michael Niewöhner. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59887 ) Change subject: soc/intel/cannonlake: Hook up DPTF device to devicetree ...................................................................... Patch Set 10: (1 comment) File src/mainboard/google/hatch/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/59887/comment/5ab36b3a_6a5681fc PS4, Line 204: device pci 04.0 on end # SA Thermal device > Well, what I said: […] I moved the former two changes for separation into their own commit. So this should be fine now, I think? -- To view, visit https://review.coreboot.org/c/coreboot/+/59887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2ab7a691cb0f6941ef7c9def5fa2e6247127c15 Gerrit-Change-Number: 59887 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 18 Dec 2021 00:03:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/cannonlake: Hook up DPTF device to devicetree
by Felix Singer (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Tim Crawford, Nico Huber, Patrick Rudolph, Jeremy Soller, Christian Walter, Tim Wawrzynczak, Michael Niewöhner. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59887 ) Change subject: soc/intel/cannonlake: Hook up DPTF device to devicetree ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/59887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2ab7a691cb0f6941ef7c9def5fa2e6247127c15 Gerrit-Change-Number: 59887 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 17 Dec 2021 23:59:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mainboard: Fix DPTF device state in the devicetree on CFL boards
by Felix Singer (Code Review) 18 Dec '21

18 Dec '21

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60203 ) Change subject: mainboard: Fix DPTF device state in the devicetree on CFL boards ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/60203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I561598c252c5da64ece569c6ba336852e713ccab Gerrit-Change-Number: 60203 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 17 Dec 2021 23:59:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/cezanne/fch: disable 48MHz output in S0i3
by Felix Held (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60125 ) Change subject: soc/amd/cezanne/fch: disable 48MHz output in S0i3 ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60125/comment/e4d0fa4a_7ef2bd58 PS1, Line 7: S0i3 > yes, this should save some power in s0i3. […] i've added a commit message that should explain this in the last version of the patch -- To view, visit https://review.coreboot.org/c/coreboot/+/60125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If445f5825dc7b795c95d73c061156cc485421ada Gerrit-Change-Number: 60125 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Fri, 17 Dec 2021 21:49:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/denverton_ns: Use `popcnt()` helper
by Felix Held (Code Review) 17 Dec '21

17 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58912 ) Change subject: soc/intel/denverton_ns: Use `popcnt()` helper ...................................................................... soc/intel/denverton_ns: Use `popcnt()` helper Use the `popcnt()` helper instead of manually counting the number of set bits in the first `CONFIG_MAX_CPUS` bits with a loop. Also, use unsigned types to store the number of active/total cores. Change-Id: Iae6b16991fcf07c9ad67d2b737e490212b8deedd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58912 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/cpu.h 2 files changed, 9 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index ef1140b..fb4923f 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -15,7 +15,7 @@ #include <device/device.h> #include <device/pci.h> #include <intelblocks/cpulib.h> - +#include <lib.h> #include <soc/msr.h> #include <soc/cpu.h> #include <soc/iomap.h> @@ -182,28 +182,19 @@ } } -static int detect_num_cpus_via_mch(void) +/* Assumes that FSP has already programmed the cores disabled register */ +static unsigned int detect_num_cpus_via_mch(void) { - /* Assumes that FSP has already programmed the cores disabled register - */ - u32 core_exists_mask, active_cores_mask; - u32 core_disable_mask; - register int active_cores = 0, total_cores = 0; - register int counter = 0; - /* Get Masks for Total Existing SOC Cores and Core Disable Mask */ - core_exists_mask = MMIO32(DEFAULT_MCHBAR + MCH_BAR_CORE_EXISTS_MASK); - core_disable_mask = MMIO32(DEFAULT_MCHBAR + MCH_BAR_CORE_DISABLE_MASK); - active_cores_mask = (~core_disable_mask) & core_exists_mask; + const u32 core_exists_mask = MMIO32(DEFAULT_MCHBAR + MCH_BAR_CORE_EXISTS_MASK); + const u32 core_disable_mask = MMIO32(DEFAULT_MCHBAR + MCH_BAR_CORE_DISABLE_MASK); + const u32 active_cores_mask = ~core_disable_mask & core_exists_mask; /* Calculate Number of Active Cores */ - for (; counter < CONFIG_MAX_CPUS; - counter++, active_cores_mask >>= 1, core_exists_mask >>= 1) { - active_cores += (active_cores_mask & CORE_BIT_MSK); - total_cores += (core_exists_mask & CORE_BIT_MSK); - } + const unsigned int active_cores = popcnt(active_cores_mask); + const unsigned int total_cores = popcnt(core_exists_mask); - printk(BIOS_DEBUG, "Number of Active Cores: %d of %d total.\n", + printk(BIOS_DEBUG, "Number of Active Cores: %u of %u total.\n", active_cores, total_cores); return active_cores; diff --git a/src/soc/intel/denverton_ns/include/soc/cpu.h b/src/soc/intel/denverton_ns/include/soc/cpu.h index a714764..a8af626 100644 --- a/src/soc/intel/denverton_ns/include/soc/cpu.h +++ b/src/soc/intel/denverton_ns/include/soc/cpu.h @@ -11,7 +11,6 @@ #ifndef __ACPI__ #define MSR_CORE_THREAD_COUNT 0x35 -#define CORE_BIT_MSK 0x1 #define MCH_BAR_CORE_EXISTS_MASK 0x7164 #define MCH_BAR_CORE_DISABLE_MASK 0x7168 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae6b16991fcf07c9ad67d2b737e490212b8deedd Gerrit-Change-Number: 58912 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: crossgcc: Update acpica from 20210331 to 20211217
by HAOUAS Elyes (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: HAOUAS Elyes. Hello build bot (Jenkins), Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59174 to look at the new patch set (#9). Change subject: crossgcc: Update acpica from 20210331 to 20211217 ...................................................................... crossgcc: Update acpica from 20210331 to 20211217 Change-Id: I3a03b74e95f910b50aa2f7ce502b1e9ad5b6df37 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20211217_iasl.patch D util/crossgcc/sum/acpica-unix2-20210331.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20211217.tar.gz.cksum 4 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/59174/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/59174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a03b74e95f910b50aa2f7ce502b1e9ad5b6df37 Gerrit-Change-Number: 59174 Gerrit-PatchSet: 9 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2021