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Change in coreboot[master]: sb/intel/lynxpoint: Use unions for MEI registers
by Felix Held (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59623 ) Change subject: sb/intel/lynxpoint: Use unions for MEI registers ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4defbb8c0e7812bf95c672ce529959f67c34537a Gerrit-Change-Number: 59623 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 18 Dec 2021 12:48:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Add enum for `power_profile`
by Angel Pons (Code Review) 18 Dec '21

18 Dec '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60212 ) Change subject: mb/starlabs/labtop: Add enum for `power_profile` ...................................................................... mb/starlabs/labtop: Add enum for `power_profile` Introduce and use an enum for the `power_profile` CMOS option. Add a helper function that converts CMOS values into enum values. Using an enum allows GCC to warn about switch statements using enum types for their control expressions not handling all possible enum values, and also improves readability. Change-Id: I47a453ea12d164d26908a9944a89a481757e753c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/starlabs/labtop/include/variants.h M src/mainboard/starlabs/labtop/mainboard.c M src/mainboard/starlabs/labtop/variants/tgl/devtree.c 3 files changed, 29 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/60212/1 diff --git a/src/mainboard/starlabs/labtop/include/variants.h b/src/mainboard/starlabs/labtop/include/variants.h index c95d15b..0dd41c0 100644 --- a/src/mainboard/starlabs/labtop/include/variants.h +++ b/src/mainboard/starlabs/labtop/include/variants.h @@ -5,6 +5,15 @@ #include <soc/gpio.h> +enum cmos_power_profile { + PP_POWER_SAVER = 0, + PP_BALANCED = 1, + PP_PERFORMANCE = 2, +}; +#define NUM_POWER_PROFILES 3 + +enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback); + /* * The next set of functions return the gpio table and fill in the number of * entries for each table. diff --git a/src/mainboard/starlabs/labtop/mainboard.c b/src/mainboard/starlabs/labtop/mainboard.c index 60e65ee..d394f25 100644 --- a/src/mainboard/starlabs/labtop/mainboard.c +++ b/src/mainboard/starlabs/labtop/mainboard.c @@ -5,6 +5,12 @@ #include <option.h> #include <variants.h> +enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback) +{ + const unsigned int power_profile = get_uint_option("power_profile", fallback); + return power_profile < NUM_POWER_PROFILES ? power_profile : fallback; +} + static void init_mainboard(void *chip_info) { const struct pad_config *pads; diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devtree.c b/src/mainboard/starlabs/labtop/variants/tgl/devtree.c index 42a5aff..09d26e8 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devtree.c +++ b/src/mainboard/starlabs/labtop/variants/tgl/devtree.c @@ -24,26 +24,26 @@ /* Update PL1 & PL2 based on CMOS settings */ - switch (get_uint_option("power_profile", 0)) { - case 1: - soc_conf_2core->tdp_pl1_override = 15; - soc_conf_4core->tdp_pl1_override = 15; - soc_conf_2core->tdp_pl2_override = 25; - soc_conf_4core->tdp_pl2_override = 25; - break; - case 2: - soc_conf_2core->tdp_pl1_override = 28; - soc_conf_4core->tdp_pl1_override = 28; - soc_conf_2core->tdp_pl2_override = 40; - soc_conf_4core->tdp_pl2_override = 40; - break; - default: + switch (get_power_profile(PP_POWER_SAVER)) { + case PP_POWER_SAVER: disable_turbo(); soc_conf_2core->tdp_pl1_override = 15; soc_conf_4core->tdp_pl1_override = 15; soc_conf_2core->tdp_pl2_override = 15; soc_conf_4core->tdp_pl2_override = 15; break; + case PP_BALANCED: + soc_conf_2core->tdp_pl1_override = 15; + soc_conf_4core->tdp_pl1_override = 15; + soc_conf_2core->tdp_pl2_override = 25; + soc_conf_4core->tdp_pl2_override = 25; + break; + case PP_PERFORMANCE: + soc_conf_2core->tdp_pl1_override = 28; + soc_conf_4core->tdp_pl1_override = 28; + soc_conf_2core->tdp_pl2_override = 40; + soc_conf_4core->tdp_pl2_override = 40; + break; } /* Enable/Disable Wireless based on CMOS settings */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47a453ea12d164d26908a9944a89a481757e753c Gerrit-Change-Number: 60212 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/starlabs/labtop: Rename some files
by Angel Pons (Code Review) 18 Dec '21

18 Dec '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60211 ) Change subject: mb/starlabs/labtop: Rename some files ...................................................................... mb/starlabs/labtop: Rename some files Rename `mainboard.c` to `smbios.c` as it only contains SMBIOS functions. Rename `ramstage.c` to `mainboard.c` as it contains the mainboard chip operations struct. Change-Id: I9548ca72a7583de98f5b154e3381825bba00d5cf Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/starlabs/labtop/Makefile.inc M src/mainboard/starlabs/labtop/mainboard.c D src/mainboard/starlabs/labtop/ramstage.c A src/mainboard/starlabs/labtop/smbios.c 4 files changed, 60 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/60211/1 diff --git a/src/mainboard/starlabs/labtop/Makefile.inc b/src/mainboard/starlabs/labtop/Makefile.inc index cb72a08..71fc0cf 100644 --- a/src/mainboard/starlabs/labtop/Makefile.inc +++ b/src/mainboard/starlabs/labtop/Makefile.inc @@ -7,5 +7,5 @@ ramstage-y += hda_verb.c ramstage-y += mainboard.c -ramstage-y += ramstage.c +ramstage-y += smbios.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/starlabs/labtop/mainboard.c b/src/mainboard/starlabs/labtop/mainboard.c index 8babae3..60e65ee 100644 --- a/src/mainboard/starlabs/labtop/mainboard.c +++ b/src/mainboard/starlabs/labtop/mainboard.c @@ -1,47 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <chip.h> -#include <console/console.h> #include <device/device.h> -#include <device/pci_def.h> -#include <ec/starlabs/merlin/ec.h> -#include <limits.h> +#include <soc/ramstage.h> #include <option.h> -#include <smbios.h> -#include <types.h> -#include <uuid.h> #include <variants.h> -const char *smbios_mainboard_bios_version(void) +static void init_mainboard(void *chip_info) { - return "8"; + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); + + devtree_update(); } -/* Get the Embedded Controller firmware version */ -void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision) -{ - u16 ec_version = it_get_version(); - - *ec_major_revision = ec_version >> 8; - *ec_minor_revision = ec_version & 0xff; -} - -const char *smbios_system_sku(void) -{ - return CONFIG_MAINBOARD_FAMILY; -} - -u8 smbios_mainboard_feature_flags(void) -{ - return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; -} - -const char *smbios_chassis_version(void) -{ - return smbios_mainboard_version(); -} - -const char *smbios_chassis_serial_number(void) -{ - return smbios_mainboard_serial_number(); -} +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; diff --git a/src/mainboard/starlabs/labtop/ramstage.c b/src/mainboard/starlabs/labtop/ramstage.c deleted file mode 100644 index 60e65ee..0000000 --- a/src/mainboard/starlabs/labtop/ramstage.c +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <soc/ramstage.h> -#include <option.h> -#include <variants.h> - -static void init_mainboard(void *chip_info) -{ - const struct pad_config *pads; - size_t num; - - pads = variant_gpio_table(&num); - gpio_configure_pads(pads, num); - - devtree_update(); -} - -struct chip_operations mainboard_ops = { - .init = init_mainboard, -}; diff --git a/src/mainboard/starlabs/labtop/smbios.c b/src/mainboard/starlabs/labtop/smbios.c new file mode 100644 index 0000000..8babae3 --- /dev/null +++ b/src/mainboard/starlabs/labtop/smbios.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <chip.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <ec/starlabs/merlin/ec.h> +#include <limits.h> +#include <option.h> +#include <smbios.h> +#include <types.h> +#include <uuid.h> +#include <variants.h> + +const char *smbios_mainboard_bios_version(void) +{ + return "8"; +} + +/* Get the Embedded Controller firmware version */ +void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision) +{ + u16 ec_version = it_get_version(); + + *ec_major_revision = ec_version >> 8; + *ec_minor_revision = ec_version & 0xff; +} + +const char *smbios_system_sku(void) +{ + return CONFIG_MAINBOARD_FAMILY; +} + +u8 smbios_mainboard_feature_flags(void) +{ + return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; +} + +const char *smbios_chassis_version(void) +{ + return smbios_mainboard_version(); +} + +const char *smbios_chassis_serial_number(void) +{ + return smbios_mainboard_serial_number(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/60211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9548ca72a7583de98f5b154e3381825bba00d5cf Gerrit-Change-Number: 60211 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Use unions for ME PCI registers
by Felix Held (Code Review) 18 Dec '21

18 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59622 ) Change subject: sb/intel/lynxpoint: Use unions for ME PCI registers ...................................................................... sb/intel/lynxpoint: Use unions for ME PCI registers Wrap bitfield structs in unions to reduce pointer usage. Change-Id: I8ac901211beb0ef24dff926b1a06004a99e68bda Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59622 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/southbridge/intel/lynxpoint/early_me.c M src/southbridge/intel/lynxpoint/me.c M src/southbridge/intel/lynxpoint/me.h M src/southbridge/intel/lynxpoint/me_status.c 4 files changed, 87 insertions(+), 103 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index e5ce3f5..9ab00cd 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -20,26 +20,10 @@ [ME_HFS_ACK_CONTINUE] = "Continue to boot" }; -static inline void pci_read_dword_ptr(void *ptr, int offset) -{ - u32 dword = pci_read_config32(PCH_ME_DEV, offset); - memcpy(ptr, &dword, sizeof(dword)); -} - -static inline void pci_write_dword_ptr(void *ptr, int offset) -{ - u32 dword = 0; - memcpy(&dword, ptr, sizeof(dword)); - pci_write_config32(PCH_ME_DEV, offset, dword); -} - void intel_early_me_status(void) { - struct me_hfs hfs; - struct me_hfs2 hfs2; - - pci_read_dword_ptr(&hfs, PCI_ME_HFS); - pci_read_dword_ptr(&hfs2, PCI_ME_HFS2); + union me_hfs hfs = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS) }; + union me_hfs2 hfs2 = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS2) }; intel_me_status(&hfs, &hfs2); } @@ -47,15 +31,15 @@ int intel_early_me_init(void) { int count; - struct me_uma uma; - struct me_hfs hfs; + union me_uma uma; + union me_hfs hfs; printk(BIOS_INFO, "Intel ME early init\n"); /* Wait for ME UMA SIZE VALID bit to be set */ /* FIXME: ME9 BGW indicates a 5 sec poll timeout. */ for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(&uma, PCI_ME_UMA); + uma.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA); if (uma.valid) break; udelay(ME_DELAY); @@ -66,7 +50,7 @@ } /* Check for valid firmware */ - pci_read_dword_ptr(&hfs, PCI_ME_HFS); + hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); if (hfs.fpt_bad) { printk(BIOS_WARNING, "WARNING: ME has bad firmware\n"); return -1; @@ -78,9 +62,8 @@ int intel_early_me_uma_size(void) { - struct me_uma uma; + union me_uma uma = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA) }; - pci_read_dword_ptr(&uma, PCI_ME_UMA); if (uma.valid) { printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size); return uma.size; @@ -108,8 +91,8 @@ u8 reset; int count; u32 mebase_l, mebase_h; - struct me_hfs hfs; - struct me_did did = { + union me_hfs hfs; + union me_did did = { .init_done = ME_INIT_DONE, .status = status }; @@ -123,7 +106,7 @@ printk(BIOS_DEBUG, "ME: Sending Init Done with status: %d, " "UMA base: 0x%04x\n", status, did.uma_base); - pci_write_dword_ptr(&did, PCI_ME_H_GS); + pci_write_config32(PCH_ME_DEV, PCI_ME_H_GS, did.raw); /* * The ME firmware does not respond with an ACK when NOMEM or ERROR @@ -134,7 +117,7 @@ /* Must wait for ME acknowledgement */ for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(&hfs, PCI_ME_HFS); + hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); if (hfs.bios_msg_ack) break; udelay(ME_DELAY); diff --git a/src/southbridge/intel/lynxpoint/me.c b/src/southbridge/intel/lynxpoint/me.c index 9196fb3..a1625e8 100644 --- a/src/southbridge/intel/lynxpoint/me.c +++ b/src/southbridge/intel/lynxpoint/me.c @@ -92,13 +92,6 @@ mei_dump(ptr, dword, offset, "WRITE"); } -static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) -{ - u32 dword = pci_read_config32(dev, offset); - memcpy(ptr, &dword, sizeof(dword)); - mei_dump(ptr, dword, offset, "PCI READ"); -} - static inline void read_host_csr(struct mei_csr *csr) { mei_read_dword_ptr(csr, MEI_H_CSR); @@ -434,11 +427,11 @@ static void intel_me_mbp_clear(struct device *dev) { int count; - struct me_hfs2 hfs2; + union me_hfs2 hfs2; /* Wait for the mbp_cleared indicator */ for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); + hfs2.raw = pci_read_config32(dev, PCI_ME_HFS2); if (hfs2.mbp_cleared) break; udelay(ME_DELAY); @@ -539,7 +532,7 @@ void intel_me_finalize(struct device *dev) { - struct me_hfs hfs; + union me_hfs hfs; u32 reg32; reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -553,8 +546,7 @@ intel_me_mbp_clear(dev); /* Make sure ME is in a mode that expects EOP */ - reg32 = pci_read_config32(dev, PCI_ME_HFS); - memcpy(&hfs, &reg32, sizeof(u32)); + hfs.raw = pci_read_config32(dev, PCI_ME_HFS); /* Abort and leave device alone if not normal mode */ if (hfs.fpt_bad || @@ -599,11 +591,8 @@ static enum me_bios_path intel_me_path(struct device *dev) { enum me_bios_path path = ME_DISABLE_BIOS_PATH; - struct me_hfs hfs; - struct me_hfs2 hfs2; - - pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); - pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); + union me_hfs hfs = { .raw = pci_read_config32(dev, PCI_ME_HFS) }; + union me_hfs2 hfs2 = { .raw = pci_read_config32(dev, PCI_ME_HFS2) }; /* Check and dump status */ intel_me_status(&hfs, &hfs2); @@ -693,11 +682,10 @@ /* Read the Extend register hash of ME firmware */ static int intel_me_extend_valid(struct device *dev) { - struct me_heres status; + union me_heres status = { .raw = pci_read_config32(dev, PCI_ME_HERES) }; u32 extend[8] = {0}; int i, count = 0; - pci_read_dword_ptr(dev, &status, PCI_ME_HERES); if (!status.extend_feature_present) { printk(BIOS_ERR, "ME: Extend Feature not present\n"); return -1; @@ -762,12 +750,10 @@ struct mbp_header mbp_hdr; u32 me2host_pending; struct mei_csr host; - struct me_hfs2 hfs2; + union me_hfs2 hfs2 = { .raw = pci_read_config32(dev, PCI_ME_HFS2) }; struct mbp_payload *mbp; int i; - pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); - if (!hfs2.mbp_rdy) { printk(BIOS_ERR, "ME: MBP not ready\n"); goto mbp_failure; diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index cf797f3..6b072f9 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -50,31 +50,37 @@ #define ME_HFS_ACK_GBL_RESET 6 #define ME_HFS_ACK_CONTINUE 7 -struct me_hfs { - u32 working_state: 4; - u32 mfg_mode: 1; - u32 fpt_bad: 1; - u32 operation_state: 3; - u32 fw_init_complete: 1; - u32 ft_bup_ld_flr: 1; - u32 update_in_progress: 1; - u32 error_code: 4; - u32 operation_mode: 4; - u32 reserved: 4; - u32 boot_options_present: 1; - u32 ack_data: 3; - u32 bios_msg_ack: 4; -} __packed; +union me_hfs { + struct __packed { + u32 working_state: 4; + u32 mfg_mode: 1; + u32 fpt_bad: 1; + u32 operation_state: 3; + u32 fw_init_complete: 1; + u32 ft_bup_ld_flr: 1; + u32 update_in_progress: 1; + u32 error_code: 4; + u32 operation_mode: 4; + u32 reserved: 4; + u32 boot_options_present: 1; + u32 ack_data: 3; + u32 bios_msg_ack: 4; + }; + u32 raw; +}; #define PCI_ME_UMA 0x44 -struct me_uma { - u32 size: 6; - u32 reserved_1: 10; - u32 valid: 1; - u32 reserved_0: 14; - u32 set_to_one: 1; -} __packed; +union me_uma { + struct __packed { + u32 size: 6; + u32 reserved_1: 10; + u32 valid: 1; + u32 reserved_0: 14; + u32 set_to_one: 1; + }; + u32 raw; +}; #define PCI_ME_H_GS 0x4c #define ME_INIT_DONE 1 @@ -83,13 +89,16 @@ #define ME_INIT_STATUS_ERROR 2 #define ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */ -struct me_did { - u32 uma_base: 16; - u32 reserved: 7; - u32 rapid_start: 1; - u32 status: 4; - u32 init_done: 4; -} __packed; +union me_did { + struct __packed { + u32 uma_base: 16; + u32 reserved: 7; + u32 rapid_start: 1; + u32 status: 4; + u32 init_done: 4; + }; + u32 raw; +}; /* * Apparently the GMES register is renamed to HFS2 (or HFSTS2 according @@ -165,22 +174,25 @@ #define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb #define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc -struct me_hfs2 { - u32 bist_in_progress: 1; - u32 reserved1: 2; - u32 invoke_mebx: 1; - u32 cpu_replaced_sts: 1; - u32 mbp_rdy: 1; - u32 mfs_failure: 1; - u32 warm_reset_request: 1; - u32 cpu_replaced_valid: 1; - u32 reserved2: 4; - u32 mbp_cleared: 1; - u32 reserved3: 2; - u32 current_state: 8; - u32 current_pmevent: 4; - u32 progress_code: 4; -} __packed; +union me_hfs2 { + struct __packed { + u32 bist_in_progress: 1; + u32 reserved1: 2; + u32 invoke_mebx: 1; + u32 cpu_replaced_sts: 1; + u32 mbp_rdy: 1; + u32 mfs_failure: 1; + u32 warm_reset_request: 1; + u32 cpu_replaced_valid: 1; + u32 reserved2: 4; + u32 mbp_cleared: 1; + u32 reserved3: 2; + u32 current_state: 8; + u32 current_pmevent: 4; + u32 progress_code: 4; + }; + u32 raw; +}; #define PCI_ME_H_GS2 0x70 #define PCI_ME_MBP_GIVE_UP 0x01 @@ -190,12 +202,15 @@ #define PCI_ME_EXT_SHA256 0x02 #define PCI_ME_HER(x) (0xc0+(4*(x))) -struct me_heres { - u32 extend_reg_algorithm: 4; - u32 reserved: 26; - u32 extend_feature_present: 1; - u32 extend_reg_valid: 1; -} __packed; +union me_heres { + struct __packed { + u32 extend_reg_algorithm: 4; + u32 reserved: 26; + u32 extend_feature_present: 1; + u32 extend_reg_valid: 1; + }; + u32 raw; +}; /* * Management Engine MEI registers @@ -313,7 +328,7 @@ }; /* Defined in me_status.c for both romstage and ramstage */ -void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2); +void intel_me_status(union me_hfs *hfs, union me_hfs2 *hfs2); void intel_early_me_status(void); int intel_early_me_init(void); diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index fb4490f..3f4d9bc 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -123,7 +123,7 @@ [ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] = "Required VSCC values for flash parts do not match", }; -void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2) +void intel_me_status(union me_hfs *hfs, union me_hfs2 *hfs2) { if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/59622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ac901211beb0ef24dff926b1a06004a99e68bda Gerrit-Change-Number: 59622 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: sb/intel/lynxpoint: Use unions for ME PCI registers
by Felix Held (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59622 ) Change subject: sb/intel/lynxpoint: Use unions for ME PCI registers ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ac901211beb0ef24dff926b1a06004a99e68bda Gerrit-Change-Number: 59622 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 18 Dec 2021 12:35:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sb/intel/lynxpoint: Drop typedefs of enum type
by Felix Held (Code Review) 18 Dec '21

18 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59620 ) Change subject: sb/intel/lynxpoint: Drop typedefs of enum type ...................................................................... sb/intel/lynxpoint: Drop typedefs of enum type There's no need to use typedefs for enum types. Get rid of it. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I830d95018b33fe6ab7e2c37ebf15bb1df6ceec38 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59620 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/southbridge/intel/lynxpoint/me.c M src/southbridge/intel/lynxpoint/me.h 2 files changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/southbridge/intel/lynxpoint/me.c b/src/southbridge/intel/lynxpoint/me.c index b56d1d8..9196fb3 100644 --- a/src/southbridge/intel/lynxpoint/me.c +++ b/src/southbridge/intel/lynxpoint/me.c @@ -596,9 +596,9 @@ } /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(struct device *dev) +static enum me_bios_path intel_me_path(struct device *dev) { - me_bios_path path = ME_DISABLE_BIOS_PATH; + enum me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; struct me_hfs2 hfs2; @@ -879,7 +879,7 @@ static void intel_me_init(struct device *dev) { struct southbridge_intel_lynxpoint_config *config = dev->chip_info; - me_bios_path path = intel_me_path(dev); + enum me_bios_path path = intel_me_path(dev); struct me_bios_payload mbp_data; /* Do initial setup and determine the BIOS path */ diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index dfc8a564..cf797f3 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -303,14 +303,14 @@ u8 reset_type; } __packed; -typedef enum { +enum me_bios_path { ME_NORMAL_BIOS_PATH, ME_S3WAKE_BIOS_PATH, ME_ERROR_BIOS_PATH, ME_RECOVERY_BIOS_PATH, ME_DISABLE_BIOS_PATH, ME_FIRMWARE_UPDATE_BIOS_PATH, -} me_bios_path; +}; /* Defined in me_status.c for both romstage and ramstage */ void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2); -- To view, visit https://review.coreboot.org/c/coreboot/+/59620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I830d95018b33fe6ab7e2c37ebf15bb1df6ceec38 Gerrit-Change-Number: 59620 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: sb/intel/lynxpoint: Drop typedefs of enum type
by Felix Held (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59620 ) Change subject: sb/intel/lynxpoint: Drop typedefs of enum type ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I830d95018b33fe6ab7e2c37ebf15bb1df6ceec38 Gerrit-Change-Number: 59620 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 18 Dec 2021 12:30:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sb/intel/lynxpoint: Drop typedefs of struct types
by Felix Held (Code Review) 18 Dec '21

18 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59619 ) Change subject: sb/intel/lynxpoint: Drop typedefs of struct types ...................................................................... sb/intel/lynxpoint: Drop typedefs of struct types There's no need to use typedefs for struct types. Get rid of them. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I109bd690500a9f03b9da0fd72044be79abf660d3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59619 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/southbridge/intel/lynxpoint/me.c M src/southbridge/intel/lynxpoint/me.h 2 files changed, 61 insertions(+), 61 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/southbridge/intel/lynxpoint/me.c b/src/southbridge/intel/lynxpoint/me.c index c2f1db2..b56d1d8 100644 --- a/src/southbridge/intel/lynxpoint/me.c +++ b/src/southbridge/intel/lynxpoint/me.c @@ -452,7 +452,7 @@ } } -static void me_print_fw_version(mbp_fw_version_name *vers_name) +static void me_print_fw_version(struct mbp_fw_version_name *vers_name) { if (!vers_name) { printk(BIOS_ERR, "ME: mbp missing version report\n"); @@ -471,7 +471,7 @@ } /* Get ME Firmware Capabilities */ -static int mkhi_get_fwcaps(mbp_mefwcaps *cap) +static int mkhi_get_fwcaps(struct mbp_mefwcaps *cap) { u32 rule_id = 0; struct me_fwcaps cap_msg; @@ -491,9 +491,9 @@ } /* Get ME Firmware Capabilities */ -static void me_print_fwcaps(mbp_mefwcaps *cap) +static void me_print_fwcaps(struct mbp_mefwcaps *cap) { - mbp_mefwcaps local_caps; + struct mbp_mefwcaps local_caps; if (!cap) { cap = &local_caps; printk(BIOS_ERR, "ME: mbp missing fwcaps report\n"); @@ -747,7 +747,7 @@ } struct mbp_payload { - mbp_header header; + struct mbp_header header; u32 data[0]; }; @@ -757,9 +757,9 @@ * Return -1 to indicate a problem (give up) * Return 0 to indicate success (send LOCK+EOP) */ -static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) +static int intel_me_read_mbp(struct me_bios_payload *mbp_data, struct device *dev) { - mbp_header mbp_hdr; + struct mbp_header mbp_hdr; u32 me2host_pending; struct mei_csr host; struct me_hfs2 hfs2; @@ -826,7 +826,7 @@ } /* Setup the pointers in the me_bios_payload structure. */ for (i = 0; i < mbp->header.mbp_size - 1;) { - mbp_item_header *item = (void *)&mbp->data[i]; + struct mbp_item_header *item = (void *)&mbp->data[i]; switch (MBP_MAKE_IDENT(item->app_id, item->item_id)) { case MBP_IDENT(KERNEL, FW_VER): @@ -880,7 +880,7 @@ { struct southbridge_intel_lynxpoint_config *config = dev->chip_info; me_bios_path path = intel_me_path(dev); - me_bios_payload mbp_data; + struct me_bios_payload mbp_data; /* Do initial setup and determine the BIOS path */ printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index d908e5b..dfc8a564 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -353,27 +353,27 @@ #define MBP_IDENT(appid, item) \ MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM) -typedef struct { +struct mbp_header { u32 mbp_size : 8; u32 num_entries : 8; u32 rsvd : 16; -} __packed mbp_header; +} __packed; -typedef struct { +struct mbp_item_header { u32 app_id : 8; u32 item_id : 8; u32 length : 8; u32 rsvd : 8; -} __packed mbp_item_header; +} __packed; -typedef struct { +struct mbp_fw_version_name { u32 major_version : 16; u32 minor_version : 16; u32 hotfix_version : 16; u32 build_version : 16; -} __packed mbp_fw_version_name; +} __packed; -typedef struct { +struct mbp_mefwcaps { u32 full_net : 1; u32 std_net : 1; u32 manageability : 1; @@ -393,19 +393,19 @@ u32 reserved_4 : 1; u32 wlan : 1; u32 reserved_5 : 8; -} __packed mbp_mefwcaps; +} __packed; -typedef struct { +struct mbp_rom_bist_data { u16 device_id; u16 fuse_test_flags; u32 umchid[4]; -} __packed mbp_rom_bist_data; +} __packed; -typedef struct { +struct mbp_platform_key { u32 key[8]; -} mbp_platform_key; +}; -typedef struct { +struct mbp_me_firmware_type { u32 mobile: 1; u32 desktop: 1; u32 server: 1; @@ -417,70 +417,70 @@ u32 image_type: 4; u32 brand: 4; u32 rsvd1: 16; -} __packed mbp_me_firmware_type; +} __packed; -typedef struct { - mbp_me_firmware_type rule_data; - u8 available; -} mbp_plat_type; +struct mbp_plat_type { + struct mbp_me_firmware_type rule_data; + u8 available; +}; -typedef struct { +struct icc_address_mask { u16 icc_start_address; u16 mask; -} __packed icc_address_mask; +} __packed; -typedef struct { - u8 num_icc_profiles; - u8 icc_profile_soft_strap; - u8 icc_profile_index; - u8 reserved; - u32 icc_reg_bundles; - icc_address_mask icc_address_mask[0]; -} __packed mbp_icc_profile; +struct mbp_icc_profile { + u8 num_icc_profiles; + u8 icc_profile_soft_strap; + u8 icc_profile_index; + u8 reserved; + u32 icc_reg_bundles; + struct icc_address_mask icc_address_mask[0]; +} __packed; -typedef struct { +struct tdt_state_flag { u16 lock_state : 1; u16 authenticate_module : 1; u16 s3authentication : 1; u16 flash_wear_out : 1; u16 flash_variable_security : 1; u16 reserved : 11; -} __packed tdt_state_flag; +} __packed; -typedef struct { - u8 state; - u8 last_theft_trigger; - tdt_state_flag flags; -} __packed mbp_at_state; +struct mbp_at_state { + u8 state; + u8 last_theft_trigger; + struct tdt_state_flag flags; +} __packed; -typedef struct { +struct mbp_plat_time { u32 wake_event_mrst_time_ms; u32 mrst_pltrst_time_ms; u32 pltrst_cpurst_time_ms; -} __packed mbp_plat_time; +} __packed; -typedef struct { +struct mbp_nfc_data { u32 device_type : 2; u32 reserved : 30; -} __packed mbp_nfc_data; +} __packed; -typedef struct { - mbp_fw_version_name *fw_version_name; - mbp_mefwcaps *fw_capabilities; - mbp_rom_bist_data *rom_bist_data; - mbp_platform_key *platform_key; - mbp_plat_type *fw_plat_type; - mbp_icc_profile *icc_profile; - mbp_at_state *at_state; - u32 *mfsintegrity; - mbp_plat_time *plat_time; - mbp_nfc_data *nfc_data; -} me_bios_payload; +struct me_bios_payload { + struct mbp_fw_version_name *fw_version_name; + struct mbp_mefwcaps *fw_capabilities; + struct mbp_rom_bist_data *rom_bist_data; + struct mbp_platform_key *platform_key; + struct mbp_plat_type *fw_plat_type; + struct mbp_icc_profile *icc_profile; + struct mbp_at_state *at_state; + u32 *mfsintegrity; + struct mbp_plat_time *plat_time; + struct mbp_nfc_data *nfc_data; +}; struct me_fwcaps { u32 id; u8 length; - mbp_mefwcaps caps_sku; + struct mbp_mefwcaps caps_sku; u8 reserved[3]; } __packed; -- To view, visit https://review.coreboot.org/c/coreboot/+/59619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I109bd690500a9f03b9da0fd72044be79abf660d3 Gerrit-Change-Number: 59619 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: sb/intel/lynxpoint: Drop typedefs of struct types
by Felix Held (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59619 ) Change subject: sb/intel/lynxpoint: Drop typedefs of struct types ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I109bd690500a9f03b9da0fd72044be79abf660d3 Gerrit-Change-Number: 59619 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 18 Dec 2021 12:29:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mainboard: Fix DPTF device state in the devicetree on CFL boards
by Nico Huber (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Felix Singer, Tim Crawford, Patrick Rudolph, Jeremy Soller, Christian Walter, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60203 ) Change subject: mainboard: Fix DPTF device state in the devicetree on CFL boards ...................................................................... Patch Set 2: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60203/comment/7ffeaae0_5848c1db PS2, Line 12: * google/hatch Actually, it's only true for half of the variants. Those that use static ASL code for DPTF, it seems. I don't fully understand the pattern, but it still seems to me that the device was `off` by accident. Would be nice to have one of the affected variants tested. https://review.coreboot.org/c/coreboot/+/60203/comment/5a07a3b7_ebe4c5c3 PS2, Line 14: Thus, set it to on to make the resource allocator aware of it. It also activates `soc/intel/common/block/dtt/dtt.c`. This simply hooks up scan_generic_bus(). However, that shouldn't matter if only variants with static ASL code / without a dummy device below 04.0 are affected. -- To view, visit https://review.coreboot.org/c/coreboot/+/60203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I561598c252c5da64ece569c6ba336852e713ccab Gerrit-Change-Number: 60203 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Sat, 18 Dec 2021 12:28:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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