coreboot-gerrit December 2021

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Change in coreboot[master]: cpu/x86/mp: Use unsigned type for CPU count
by Angel Pons (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Christian Walter, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58919 ) Change subject: cpu/x86/mp: Use unsigned type for CPU count ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: src/northbridge/amd/pi/00730F01/northbridge.c:892:26: error: initialization of 'unsigned int (*)(void)' from incompatible pointer type 'int (*)(void)' [-Werror=incompatible-pointer-types] 892 | .get_cpu_count = get_cpu_count, | ^~~~~~~~~~~~~ src/northbridge/amd/pi/00730F01/northbridge.c:892:26: note: (near initialization for 'mp_ops.get_cpu_count') -- To view, visit https://review.coreboot.org/c/coreboot/+/58919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb1e89a7e63952736503b0906dd11a6d38e9cc1c Gerrit-Change-Number: 58919 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 17 Dec 2021 11:22:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp_n: Add support for ADL-N LP5 RVP
by Krishna P Bhat D (Code Review) 17 Dec '21

17 Dec '21

Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60193 ) Change subject: mb/intel/adlrvp_n: Add support for ADL-N LP5 RVP ...................................................................... mb/intel/adlrvp_n: Add support for ADL-N LP5 RVP Add support for Alder lake N LP5 RVP with board ID 0x7. Change-Id: Ib2f53e65f75e23793d8c85ee924827446fd9fea7 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/intel/adlrvp/include/baseboard/variants.h M src/mainboard/intel/adlrvp/memory.c M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/adlrvp/spd/Makefile.inc A src/mainboard/intel/adlrvp/spd/adlrvp_n_lp5.spd.hex 5 files changed, 100 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/60193/1 diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index 9ab05f6..143679a 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -24,6 +24,8 @@ /* ADL-M LP4 and LP5 RVPs */ ADL_M_LP4 = 0x1, ADL_M_LP5 = 0x2, + /* ADL-N LP5 RVP */ + ADL_N_LP5 = 0x7, }; /* The next set of functions return the gpio table and fill in the number of diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index f4ae541..b917d98 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -290,6 +290,68 @@ }, }; +static const struct mb_cfg adln_lp5_mem_config = { + .type = MEM_TYPE_LP5X, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr1 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr2 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr3 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + .ddr4 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr5 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr6 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr7 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } + }, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_ULT_ULX, + + .LpDdrDqDqsReTraining = 1, + + .lp5x_config = { + .ccc_config = 0xff, + }, +}; + const struct mb_cfg *variant_memory_params(void) { int board_id = get_board_id(); @@ -311,6 +373,8 @@ return &adlm_lp4_mem_config; case ADL_M_LP5: return &adlm_lp5_mem_config; + case ADL_N_LP5: + return &adln_lp5_mem_config; default: die("unsupported board id : 0x%x\n", board_id); } diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 05d2a17..56bd0cd 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -80,6 +80,7 @@ case ADL_P_LP5_2: case ADL_M_LP4: case ADL_M_LP5: + case ADL_N_LP5: memcfg_init(m_cfg, mem_config, &memory_down_spd_info, half_populated); break; default: diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc index 4cb0f98..96869f4 100644 --- a/src/mainboard/intel/adlrvp/spd/Makefile.inc +++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc @@ -7,4 +7,4 @@ SPD_SOURCES += empty # 0b004 SPD_SOURCES += empty # 0b005 SPD_SOURCES += adlrvp_ddr5_mr # 0b006 -SPD_SOURCES += adlrvp_lp5 # 0b007 +SPD_SOURCES += adlrvp_n_lp5 # 0b007 diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_n_lp5.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_n_lp5.spd.hex new file mode 100644 index 0000000..88a1f1f --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_n_lp5.spd.hex @@ -0,0 +1,32 @@ +23 10 13 0E 15 1A B5 08 00 40 00 00 0A 01 00 00 +48 00 0A FF 92 55 05 00 AA 00 90 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/60193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2f53e65f75e23793d8c85ee924827446fd9fea7 Gerrit-Change-Number: 60193 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Meminit function call in coreboot has been updated as per new FSP UPD...
by Saurabh Mishra (Code Review) 17 Dec '21

17 Dec '21

Saurabh Mishra has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/60192 ) Change subject: Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/60192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c543b2 Gerrit-Change-Number: 60192 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: Meminit function call in coreboot has been updated as per new FSP UPD...
by Saurabh Mishra (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Tim Wawrzynczak. Saurabh Mishra has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/60192 ) Change subject: Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... Removed reviewer Patrick Rudolph. -- To view, visit https://review.coreboot.org/c/coreboot/+/60192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c543b2 Gerrit-Change-Number: 60192 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: Meminit function call in coreboot has been updated as per new FSP UPD...
by Saurabh Mishra (Code Review) 17 Dec '21

17 Dec '21

Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60192 ) Change subject: Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. src/soc/intel/alderlake/meminit.c: Changes adopted as per new FSP DQS & UPD calls. Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. change-Id: I0c6ae72610da39fc18ff252c440d006e83c543b2 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/alderlake/meminit.c 1 file changed, 26 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/60192/1 diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 44071db..8771181 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -123,14 +123,14 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data) { uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = { - [0] = { &mem_cfg->MemorySpdPtr00, &mem_cfg->MemorySpdPtr01, }, - [1] = { &mem_cfg->MemorySpdPtr02, &mem_cfg->MemorySpdPtr03, }, - [2] = { &mem_cfg->MemorySpdPtr04, &mem_cfg->MemorySpdPtr05, }, - [3] = { &mem_cfg->MemorySpdPtr06, &mem_cfg->MemorySpdPtr07, }, - [4] = { &mem_cfg->MemorySpdPtr08, &mem_cfg->MemorySpdPtr09, }, - [5] = { &mem_cfg->MemorySpdPtr10, &mem_cfg->MemorySpdPtr11, }, - [6] = { &mem_cfg->MemorySpdPtr12, &mem_cfg->MemorySpdPtr13, }, - [7] = { &mem_cfg->MemorySpdPtr14, &mem_cfg->MemorySpdPtr15, }, + [0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, }, + [1] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, }, + [2] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, }, + [3] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, }, + [4] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, }, + [5] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr011, }, + [6] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr011, }, + [7] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr011, }, }; uint8_t *disable_channel_upds[MRC_CHANNELS] = { &mem_cfg->DisableMc0Ch0, @@ -179,17 +179,17 @@ const struct mb_cfg *mb_cfg, bool auto_detect) { void *dq_upds[MRC_CHANNELS] = { - &mem_cfg->DqMapCpu2DramCh0, - &mem_cfg->DqMapCpu2DramCh1, - &mem_cfg->DqMapCpu2DramCh2, - &mem_cfg->DqMapCpu2DramCh3, - &mem_cfg->DqMapCpu2DramCh4, - &mem_cfg->DqMapCpu2DramCh5, - &mem_cfg->DqMapCpu2DramCh6, - &mem_cfg->DqMapCpu2DramCh7, + &mem_cfg->DqMapCpu2DramMc0Ch0, + &mem_cfg->DqMapCpu2DramMc0Ch1, + &mem_cfg->DqMapCpu2DramMc0Ch2, + &mem_cfg->DqMapCpu2DramMc0Ch3, + &mem_cfg->DqMapCpu2DramMc1Ch0, + &mem_cfg->DqMapCpu2DramMc1Ch1, + &mem_cfg->DqMapCpu2DramMc1Ch2, + &mem_cfg->DqMapCpu2DramMc1Ch3, }; - const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramCh0); + const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramMc0Ch0); _Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH, "Incorrect DQ UPD size!"); @@ -200,17 +200,17 @@ const struct mb_cfg *mb_cfg, bool auto_detect) { void *dqs_upds[MRC_CHANNELS] = { - &mem_cfg->DqsMapCpu2DramCh0, - &mem_cfg->DqsMapCpu2DramCh1, - &mem_cfg->DqsMapCpu2DramCh2, - &mem_cfg->DqsMapCpu2DramCh3, - &mem_cfg->DqsMapCpu2DramCh4, - &mem_cfg->DqsMapCpu2DramCh5, - &mem_cfg->DqsMapCpu2DramCh6, - &mem_cfg->DqsMapCpu2DramCh7, + &mem_cfg->DqsMapCpu2DramMc0Ch0, + &mem_cfg->DqsMapCpu2DramMc0Ch1, + &mem_cfg->DqsMapCpu2DramMc0Ch2, + &mem_cfg->DqsMapCpu2DramMc0Ch3, + &mem_cfg->DqsMapCpu2DramMc1Ch0, + &mem_cfg->DqsMapCpu2DramMc1Ch1, + &mem_cfg->DqsMapCpu2DramMc1Ch2, + &mem_cfg->DqsMapCpu2DramMc1Ch3, }; - const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramCh0); + const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0); _Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH / 8, "Incorrect DQS UPD size!"); -- To view, visit https://review.coreboot.org/c/coreboot/+/60192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c543b2 Gerrit-Change-Number: 60192 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/var/scout: improve USB2 port 4 strength
by Kenneth Chan (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Rehan Ghori. Hello build bot (Jenkins), Tim Wawrzynczak, Joe Tessler, Rehan Ghori, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60131 to look at the new patch set (#6). Change subject: mb/google/hatch/var/scout: improve USB2 port 4 strength ...................................................................... mb/google/hatch/var/scout: improve USB2 port 4 strength Set USB2 port 4 pre emphasis to 15mV for passing USB2 SI - margin eye diagram. BUG=b:210755120 TEST=emerge-ambassadorcoreboot chromeos-bootimage; Build local fw and pass to HW for measuring USB2 port 4 eye diagram. Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8 --- M src/mainboard/google/hatch/variants/scout/overridetree.cb 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/60131/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/60131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8 Gerrit-Change-Number: 60131 Gerrit-PatchSet: 6 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Joe Tessler <jrt(a)google.com> Gerrit-Reviewer: Rehan Ghori <rehang(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rehan Ghori <rehang(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/hatch/var/scout: improve USB2 port 4 strength
by Kenneth Chan (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Rehan Ghori. Hello build bot (Jenkins), Tim Wawrzynczak, Joe Tessler, Rehan Ghori, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60131 to look at the new patch set (#5). Change subject: mb/google/hatch/var/scout: improve USB2 port 4 strength ...................................................................... mb/google/hatch/var/scout: improve USB2 port 4 strength Set USB2 port 4 pre emphasis to 15mV for passing USB2 SI - margin eye diagram. BUG=b:210755120 TEST=emerge-ambassadorcoreboot chromeos-bootimage; Build local fw and pass to HW for testing USB2 port 4. Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8 --- M src/mainboard/google/hatch/variants/scout/overridetree.cb 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/60131/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/60131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8 Gerrit-Change-Number: 60131 Gerrit-PatchSet: 5 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Joe Tessler <jrt(a)google.com> Gerrit-Reviewer: Rehan Ghori <rehang(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rehan Ghori <rehang(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/denverton_ns: Use `popcnt()` helper
by Angel Pons (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Mariusz Szafrański, Paul Menzel, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58912 ) Change subject: soc/intel/denverton_ns: Use `popcnt()` helper ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > i like the new commit message; at least for me it now mentions everything that i want to know Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/58912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae6b16991fcf07c9ad67d2b737e490212b8deedd Gerrit-Change-Number: 58912 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 17 Dec 2021 10:56:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/var/scout: improve USB2 port 4 strength
by Kenneth Chan (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Rehan Ghori. Hello Tim Wawrzynczak, Joe Tessler, Rehan Ghori, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60131 to look at the new patch set (#4). Change subject: mb/google/hatch/var/scout: improve USB2 port 4 strength ...................................................................... mb/google/hatch/var/scout: improve USB2 port 4 strength Set USB2 port 4 pre emphasis to 15mV for passing USB2 SI eye diagram fail. BUG=b:210755120 TEST=emerge-ambassadorcoreboot chromeos-bootimage; Build local fw and pass to HW for testing USB2 port 4. Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8 --- M src/mainboard/google/hatch/variants/scout/overridetree.cb 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/60131/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/60131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8 Gerrit-Change-Number: 60131 Gerrit-PatchSet: 4 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Joe Tessler <jrt(a)google.com> Gerrit-Reviewer: Rehan Ghori <rehang(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rehan Ghori <rehang(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/hatch/var/scout: improve USB2 port 4 strength
by Kenneth Chan (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Rehan Ghori. Hello Tim Wawrzynczak, Joe Tessler, Rehan Ghori, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60131 to look at the new patch set (#3). Change subject: mb/google/hatch/var/scout: improve USB2 port 4 strength ...................................................................... mb/google/hatch/var/scout: improve USB2 port 4 strength Set USB2 port 4 pre emphasis to 15mv for passing USB2 SI eye diagram fail. BUG=b:210755120 TEST=emerge-ambassadorcoreboot chromeos-bootimage; Build local fw and pass to HW for testing USB2 port 4. Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8 --- M src/mainboard/google/hatch/variants/scout/overridetree.cb 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/60131/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/60131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8 Gerrit-Change-Number: 60131 Gerrit-PatchSet: 3 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Joe Tessler <jrt(a)google.com> Gerrit-Reviewer: Rehan Ghori <rehang(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rehan Ghori <rehang(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2021