Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60172 )
Change subject: soc/amd/cezanne/acpi: Add support for RTC workaround
......................................................................
Patch Set 2:
(2 comments)
File src/soc/amd/cezanne/acpi/rtc_workaround.asl:
https://review.coreboot.org/c/coreboot/+/60172/comment/d1a86734_112b0d29
PS2, Line 23: _E2C
> I am not seeing a documentation for this method. […]
https://uefi.org/specs/ACPI/6.4/05_ACPI_Software_Programming_Model/ACPI_Sof…https://review.coreboot.org/c/coreboot/+/60172/comment/c0ca0ba8_43ec56de
PS2, Line 24: \_SB_
> Is this extra underscore a typo?
It wasn't intentional, but I think it's fine. I think ACPI names that are shorter than 4 characters have the _ suffix appended as padding.
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Change subject: starlabs: Convert EC_GPE_SCI to Kconfig
......................................................................
Patch Set 4: Code-Review+2
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Change subject: starlabs: Convert EC_GPE_SCI to Kconfig
......................................................................
Patch Set 4:
(3 comments)
File src/ec/starlabs/merlin/Kconfig:
https://review.coreboot.org/c/coreboot/+/60229/comment/22b18903_6a7e47dd
PS3, Line 59: GPI
> GP*E* […]
Done
File src/mainboard/starlabs/labtop/Kconfig:
https://review.coreboot.org/c/coreboot/+/60229/comment/13654fd8_5b9e4da7
PS3, Line 54: GPI
> GP*E*
Done
File src/mainboard/starlabs/labtop/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/60229/comment/2996d01f_86768874
PS3, Line 3: #define EC_GPE_SCI CONFIG_EC_GPE_SCI
> Please also drop the define. It's currently only used in one place in your EC code: […]
Done
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Hello build bot (Jenkins), Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60229
to look at the new patch set (#4).
Change subject: starlabs: Convert EC_GPE_SCI to Kconfig
......................................................................
starlabs: Convert EC_GPE_SCI to Kconfig
Convert EC_GPI_SCI to Kconfig option with default value of
0x50 that is used by most boards.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I8d47ebe76394fe1bcb217e0c6211db1566f82189
---
M src/ec/starlabs/merlin/Kconfig
M src/ec/starlabs/merlin/acpi/ec.asl
M src/mainboard/starlabs/labtop/Kconfig
M src/mainboard/starlabs/labtop/dsdt.asl
4 files changed, 8 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/60229/4
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Change subject: mb/google/dedede/var/cret: Generate new SPD ID for new memory parts
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Patch Set 4: Code-Review+2
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Change subject: mb/google/dedede/var/beadrix: Configure GPIO settings
......................................................................
Patch Set 2:
(2 comments)
File src/mainboard/google/dedede/variants/beadrix/gpio.c:
https://review.coreboot.org/c/coreboot/+/60245/comment/569488c8_e646b40c
PS2, Line 60: PAD_NC(GPP_H1, NONE),
It seems SD Card is not going to be supported. If so, SD Controller can be disabled in beadrix overridetree.cb?
device pci 14.5 off end # SDCard
https://review.coreboot.org/c/coreboot/+/60245/comment/a25e0e2d_73d2c05a
PS2, Line 63: /* TODO; static const struct pad_config lte_disable_pads[] = {
: PAD_NC(GPP_A10, NONE),
: PAD_NC(GPP_D0, NONE),
: PAD_NC(GPP_H17, NONE),
: }; */
Remove the TODO. Same comment for line 75 - 81.
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Change subject: mb/google/dedede/var/beadrix: Correct memory settings
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Patch Set 1: Code-Review+2
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Change subject: mb/google/dedede/var/beadrix: Add memory part and generate DRAM ID
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Patch Set 1: Code-Review+2
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Change subject: mb/google/dedede/var/magolor: Add stylus pen function
......................................................................
Patch Set 2:
(3 comments)
File src/mainboard/google/dedede/variants/magolor/gpio.c:
https://review.coreboot.org/c/coreboot/+/60185/comment/c4a7232b_556cd9d1
PS2, Line 9:
Nit: Remove the extra line
https://review.coreboot.org/c/coreboot/+/60185/comment/74e31cf6_7ffa19ae
PS2, Line 12:
Nit: Remove the extra line
https://review.coreboot.org/c/coreboot/+/60185/comment/a1c1d928_11a77a6a
PS2, Line 17: *num = ARRAY_SIZE(gpio_table);
This Firmware target is applied to Magolor/Maglia/Magma/Maglet etc. Is pen stuffed on all boards. I believe not. If so, can you please apply this configuration only on the boards where pen is stuffed and mark this GPIO as PAD_NC on other boards.
Otherwise you might end up receiving spurious wakes due to this GPIO configuration.
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