coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: google/herobrine: configure gpio to detect board ID.
by Shelley Chen (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Ravi kumar, Sudheer Amrabadi. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56642 ) Change subject: google/herobrine: configure gpio to detect board ID. ...................................................................... Patch Set 35: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56642/comment/deaac3ea_7290eb66 PS35, Line 9: change binary board ID to tri-state mode. I don't think that you're doing this anymore in this CL... -- To view, visit https://review.coreboot.org/c/coreboot/+/56642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6de2a7e7b11ecce8325e0fd44dc7221d73729390 Gerrit-Change-Number: 56642 Gerrit-PatchSet: 35 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Mon, 20 Dec 2021 19:11:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/herobrine: Initialize SPI FW for EC and TPM
by Shelley Chen (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Ravi kumar, Paul Menzel, mturney mturney, Sudheer Amrabadi, Julius Werner, Rajesh Patil. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50581 ) Change subject: mb/google/herobrine: Initialize SPI FW for EC and TPM ...................................................................... Patch Set 93: (1 comment) File src/mainboard/google/herobrine/Kconfig: https://review.coreboot.org/c/coreboot/+/50581/comment/1b151fdf_3ea5e089 PS93, Line 67: default 0xC > trailing whitespace Please fix. This is causing the verified-1. -- To view, visit https://review.coreboot.org/c/coreboot/+/50581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c Gerrit-Change-Number: 50581 Gerrit-PatchSet: 93 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Mon, 20 Dec 2021 19:09:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGE
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60139 ) Change subject: mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGE ...................................................................... mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGE Enable PSP_S0I3_RESUME_VERSTAGE for all guybrush based boards. This will cause verstage to run during s0i3 resume. The TPM will be reinitialized in verstage during s0i3 resume. This is necessary on guybrush boards because the TPM_RST_L pin is asserted by the SOC in S0i3. BUG=b:200578885 BRANCH=None TEST=TPM initialized after s0i3 Change-Id: I9d64fe92ffc67a421be6d5e013e636332ce86dd5 Signed-off-by: Rob Barnes <robbarnes(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60139 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/guybrush/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 7d9cd3d..ded66ab 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -39,6 +39,7 @@ select PCIEXP_COMMON_CLOCK select PCIEXP_L1_SUB_STATE select PSP_DISABLE_POSTCODES + select PSP_S0I3_RESUME_VERSTAGE if VBOOT_STARTS_BEFORE_BOOTBLOCK select SOC_AMD_CEZANNE select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF select SOC_AMD_COMMON_BLOCK_USE_ESPI 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d64fe92ffc67a421be6d5e013e636332ce86dd5 Gerrit-Change-Number: 60139 Gerrit-PatchSet: 5 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Correct S0i3 verstage softfuse bit
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60214 ) Change subject: soc/amd/cezanne: Correct S0i3 verstage softfuse bit ...................................................................... soc/amd/cezanne: Correct S0i3 verstage softfuse bit PSP_S0I3_RESUME_VERSTAGE softfuse bit is 58, not 40. BUG=b:202397678 BRANCH=None TEST=Boot guybrush, ensure S0i3 verstage runs with latest PSP. Change-Id: Ia27f6e48e345aac0d5f6579d663a6b655688239a Signed-off-by: Rob Barnes <robbarnes(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60214 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/soc/amd/cezanne/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index a05da8d..050ba44 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -111,7 +111,7 @@ endif ifeq ($(CONFIG_PSP_S0I3_RESUME_VERSTAGE),y) -PSP_SOFTFUSE_BITS += 40 +PSP_SOFTFUSE_BITS += 58 endif # Use additional Soft Fuse bits specified in Kconfig -- To view, visit https://review.coreboot.org/c/coreboot/+/60214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia27f6e48e345aac0d5f6579d663a6b655688239a Gerrit-Change-Number: 60214 Gerrit-PatchSet: 3 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: configs: Add config for Prodrive Hermes
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57168 ) Change subject: configs: Add config for Prodrive Hermes ...................................................................... configs: Add config for Prodrive Hermes Build-test the configuration Prodrive uses to build coreboot for their Hermes mainboard. Change-Id: I62e79d3143851bf14dfdbe70e60c60f13dd06c3f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57168 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Justin van Son <justin.van.son(a)prodrive-technologies.com> --- A configs/config.prodrive_hermes 1 file changed, 13 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Justin van Son: Looks good to me, but someone else must approve diff --git a/configs/config.prodrive_hermes b/configs/config.prodrive_hermes new file mode 100644 index 0000000..34556cc --- /dev/null +++ b/configs/config.prodrive_hermes @@ -0,0 +1,13 @@ +# Settings used by Prodrive to build coreboot for the Hermes +CONFIG_VENDOR_PRODRIVE=y +CONFIG_BOARD_PRODRIVE_HERMES=y +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Prodrive Techonologies B.V." +CONFIG_POST_IO=y +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_HERMES_USES_SPS_FIRMWARE=y +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_SMMSTORE=y +CONFIG_SMMSTORE_V2=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3=y +CONFIG_POST_DEVICE_LPC=y +CONFIG_MAINBOARD_SERIAL_NUMBER="N/A" -- To view, visit https://review.coreboot.org/c/coreboot/+/57168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62e79d3143851bf14dfdbe70e60c60f13dd06c3f Gerrit-Change-Number: 57168 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: commonlib: Add new TS for CSE firmware Sync
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59668 ) Change subject: commonlib: Add new TS for CSE firmware Sync ...................................................................... commonlib: Add new TS for CSE firmware Sync The patch defines new TS for CSE firmware synchronization. Also, removes unused TS_FIT_UCODE_LOADED TS. TEST=Build the code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I9ed82c5358eb94b5e7c91b9fd783c5e09189b77a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59668 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/commonlib/include/commonlib/timestamp_serialized.h 1 file changed, 4 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Maulik V Vaghela: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index de3e1bb..3d518b7 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -119,7 +119,8 @@ TS_ME_ICC_CONFIG_START = 945, TS_ME_HOST_BOOT_PREP_DONE = 946, TS_ME_RECEIVED_CRDA_FROM_PMC = 947, - TS_FIT_UCODE_LOADED = 948, + TS_START_CSE_FW_SYNC = 948, + TS_END_CSE_FW_SYNC = 949, /* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */ TS_FSP_MEMORY_INIT_START = 950, @@ -280,7 +281,8 @@ { TS_ME_ICC_CONFIG_START, "CSE started to handle ICC configuration"}, { TS_ME_HOST_BOOT_PREP_DONE, "CSE sent 'Host BIOS Prep Done' to PMC"}, { TS_ME_RECEIVED_CRDA_FROM_PMC, "CSE received 'CPU Reset Done Ack sent' from PMC"}, - { TS_FIT_UCODE_LOADED, "CPU has loaded UCODE/PCODE from FIT"}, + { TS_START_CSE_FW_SYNC, "starting CSE firmware sync"}, + { TS_END_CSE_FW_SYNC, "finished CSE firmware sync"}, /* FSP related timestamps */ { TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/59668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ed82c5358eb94b5e7c91b9fd783c5e09189b77a Gerrit-Change-Number: 59668 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/brask: Add wake-on-lan function
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60132 ) Change subject: mb/google/brya/var/brask: Add wake-on-lan function ...................................................................... mb/google/brya/var/brask: Add wake-on-lan function Add a wake-on-lan GPIO in devicetree for RTL8125. Modify GPIO A7 for wake-on-lan. BUG=b:204289108 TEST=emerge-brask coreboot chromeos-bootimage Signed-off-by: Rory Liu <rory.liu(a)quanta.corp-partner.google.com> Change-Id: Ic40301888a138df4a67398485f2a484d69b83fc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60132 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/brask/gpio.c M src/mainboard/google/brya/variants/brask/overridetree.cb 2 files changed, 3 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index ffdc285..5ad8e46 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -18,8 +18,8 @@ PAD_NC(GPP_A5, NONE), /* A6 : ESPI_ALERT1# ==> TP88 */ PAD_NC(GPP_A6, NONE), - /* A7 : SRCCLK_OE7# ==> NC */ - PAD_NC(GPP_A7, NONE), + /* A7 : SRCCLK_OE7# ==> LAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_A7, NONE, DEEP, EDGE_SINGLE), /* A8 : SRCCLKREQ7# ==> CLKREQ_7 */ PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK ==> ESPI_CLK */ diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index a7b763f..d1931cf 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -95,6 +95,7 @@ register "stop_delay_ms" = "12" # NIC needs time to quiesce register "stop_off_delay_ms" = "1" register "has_power_resource" = "1" + register "wake" = "GPE0_DW0_07" device pci 00.0 on end end end # RTL8125 Ethernet NIC -- To view, visit https://review.coreboot.org/c/coreboot/+/60132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic40301888a138df4a67398485f2a484d69b83fc9 Gerrit-Change-Number: 60132 Gerrit-PatchSet: 2 Gerrit-Owner: Rory Liu <rory.liu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Do not trigger crashlog on all resets by default
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59951 ) Change subject: soc/intel/common: Do not trigger crashlog on all resets by default ...................................................................... soc/intel/common: Do not trigger crashlog on all resets by default Crashlog has error records and PMC reset records two parts. When we send ipc cmd "PMC_IPC_CMD_ID_CRASHLOG_ON_RESET", PMC reset record is enabled. At each warm/cold/global reset, crashlog would be triggered. The cause of this crash would be "TRIGGER_ON_ALL_RESETS", it is used to catch unknown reset reason. At the same time, we would see [Hardware Error] in the kernel log. If we default enable TRIGGER_ON_ALL_RESETS, we would have too many false alarm. Now we disable PMC reset records part by default. And we could enable it when we need it for the debug purpose. The generated bert dump is under /var/spool/crash/, we could check this path to verify this CONFIG disable/enable status. BUG=b:202737385 TEST=No new bert dump after a warm reset. Signed-off-by: Curtis Chen <curtis.chen(a)intel.com> Change-Id: I3ec4ff3c8a3799156de030f4556fe6ce61305139 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59951 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/common/Kconfig.common M src/soc/intel/common/block/crashlog/crashlog.c M src/soc/intel/tigerlake/Kconfig 4 files changed, 18 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 9e69663..46fd742 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -333,13 +333,6 @@ int default 16 -config SOC_INTEL_CRASHLOG - def_bool n - select SOC_INTEL_COMMON_BLOCK_CRASHLOG - select ACPI_BERT - help - Enables CrashLog. - config ACPI_ADL_IPU_ES_SUPPORT def_bool n help diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common index 5f1f608..c7e1aec 100644 --- a/src/soc/intel/common/Kconfig.common +++ b/src/soc/intel/common/Kconfig.common @@ -79,4 +79,18 @@ hex default 0x800 +config SOC_INTEL_CRASHLOG + def_bool n + select SOC_INTEL_COMMON_BLOCK_CRASHLOG + select ACPI_BERT + help + Enables Crashlog. + +config SOC_INTEL_CRASHLOG_ON_RESET + def_bool n + help + Enables the PMC to collect crashlog records on every reset event. NOTE: + This will result in a BERT table being populated containing a PMC + crashlog record on every boot. + endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/block/crashlog/crashlog.c b/src/soc/intel/common/block/crashlog/crashlog.c index c3d0cfd..8c31d03 100644 --- a/src/soc/intel/common/block/crashlog/crashlog.c +++ b/src/soc/intel/common/block/crashlog/crashlog.c @@ -479,8 +479,10 @@ { if (pmc_crashlog_support() && cl_pmc_data_present() && (cl_get_pmc_record_size() > 0)) { - cl_pmc_en_gen_on_all_reboot(); - printk(BIOS_DEBUG, "Crashlog collection enabled on every reboot.\n"); + if (CONFIG(SOC_INTEL_CRASHLOG_ON_RESET)) { + cl_pmc_en_gen_on_all_reboot(); + printk(BIOS_DEBUG, "Crashlog collection enabled on every reboot.\n"); + } cl_get_pmc_sram_data(); } else { printk(BIOS_DEBUG, "Skipping PMC crashLog collection. Data not present.\n"); diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index a7b3ae4..cf59b60 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -284,13 +284,6 @@ int default 16 -config SOC_INTEL_CRASHLOG - def_bool n - select SOC_INTEL_COMMON_BLOCK_CRASHLOG - select ACPI_BERT - help - Enables CrashLog. - # Intel recommends reserving the following resources per USB4 root port, # from TGL BIOS Spec (doc #611569) Revision 0.7.6 Section 7.2.5.1.5 # - 42 buses -- To view, visit https://review.coreboot.org/c/coreboot/+/59951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ec4ff3c8a3799156de030f4556fe6ce61305139 Gerrit-Change-Number: 59951 Gerrit-PatchSet: 7 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/vell: update memory settings
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59334 ) Change subject: mb/google/brya/var/vell: update memory settings ...................................................................... mb/google/brya/var/vell: update memory settings DQ/DQS info from Intel_Platform_DQ_DQS_RCOMP_Info_Utility GPIO_MEN_CONFIG_0 GPP_E11 to GPP_E3 GPIO_MEN_CONFIG_3 GPP_E12 to GPP_E7 GPIO_MEM_CH_SEL_GPP_E5 GPP_E13 to GPP_E5 BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59334 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/vell/Makefile.inc A src/mainboard/google/brya/variants/vell/memory.c 2 files changed, 104 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/vell/Makefile.inc b/src/mainboard/google/brya/variants/vell/Makefile.inc index 58c4d79..20c6c3c 100644 --- a/src/mainboard/google/brya/variants/vell/Makefile.inc +++ b/src/mainboard/google/brya/variants/vell/Makefile.inc @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +romstage-y += memory.c romstage-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/vell/memory.c b/src/mainboard/google/brya/variants/vell/memory.c new file mode 100644 index 0000000..afbe114 --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/memory.c @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <console/console.h> +#include <soc/romstage.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP5X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = { 40, 36, 35, 35, 35 }, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 4, 0, 1, 3, 7, 5, 6, 2, }, + .dq1 = { 9, 13, 12, 8, 15, 10, 14, 11, }, + }, + .ddr1 = { + .dq0 = { 0, 2, 1, 3, 7, 5, 6, 4, }, + .dq1 = { 10, 8, 11, 9, 13, 15, 14, 12, }, + }, + .ddr2 = { + .dq0 = { 3, 7, 2, 6, 4, 1, 5, 0, }, + .dq1 = { 12, 14, 15, 13, 11, 8, 10, 9, }, + }, + .ddr3 = { + .dq0 = { 7, 6, 4, 5, 0, 3, 1, 2, }, + .dq1 = { 9, 13, 8, 12, 15, 10, 14, 11, }, + }, + .ddr4 = { + .dq0 = { 7, 5, 4, 6, 2, 0, 1, 3, }, + .dq1 = { 15, 14, 12, 13, 10, 9, 8, 11, }, + }, + .ddr5 = { + .dq0 = { 3, 7, 2, 6, 0, 4, 5, 1, }, + .dq1 = { 9, 10, 11, 8, 12, 15, 13, 14, }, + }, + .ddr6 = { + .dq0 = { 1, 0, 3, 2, 7, 5, 4, 6, }, + .dq1 = { 11, 8, 10, 9, 12, 14, 13, 15, }, + }, + .ddr7 = { + .dq0 = { 3, 2, 1, 0, 7, 5, 6, 4, }, + .dq1 = { 8, 9, 10, 12, 14, 11, 13, 15, }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .ect = true, /* Enable Early Command Training */ + + .lp5x_config = { + .ccc_config = 0xff, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E3 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E1 + * GPIO_MEM_CONFIG_3 GPP_E7 + */ + gpio_t spd_gpios[] = { + GPP_E3, + GPP_E2, + GPP_E1, + GPP_E7, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* GPIO_MEM_CH_SEL GPP_E5 */ + return gpio_get(GPP_E5); +} 22 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Gerrit-Change-Number: 59334 Gerrit-PatchSet: 25 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/vell: update gpio override
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59305 ) Change subject: mb/google/brya/var/vell: update gpio override ...................................................................... mb/google/brya/var/vell: update gpio override Configure GPIOs according to schematics BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Icc91866f7555c294af7eed9e5d1550e73d8059d0 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59305 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- A src/mainboard/google/brya/variants/vell/Makefile.inc A src/mainboard/google/brya/variants/vell/gpio.c 2 files changed, 181 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/vell/Makefile.inc b/src/mainboard/google/brya/variants/vell/Makefile.inc new file mode 100644 index 0000000..58c4d79 --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/Makefile.inc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/vell/gpio.c b/src/mainboard/google/brya/variants/vell/gpio.c new file mode 100644 index 0000000..7028222 --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/gpio.c @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A11 : PMC_I2C_SDA ==> NC */ + PAD_NC(GPP_A11, NONE), + + /* B2 : VRALERT# ==> RGB_RST_ODL */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), + /* B15 : TIME_SYNC0 ==> NC */ + PAD_NC(GPP_B15, NONE), + + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + + /* D3 : ISH_GP3 ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D3, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> USB_C3_LSX_TX */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4), + /* D12 : ISH_SPI_MOSI ==> USB_C3_LSX_RX_STRAP */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF4), + + /* E3 : PROC_GP0 ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_E3, NONE, DEEP), + /* E5 : SATA_DEVSLP1 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E5, NONE, DEEP), + /* E7 : PROC_GP1 ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + /* E10 : THC0_SPI1_CS# ==> UWB_GSPI0_CS */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF2), + /* E11 : THC0_SPI1_CLK ==> UWB_CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2), + /* E12 : THC0_SPI1_IO1 ==> UWB_GSPI0_DI */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3), + /* E13 : THC0_SPI1_IO2 ==> UWB_GSPI0_DO */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3), + /* E22 : DDPA_CTRLCLK ==> WWAN_CONFIG0 */ + PAD_CFG_GPI(GPP_E22, NONE, DEEP), + /* E23 : DDPA_CTRLDATA ==> USB_C3_OC_ODL */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + + /* F19 : NC */ + PAD_NC(GPP_F19, NONE), + + /* H12 : I2C7_SDA ==> UWB_SDA */ + PAD_CFG_NF(GPP_H12, NONE, DEEP, NF1), + /* H13 : I2C7_SCL ==> UWB_SCL */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + /* H15 : DDPB_CTRLCLK ==> USB_C3_AUX_DC_P */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF6), + /* H17 : DDPB_CTRLDATA ==> USB_C3_AUX_DC_N */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF6), + + /* R4 : HDA_RST# ==> DMIC_CLK0_R */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), + /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), + /* R6 : I2S2_TXD ==> DMIC_CLK1_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), + /* R7 : I2S2_RXD ==> DMIC_DATA1_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), + + /* S0 : SNDW0_CLK ==> I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), + /* S1 : SNDW0_DATA ==> I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF2), + /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF3), + /* S3 : SNDW1_DATA ==> I2S_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF3), + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : SNDW3_CLK ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : SNDW3_DATA ==> NC */ + PAD_NC(GPP_S7, NONE), + + /* GPD11: LANPHYC ==> WWAN_CONFIG1 */ + PAD_NC(GPD11, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D3 : ISH_GP3 ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D3, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> USB_C0_LSX_SOC_TX */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4), + + /* E3 : PROC_GP0 ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_E3, NONE, DEEP), + /* E5 : SATA_DEVSLP1 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E5, NONE, DEEP), + /* E7 : PROC_GP1 ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* E16 : RSVD_TP ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_E16, 0, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + + /*Add virtual GPIOs for CPU PCIe RP*/ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc91866f7555c294af7eed9e5d1550e73d8059d0 Gerrit-Change-Number: 59305 Gerrit-PatchSet: 29 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit December 2021