coreboot-gerrit December 2021

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Change in coreboot[master]: libpayload: Add -Wno-address-of-packed-member for ARCH_MOCK
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60169 ) Change subject: libpayload: Add -Wno-address-of-packed-member for ARCH_MOCK ...................................................................... libpayload: Add -Wno-address-of-packed-member for ARCH_MOCK When compiling libpayload using x86_64 toolchain for ARCH_MOCK compiler reports an error about gerring address of packed member. Until now it had to be disabled by passing -Wno-address-of-packed-member to EXTRA_CFLAGS. This patch disables this warning. Change-Id: I9a948fabe66f7297632ecaca8ec1bfa5c842b750 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60169 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/arch/mock/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/payloads/libpayload/arch/mock/Makefile.inc b/payloads/libpayload/arch/mock/Makefile.inc index f15f0f9..415886a 100644 --- a/payloads/libpayload/arch/mock/Makefile.inc +++ b/payloads/libpayload/arch/mock/Makefile.inc @@ -5,3 +5,5 @@ libc-y += virtual.c libcbfs-$(CONFIG_LP_CBFS) += mock_media.c + +CFLAGS += -Wno-address-of-packed-member -- To view, visit https://review.coreboot.org/c/coreboot/+/60169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a948fabe66f7297632ecaca8ec1bfa5c842b750 Gerrit-Change-Number: 60169 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetrees
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60175 ) Change subject: mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetrees ...................................................................... mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetrees None of the touchscreens used in the brya program (any brya board) should require exporting of GPIOs in the ACPI _CRS method for any i2c device. This can cause i2c devices to malfunction or cause timing sequence violations if: 1) ACPI exports a PowerResource for the device that uses GPIOs that are also exported in _CRS 2) The kernel driver for the device uses the GPIOs exported in _CRS for its own purposes. This means the state of the pin is out of sync between platform firmware and the kernel. The Linux ELAN I2C touchcsreen driver (https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…) is one example of this. Therefore, add disable_gpio_export_in_crs to all brya variants that use the drivers/i2c/generic or drivers/i2c/hid chip drivers. Change-Id: Ib4475bd0dc885e230911de6298fd95baa868ef29 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60175 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/brya/variants/anahera/overridetree.cb M src/mainboard/google/brya/variants/anahera4es/overridetree.cb M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/overridetree.cb M src/mainboard/google/brya/variants/kano/overridetree.cb M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko4es/overridetree.cb M src/mainboard/google/brya/variants/vell/overridetree.cb 13 files changed, 20 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index dc563a4..118ce0c 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -215,6 +215,7 @@ register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 10 on end end chip drivers/i2c/hid @@ -229,6 +230,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 40 on end end diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb index dc563a4..118ce0c 100644 --- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb @@ -215,6 +215,7 @@ register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 10 on end end chip drivers/i2c/hid @@ -229,6 +230,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 40 on end end diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index c2da329..f9301fe 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -260,6 +260,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 4bfe124..3d8f52b 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -217,6 +217,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x15 on end end diff --git a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb index 5d6d4fc..d0d54d7 100644 --- a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb @@ -173,6 +173,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x15 on end end diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index a908a7b..a4a5c54 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -425,6 +425,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x10 on end end diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 64d0a8f..0ddf2b1 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -236,6 +236,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x10 on end end @@ -251,6 +252,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x40 on end end diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb index ce6bec5..fffc1d0 100644 --- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb @@ -223,6 +223,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x10 on end end @@ -238,6 +239,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x40 on end end diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 617ebc5..5aa84bdc 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -386,6 +386,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x15 on end end diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index 9531e5e..9ffc6a0 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -270,6 +270,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x15 on end end diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index ff4feef..985745f 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -292,6 +292,7 @@ # Parameter T4 >= 1ms register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end @@ -307,6 +308,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 10 on end end end diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb index d485662..dbca8ee 100644 --- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb @@ -292,6 +292,7 @@ # Parameter T4 >= 1ms register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end @@ -307,6 +308,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 10 on end end end diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index a65c859..483dce7 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -191,6 +191,7 @@ register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 10 on end end chip drivers/i2c/hid @@ -205,6 +206,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 40 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/60175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4475bd0dc885e230911de6298fd95baa868ef29 Gerrit-Change-Number: 60175 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/primus: Update thermal table for primus
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60101 ) Change subject: mb/google/brya/var/primus: Update thermal table for primus ...................................................................... mb/google/brya/var/primus: Update thermal table for primus - Because primus have five sensors,we need to define 5 sensors. BUG=b:200836803 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Signed-off-by: Ariel_Fang <ariel_fang(a)wistron.corp-partner.google.com> Change-Id: I02fb8eee644f9999d9c5d48e3a056499d968f85d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60101 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb 2 files changed, 18 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 58c52a7..64d0a8f 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -90,19 +90,22 @@ device ref dtt on chip drivers/intel/dptf ## sensor information - register "options.tsr[0].desc" = ""SSD"" - register "options.tsr[1].desc" = ""CHARGER"" - register "options.tsr[2].desc" = ""MEMORY"" - register "options.tsr[3].desc" = ""TYPEC"" + register "options.tsr[0].desc" = ""CPU"" + register "options.tsr[1].desc" = ""SSD"" + register "options.tsr[2].desc" = ""CHARGER"" + register "options.tsr[3].desc" = ""MEMORY"" + register "options.tsr[4].desc" = ""TYPEC"" # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 5000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 90, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 92, 5000), [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 90, 5000), [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 5000), + [5] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_4, 90, 5000), + }" ## Critical Policy @@ -112,6 +115,7 @@ [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 89, SHUTDOWN), [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), + [5] = DPTF_CRITICAL(TEMP_SENSOR_4, 85, SHUTDOWN), }" register "controls.power_limits" = "{ diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb index 22d61b0..ce6bec5 100644 --- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb @@ -84,19 +84,22 @@ device ref dtt on chip drivers/intel/dptf ## sensor information - register "options.tsr[0].desc" = ""SSD"" - register "options.tsr[1].desc" = ""CHARGER"" - register "options.tsr[2].desc" = ""MEMORY"" - register "options.tsr[3].desc" = ""TYPEC"" + register "options.tsr[0].desc" = ""CPU"" + register "options.tsr[1].desc" = ""SSD"" + register "options.tsr[2].desc" = ""CHARGER"" + register "options.tsr[3].desc" = ""MEMORY"" + register "options.tsr[4].desc" = ""TYPEC"" # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 5000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 90, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 92, 5000), [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 90, 5000), [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 5000), + [5] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_4, 90, 5000), + }" ## Critical Policy @@ -106,6 +109,7 @@ [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 89, SHUTDOWN), [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), + [5] = DPTF_CRITICAL(TEMP_SENSOR_4, 85, SHUTDOWN), }" register "controls.power_limits" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/60101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02fb8eee644f9999d9c5d48e3a056499d968f85d Gerrit-Change-Number: 60101 Gerrit-PatchSet: 8 Gerrit-Owner: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/variants/brask: Disable autonomous GPIO power management
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60100 ) Change subject: mb/google/brya/variants/brask: Disable autonomous GPIO power management ...................................................................... mb/google/brya/variants/brask: Disable autonomous GPIO power management We experienced the `Cr50 i2c TPM IRQ timeout!` error when the device executed the reboot test even though we have updated the Cr50 firmware to the latest version 0.6.70. Besides, we also experienced the device failed with the IRQ timeout when using the 0.3.22 Cr50 firmware in the factory. In order to fix these issues, we disable the gpio power management from the devicetree. BUG=b:210540890 TEST=reboot 100 cycles without the error message. Change-Id: I5f18fea5bc28493107c6d4951805de640a0b8ae5 Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60100 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/google/brya/variants/brask/overridetree.cb 1 file changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index 63a683d..a7b763f 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -1,4 +1,14 @@ chip soc/intel/alderlake + # This disables autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" device domain 0 on device ref dtt on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/60100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f18fea5bc28493107c6d4951805de640a0b8ae5 Gerrit-Change-Number: 60100 Gerrit-PatchSet: 6 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/lpc/espi_util: use enum cb_err type for return values
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60208 ) Change subject: soc/amd/common/lpc/espi_util: use enum cb_err type for return values ...................................................................... soc/amd/common/lpc/espi_util: use enum cb_err type for return values Use enum cb_err as return type of all remaining functions that only return success or failure. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6cff8480d99641fdfb613bb3e4edc4055ad5efc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60208 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/espi.h M src/soc/amd/common/block/lpc/espi_util.c 2 files changed, 29 insertions(+), 33 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index f9e2570..adb9a1d 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -3,8 +3,7 @@ #ifndef AMD_BLOCK_ESPI_H #define AMD_BLOCK_ESPI_H -#include <stdint.h> -#include <stddef.h> +#include <types.h> /* eSPI MMIO base lives at an offset of 0x10000 from the address in SPI BAR. */ #define ESPI_OFFSET_FROM_BAR 0x10000 @@ -106,15 +105,13 @@ /* * Open I/O window using the provided base and size. - * Return value: 0 = success, -1 = error. */ -int espi_open_io_window(uint16_t base, size_t size); +enum cb_err espi_open_io_window(uint16_t base, size_t size); /* * Open MMIO window using the provided base and size. - * Return value: 0 = success, -1 = error. */ -int espi_open_mmio_window(uint32_t base, size_t size); +enum cb_err espi_open_mmio_window(uint32_t base, size_t size); /* * In cases where eSPI BAR is statically provided by SoC, use that BAR instead of reading @@ -124,9 +121,8 @@ /* * Perform eSPI connection setup to the slave. Currently, this supports slave0 only. - * Returns 0 on success and -1 on error. */ -int espi_setup(void); +enum cb_err espi_setup(void); /* Run mainboard configuration needed to set up eSPI */ void mb_set_up_early_espi(void); diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 70bd351..1d7be67 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -156,7 +156,7 @@ espi_write8(ESPI_IO_RANGE_SIZE(idx), size - 1); } -static int espi_open_generic_io_window(uint16_t base, size_t size) +static enum cb_err espi_open_generic_io_window(uint16_t base, size_t size) { size_t win_size; int idx; @@ -186,24 +186,24 @@ printk(BIOS_ERR, "Cannot open IO window base %x size %zx\n", base, size); printk(BIOS_ERR, "ERROR: No more available IO windows!\n"); - return -1; + return CB_ERR; } espi_write_io_window(idx, base, win_size); espi_enable_decode(ESPI_DECODE_IO_RANGE_EN(idx)); } - return 0; + return CB_SUCCESS; } -int espi_open_io_window(uint16_t base, size_t size) +enum cb_err espi_open_io_window(uint16_t base, size_t size) { int std_io; std_io = espi_std_io_decode(base, size); if (std_io != -1) { espi_enable_decode(std_io); - return 0; + return CB_SUCCESS; } else { return espi_open_generic_io_window(base, size); } @@ -248,7 +248,7 @@ espi_write16(ESPI_MMIO_RANGE_SIZE(idx), size - 1); } -int espi_open_mmio_window(uint32_t base, size_t size) +enum cb_err espi_open_mmio_window(uint32_t base, size_t size) { size_t win_size; int idx; @@ -278,14 +278,14 @@ printk(BIOS_ERR, "Cannot open IO window base %x size %zx\n", base, size); printk(BIOS_ERR, "ERROR: No more available MMIO windows!\n"); - return -1; + return CB_ERR; } espi_write_mmio_window(idx, base, win_size); espi_enable_decode(ESPI_DECODE_MMIO_RANGE_EN(idx)); } - return 0; + return CB_SUCCESS; } static const struct espi_config *espi_get_config(void) @@ -298,7 +298,7 @@ return &soc_cfg->espi_config; } -static int espi_configure_decodes(const struct espi_config *cfg) +static enum cb_err espi_configure_decodes(const struct espi_config *cfg) { int i; @@ -308,11 +308,11 @@ if (cfg->generic_io_range[i].size == 0) continue; if (espi_open_generic_io_window(cfg->generic_io_range[i].base, - cfg->generic_io_range[i].size)) - return -1; + cfg->generic_io_range[i].size) != CB_SUCCESS) + return CB_ERR; } - return 0; + return CB_SUCCESS; } #define ESPI_DN_TX_HDR0 0x00 @@ -947,7 +947,7 @@ espi_write32(ESPI_GLOBAL_CONTROL_1, global_ctrl_reg); } -int espi_setup(void) +enum cb_err espi_setup(void) { uint32_t slave_caps; const struct espi_config *cfg = espi_get_config(); @@ -974,7 +974,7 @@ */ if (espi_send_reset() != CB_SUCCESS) { printk(BIOS_ERR, "Error: In-band reset failed!\n"); - return -1; + return CB_ERR; } espi_set_initial_config(cfg); @@ -984,7 +984,7 @@ */ if (espi_get_general_configuration(&slave_caps) != CB_SUCCESS) { printk(BIOS_ERR, "Error: Slave GET_CONFIGURATION failed!\n"); - return -1; + return CB_ERR; } /* @@ -994,7 +994,7 @@ */ if (espi_set_general_configuration(cfg, slave_caps) != CB_SUCCESS) { printk(BIOS_ERR, "Error: Slave SET_CONFIGURATION failed!\n"); - return -1; + return CB_ERR; } /* @@ -1010,39 +1010,39 @@ /* Set up VW first so we can deassert PLTRST#. */ if (espi_setup_vw_channel(cfg, slave_caps) != CB_SUCCESS) { printk(BIOS_ERR, "Error: Setup VW channel failed!\n"); - return -1; + return CB_ERR; } /* Assert PLTRST# if VW channel is enabled by mainboard. */ if (espi_send_pltrst(cfg, true) != CB_SUCCESS) { printk(BIOS_ERR, "Error: PLTRST# assertion failed!\n"); - return -1; + return CB_ERR; } /* De-assert PLTRST# if VW channel is enabled by mainboard. */ if (espi_send_pltrst(cfg, false) != CB_SUCCESS) { printk(BIOS_ERR, "Error: PLTRST# deassertion failed!\n"); - return -1; + return CB_ERR; } if (espi_setup_periph_channel(cfg, slave_caps) != CB_SUCCESS) { printk(BIOS_ERR, "Error: Setup Periph channel failed!\n"); - return -1; + return CB_ERR; } if (espi_setup_oob_channel(cfg, slave_caps) != CB_SUCCESS) { printk(BIOS_ERR, "Error: Setup OOB channel failed!\n"); - return -1; + return CB_ERR; } if (espi_setup_flash_channel(cfg, slave_caps) != CB_SUCCESS) { printk(BIOS_ERR, "Error: Setup Flash channel failed!\n"); - return -1; + return CB_ERR; } - if (espi_configure_decodes(cfg) == -1) { + if (espi_configure_decodes(cfg) != CB_SUCCESS) { printk(BIOS_ERR, "Error: Configuring decodes failed!\n"); - return -1; + return CB_ERR; } /* Enable subtractive decode if configured */ @@ -1053,7 +1053,7 @@ printk(BIOS_SPEW, "Finished initializing ESPI.\n"); - return 0; + return CB_SUCCESS; } /* Setup eSPI with any mainboard specific initialization. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cff8480d99641fdfb613bb3e4edc4055ad5efc6 Gerrit-Change-Number: 60208 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/amd/common/lpc/espi_util: use enum cb_err type for return values
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60207 ) Change subject: soc/amd/common/lpc/espi_util: use enum cb_err type for return values ...................................................................... soc/amd/common/lpc/espi_util: use enum cb_err type for return values Use enum cb_err as return type of all functions that aren't exposed outside of this compilation unit. The checks if a function has returned a failure are replaced with checks if the return value isn't CB_SUCCESS which is equivalent if only those two values are used, but also detects a failure if any unexpected value would be returned. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If8c703f62babac31948d0878e91bd31b31bebc01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60207 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 75 insertions(+), 71 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index d495a0e..70bd351 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -426,7 +426,7 @@ } __packed; /* Wait up to ESPI_CMD_TIMEOUT_US for hardware to clear DNCMD_STATUS bit. */ -static int espi_wait_ready(void) +static enum cb_err espi_wait_ready(void) { struct stopwatch sw; union espi_txhdr0 hdr0; @@ -435,10 +435,10 @@ do { hdr0.val = espi_read32(ESPI_DN_TX_HDR0); if (!hdr0.cmd_sts) - return 0; + return CB_SUCCESS; } while (!stopwatch_expired(&sw)); - return -1; + return CB_ERR; } /* Clear interrupt status register */ @@ -453,7 +453,7 @@ * Wait up to ESPI_CMD_TIMEOUT_US for interrupt status register to update after sending a * command. */ -static int espi_poll_status(uint32_t *status) +static enum cb_err espi_poll_status(uint32_t *status) { struct stopwatch sw; @@ -461,12 +461,12 @@ do { *status = espi_read32(ESPI_SLAVE0_INT_STS); if (*status) - return 0; + return CB_SUCCESS; } while (!stopwatch_expired(&sw)); printk(BIOS_ERR, "Error: eSPI timed out waiting for status update.\n"); - return -1; + return CB_ERR; } static void espi_show_failure(const struct espi_cmd *cmd, const char *str, uint32_t status) @@ -476,7 +476,7 @@ printk(BIOS_ERR, "%s (Status = 0x%x)\n", str, status); } -static int espi_send_command(const struct espi_cmd *cmd) +static enum cb_err espi_send_command(const struct espi_cmd *cmd) { uint32_t status; @@ -484,9 +484,9 @@ printk(BIOS_DEBUG, "eSPI cmd0-cmd2: %08x %08x %08x data: %08x.\n", cmd->hdr0.val, cmd->hdr1.val, cmd->hdr2.val, cmd->data.val); - if (espi_wait_ready() == -1) { + if (espi_wait_ready() != CB_SUCCESS) { espi_show_failure(cmd, "Error: eSPI was not ready to accept a command", 0); - return -1; + return CB_ERR; } espi_clear_status(); @@ -498,36 +498,36 @@ /* Dword 0 must be last as this write triggers the transaction */ espi_write32(ESPI_DN_TX_HDR0, cmd->hdr0.val); - if (espi_wait_ready() == -1) { + if (espi_wait_ready() != CB_SUCCESS) { espi_show_failure(cmd, "Error: eSPI timed out waiting for command to complete", 0); - return -1; + return CB_ERR; } - if (espi_poll_status(&status) == -1) { + if (espi_poll_status(&status) != CB_SUCCESS) { espi_show_failure(cmd, "Error: eSPI poll status failed", 0); - return -1; + return CB_ERR; } /* If command did not complete downstream, return error. */ if (!(status & ESPI_STATUS_DNCMD_COMPLETE)) { espi_show_failure(cmd, "Error: eSPI downstream command completion failure", status); - return -1; + return CB_ERR; } if (status & ~(ESPI_STATUS_DNCMD_COMPLETE | cmd->expected_status_codes)) { espi_show_failure(cmd, "Error: unexpected eSPI status register bits set", status); - return -1; + return CB_ERR; } espi_write32(ESPI_SLAVE0_INT_STS, status); - return 0; + return CB_SUCCESS; } -static int espi_send_reset(void) +static enum cb_err espi_send_reset(void) { struct espi_cmd cmd = { .hdr0 = { @@ -566,7 +566,7 @@ return espi_send_command(&cmd); } -static int espi_send_pltrst(const struct espi_config *mb_cfg, bool assert) +static enum cb_err espi_send_pltrst(const struct espi_config *mb_cfg, bool assert) { struct espi_cmd cmd = { .hdr0 = { @@ -582,7 +582,7 @@ }; if (!mb_cfg->vw_ch_en) - return 0; + return CB_SUCCESS; return espi_send_command(&cmd); } @@ -594,7 +594,7 @@ #define ESPI_CONFIGURATION_HDATA0(a) (((a) >> 8) & 0xff) #define ESPI_CONFIGURATION_HDATA1(a) ((a) & 0xff) -static int espi_get_configuration(uint16_t slave_reg_addr, uint32_t *config) +static enum cb_err espi_get_configuration(uint16_t slave_reg_addr, uint32_t *config) { struct espi_cmd cmd = { .hdr0 = { @@ -607,8 +607,8 @@ *config = 0; - if (espi_send_command(&cmd)) - return -1; + if (espi_send_command(&cmd) != CB_SUCCESS) + return CB_ERR; *config = espi_read32(ESPI_DN_TX_HDR1); @@ -616,10 +616,10 @@ printk(BIOS_DEBUG, "Get configuration for slave register(0x%x): 0x%x\n", slave_reg_addr, *config); - return 0; + return CB_SUCCESS; } -static int espi_set_configuration(uint16_t slave_reg_addr, uint32_t config) +static enum cb_err espi_set_configuration(uint16_t slave_reg_addr, uint32_t config) { struct espi_cmd cmd = { .hdr0 = { @@ -636,13 +636,13 @@ return espi_send_command(&cmd); } -static int espi_get_general_configuration(uint32_t *config) +static enum cb_err espi_get_general_configuration(uint32_t *config) { - if (espi_get_configuration(ESPI_SLAVE_GENERAL_CFG, config) == -1) - return -1; + if (espi_get_configuration(ESPI_SLAVE_GENERAL_CFG, config) != CB_SUCCESS) + return CB_ERR; espi_show_slave_general_configuration(*config); - return 0; + return CB_SUCCESS; } static void espi_set_io_mode_config(enum espi_io_mode mb_io_mode, uint32_t slave_caps, @@ -737,7 +737,8 @@ } } -static int espi_set_general_configuration(const struct espi_config *mb_cfg, uint32_t slave_caps) +static enum cb_err espi_set_general_configuration(const struct espi_config *mb_cfg, + uint32_t slave_caps) { uint32_t slave_config = 0; uint32_t ctrlr_config = 0; @@ -757,14 +758,14 @@ espi_show_slave_general_configuration(slave_config); - if (espi_set_configuration(ESPI_SLAVE_GENERAL_CFG, slave_config) == -1) - return -1; + if (espi_set_configuration(ESPI_SLAVE_GENERAL_CFG, slave_config) != CB_SUCCESS) + return CB_ERR; espi_write32(ESPI_SLAVE0_CONFIG, ctrlr_config); - return 0; + return CB_SUCCESS; } -static int espi_wait_channel_ready(uint16_t slave_reg_addr) +static enum cb_err espi_wait_channel_ready(uint16_t slave_reg_addr) { struct stopwatch sw; uint32_t config; @@ -773,12 +774,12 @@ do { espi_get_configuration(slave_reg_addr, &config); if (espi_slave_is_channel_ready(config)) - return 0; + return CB_SUCCESS; } while (!stopwatch_expired(&sw)); printk(BIOS_ERR, "Error: Channel is not ready after %d usec (slave addr: 0x%x)\n", ESPI_CH_READY_TIMEOUT_US, slave_reg_addr); - return -1; + return CB_ERR; } @@ -791,23 +792,24 @@ espi_write32(ESPI_SLAVE0_CONFIG, reg); } -static int espi_set_channel_configuration(uint32_t slave_config, uint32_t slave_reg_addr, - uint32_t ctrlr_enable) +static enum cb_err espi_set_channel_configuration(uint32_t slave_config, + uint32_t slave_reg_addr, + uint32_t ctrlr_enable) { - if (espi_set_configuration(slave_reg_addr, slave_config) == -1) - return -1; + if (espi_set_configuration(slave_reg_addr, slave_config) != CB_SUCCESS) + return CB_ERR; if (!(slave_config & ESPI_SLAVE_CHANNEL_ENABLE)) - return 0; + return CB_SUCCESS; - if (espi_wait_channel_ready(slave_reg_addr) == -1) - return -1; + if (espi_wait_channel_ready(slave_reg_addr) != CB_SUCCESS) + return CB_ERR; espi_enable_ctrlr_channel(ctrlr_enable); - return 0; + return CB_SUCCESS; } -static int espi_setup_vw_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) +static enum cb_err espi_setup_vw_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) { uint32_t slave_vw_caps; uint32_t ctrlr_vw_caps; @@ -817,15 +819,15 @@ uint32_t slave_config; if (!mb_cfg->vw_ch_en) - return 0; + return CB_SUCCESS; if (!espi_slave_supports_vw_channel(slave_caps)) { printk(BIOS_ERR, "Error: eSPI slave doesn't support VW channel!\n"); - return -1; + return CB_ERR; } - if (espi_get_configuration(ESPI_SLAVE_VW_CFG, &slave_vw_caps) == -1) - return -1; + if (espi_get_configuration(ESPI_SLAVE_VW_CFG, &slave_vw_caps) != CB_SUCCESS) + return CB_ERR; ctrlr_vw_caps = espi_read32(ESPI_MASTER_CAP); ctrlr_vw_count_supp = (ctrlr_vw_caps & ESPI_VW_MAX_SIZE_MASK) >> ESPI_VW_MAX_SIZE_SHIFT; @@ -837,15 +839,16 @@ return espi_set_channel_configuration(slave_config, ESPI_SLAVE_VW_CFG, ESPI_VW_CH_EN); } -static int espi_setup_periph_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) +static enum cb_err espi_setup_periph_channel(const struct espi_config *mb_cfg, + uint32_t slave_caps) { uint32_t slave_config; /* Peripheral channel requires BME bit to be set when enabling the channel. */ const uint32_t slave_en_mask = ESPI_SLAVE_CHANNEL_ENABLE | ESPI_SLAVE_PERIPH_BUS_MASTER_ENABLE; - if (espi_get_configuration(ESPI_SLAVE_PERIPH_CFG, &slave_config) == -1) - return -1; + if (espi_get_configuration(ESPI_SLAVE_PERIPH_CFG, &slave_config) != CB_SUCCESS) + return CB_ERR; /* * Peripheral channel is the only one which is enabled on reset. So, if the mainboard @@ -855,7 +858,7 @@ if (mb_cfg->periph_ch_en) { if (!espi_slave_supports_periph_channel(slave_caps)) { printk(BIOS_ERR, "Error: eSPI slave doesn't support periph channel!\n"); - return -1; + return CB_ERR; } slave_config |= slave_en_mask; } else { @@ -868,20 +871,20 @@ ESPI_PERIPH_CH_EN); } -static int espi_setup_oob_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) +static enum cb_err espi_setup_oob_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) { uint32_t slave_config; if (!mb_cfg->oob_ch_en) - return 0; + return CB_SUCCESS; if (!espi_slave_supports_oob_channel(slave_caps)) { printk(BIOS_ERR, "Error: eSPI slave doesn't support OOB channel!\n"); - return -1; + return CB_ERR; } - if (espi_get_configuration(ESPI_SLAVE_OOB_CFG, &slave_config) == -1) - return -1; + if (espi_get_configuration(ESPI_SLAVE_OOB_CFG, &slave_config) != CB_SUCCESS) + return CB_ERR; slave_config |= ESPI_SLAVE_CHANNEL_ENABLE; @@ -889,20 +892,21 @@ ESPI_OOB_CH_EN); } -static int espi_setup_flash_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) +static enum cb_err espi_setup_flash_channel(const struct espi_config *mb_cfg, + uint32_t slave_caps) { uint32_t slave_config; if (!mb_cfg->flash_ch_en) - return 0; + return CB_SUCCESS; if (!espi_slave_supports_flash_channel(slave_caps)) { printk(BIOS_ERR, "Error: eSPI slave doesn't support flash channel!\n"); - return -1; + return CB_ERR; } - if (espi_get_configuration(ESPI_SLAVE_FLASH_CFG, &slave_config) == -1) - return -1; + if (espi_get_configuration(ESPI_SLAVE_FLASH_CFG, &slave_config) != CB_SUCCESS) + return CB_ERR; slave_config |= ESPI_SLAVE_CHANNEL_ENABLE; @@ -968,7 +972,7 @@ * Send in-band reset * The resets affects both host and slave devices, so set initial config again. */ - if (espi_send_reset() == -1) { + if (espi_send_reset() != CB_SUCCESS) { printk(BIOS_ERR, "Error: In-band reset failed!\n"); return -1; } @@ -978,7 +982,7 @@ * Boot sequence: Step 3 * Get configuration of slave device. */ - if (espi_get_general_configuration(&slave_caps) == -1) { + if (espi_get_general_configuration(&slave_caps) != CB_SUCCESS) { printk(BIOS_ERR, "Error: Slave GET_CONFIGURATION failed!\n"); return -1; } @@ -988,7 +992,7 @@ * Step 4: Write slave device general config * Step 5: Set host slave config */ - if (espi_set_general_configuration(cfg, slave_caps) == -1) { + if (espi_set_general_configuration(cfg, slave_caps) != CB_SUCCESS) { printk(BIOS_ERR, "Error: Slave SET_CONFIGURATION failed!\n"); return -1; } @@ -1004,34 +1008,34 @@ * Channel setup */ /* Set up VW first so we can deassert PLTRST#. */ - if (espi_setup_vw_channel(cfg, slave_caps) == -1) { + if (espi_setup_vw_channel(cfg, slave_caps) != CB_SUCCESS) { printk(BIOS_ERR, "Error: Setup VW channel failed!\n"); return -1; } /* Assert PLTRST# if VW channel is enabled by mainboard. */ - if (espi_send_pltrst(cfg, true) == -1) { + if (espi_send_pltrst(cfg, true) != CB_SUCCESS) { printk(BIOS_ERR, "Error: PLTRST# assertion failed!\n"); return -1; } /* De-assert PLTRST# if VW channel is enabled by mainboard. */ - if (espi_send_pltrst(cfg, false) == -1) { + if (espi_send_pltrst(cfg, false) != CB_SUCCESS) { printk(BIOS_ERR, "Error: PLTRST# deassertion failed!\n"); return -1; } - if (espi_setup_periph_channel(cfg, slave_caps) == -1) { + if (espi_setup_periph_channel(cfg, slave_caps) != CB_SUCCESS) { printk(BIOS_ERR, "Error: Setup Periph channel failed!\n"); return -1; } - if (espi_setup_oob_channel(cfg, slave_caps) == -1) { + if (espi_setup_oob_channel(cfg, slave_caps) != CB_SUCCESS) { printk(BIOS_ERR, "Error: Setup OOB channel failed!\n"); return -1; } - if (espi_setup_flash_channel(cfg, slave_caps) == -1) { + if (espi_setup_flash_channel(cfg, slave_caps) != CB_SUCCESS) { printk(BIOS_ERR, "Error: Setup Flash channel failed!\n"); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/60207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8c703f62babac31948d0878e91bd31b31bebc01 Gerrit-Change-Number: 60207 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/lpc/espi_util: simplify espi_configure_decodes
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60206 ) Change subject: soc/amd/common/lpc/espi_util: simplify espi_configure_decodes ...................................................................... soc/amd/common/lpc/espi_util: simplify espi_configure_decodes The intermediate ret variable isn't needed. espi_open_generic_io_window only returns 0 or -1, so if ret is != 0, it has to be -1. This is a preparation to use the enum cb_err type for the return values. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia6c7f4cedf8c2defadcf4c4da1697a97c7b401f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60206 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 4 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 7261bb9..d495a0e 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -300,17 +300,16 @@ static int espi_configure_decodes(const struct espi_config *cfg) { - int i, ret; + int i; espi_enable_decode(cfg->std_io_decode_bitmap); for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { if (cfg->generic_io_range[i].size == 0) continue; - ret = espi_open_generic_io_window(cfg->generic_io_range[i].base, - cfg->generic_io_range[i].size); - if (ret) - return ret; + if (espi_open_generic_io_window(cfg->generic_io_range[i].base, + cfg->generic_io_range[i].size)) + return -1; } return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/60206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6c7f4cedf8c2defadcf4c4da1697a97c7b401f2 Gerrit-Change-Number: 60206 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/lpc/espi_util: simplify espi_get_general_configuration
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60205 ) Change subject: soc/amd/common/lpc/espi_util: simplify espi_get_general_configuration ...................................................................... soc/amd/common/lpc/espi_util: simplify espi_get_general_configuration The intermediate ret variable isn't needed. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4e6747cf468c5ba8da6c1a3b20022851e32ad951 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60205 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 4eb700b..7261bb9 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -639,8 +639,7 @@ static int espi_get_general_configuration(uint32_t *config) { - int ret = espi_get_configuration(ESPI_SLAVE_GENERAL_CFG, config); - if (ret == -1) + if (espi_get_configuration(ESPI_SLAVE_GENERAL_CFG, config) == -1) return -1; espi_show_slave_general_configuration(*config); -- To view, visit https://review.coreboot.org/c/coreboot/+/60205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e6747cf468c5ba8da6c1a3b20022851e32ad951 Gerrit-Change-Number: 60205 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne/fch: disable 48MHz output in S0i3
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60125 ) Change subject: soc/amd/cezanne/fch: disable 48MHz output in S0i3 ...................................................................... soc/amd/cezanne/fch: disable 48MHz output in S0i3 S0i3 is a low power state which reduces the power consumption to about the level of the S3 suspend state where the DRAM is kept in a self- refresh state and most of the rest of the system is powered down. So everything that can be switched off in the S0i3 state should be switched off in order to maximize the standby time. BUG=b:210722314 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If445f5825dc7b795c95d73c061156cc485421ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/60125 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/fch.c M src/soc/amd/cezanne/include/soc/southbridge.h 2 files changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Raul Rangel: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 8cd1212..2c57f08 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -78,6 +78,8 @@ uint32_t ctrl = misc_read32(MISC_CLK_CNTL0); /* Enable BP_X48M0 Clock Output */ ctrl |= BP_X48M0_OUTPUT_EN; + /* Disable clock output in S0i3 */ + ctrl |= BP_X48M0_S0I3_DIS; misc_write32(MISC_CLK_CNTL0, ctrl); } diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 3bba559..4f372ad 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -110,6 +110,7 @@ #define USB_PHY_CMCLK_S0I3_DIS BIT(9) #define USB_PHY_CMCLK_S5_DIS BIT(10) #define MISC_CLK_CNTL0 0x40 /* named MISC_CLK_CNTL1 on Picasso */ +#define BP_X48M0_S0I3_DIS BIT(4) #define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ #define MISC_I2C0_PAD_CTRL 0xd8 #define MISC_I2C1_PAD_CTRL 0xdc -- To view, visit https://review.coreboot.org/c/coreboot/+/60125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If445f5825dc7b795c95d73c061156cc485421ada Gerrit-Change-Number: 60125 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/stoneyridge/fch: add GNVS-related TODOs
by Felix Held (Code Review) 20 Dec '21

20 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60196 ) Change subject: soc/amd/stoneyridge/fch: add GNVS-related TODOs ...................................................................... soc/amd/stoneyridge/fch: add GNVS-related TODOs The AOAC device states shouldn't be stored in GNVS, but be read from the AOAC registers during runtime. Same for the EHCI controller's BAR0. The location and size of the XHCI firmware can either be statically determined at build-time or have coreboot generate ACPI objects that contain the needed addresses. Since I can't easily test changes that require booting to a desktop on Stoneyridge at the moment, only add TODOs for now. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Change-Id: I3691b05606b9430cb60923780a6131993a9887d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60196 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/fch.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/fch.c b/src/soc/amd/stoneyridge/fch.c index 16802ef..3037165 100644 --- a/src/soc/amd/stoneyridge/fch.c +++ b/src/soc/amd/stoneyridge/fch.c @@ -165,12 +165,14 @@ gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE; gnvs->fw03 = fwsize << 16; + /* TODO: This might break if the OS decides to re-allocate the PCI BARs. */ gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0) & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; } void fch_final(void *chip_info) { + /* TODO: The AOAC states and EHCI/XHCI addresses should be moved out of GNVS */ struct global_nvs *gnvs = acpi_get_gnvs(); if (gnvs) { set_sb_aoac(&gnvs->aoac); -- To view, visit https://review.coreboot.org/c/coreboot/+/60196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3691b05606b9430cb60923780a6131993a9887d4 Gerrit-Change-Number: 60196 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2021