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Change subject: [RFC]soc/intel/icelake: Drop unmaintained platform
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
.------,
,'_____,'|
| //| |
| | |
| // | ;
|______|'._
`._ `;
`-._.'
___ A
| | {*}
| | __V__
|_|o_|%%%|0_
| |
| |
|_______|
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Change subject: soc/intel/jsl: Add CdClock config
......................................................................
Patch Set 14:
(1 comment)
File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/60009/comment/dc2f1d81_153d80ca
PS14, Line 209: register "CdClock" = "0xff"
Is this the default config in FSP? Are you planning to upload a follow-up change for Magolor?
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Change subject: Revert "vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2471_02"
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60262/comment/7a72df3c_0d040612
PS1, Line 10:
Reason for revert?
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Change subject: [RFC]soc/intel/icelake: Drop unmaintained platform
......................................................................
Patch Set 2: Code-Review+1
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