coreboot-gerrit December 2021

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Change in coreboot[master]: mb/google/brya/var/taeko4es: Fix PLD group order (W/A)
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60187 ) Change subject: mb/google/brya/var/taeko4es: Fix PLD group order (W/A) ...................................................................... mb/google/brya/var/taeko4es: Fix PLD group order (W/A) In commit 667471b8d8 (ec/google/chromeec: Add PLD to EC conn in ACPI table), PLD is added to ACPI table. It causes the DUT to not boot into the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2 to solve this issue. Fixes: 667471b8d8 ("ec/google/chromeec: Add PLD to EC conn in ACPI table") BUG=b:209723556 BRANCH=none TEST=build coreboot and boot into OS. Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: Iff1302fa758bcde1ce8b03c16f7cc6eac807e5c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60187 Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/taeko4es/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb index 5ad69ac..b82e9de 100644 --- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb @@ -445,7 +445,7 @@ chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "group" = "ACPI_PLD_GROUP(2, 1)" device ref tcss_usb3_port3 on probe DB_USB DB_USB3_NO_A end @@ -465,7 +465,7 @@ chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "group" = "ACPI_PLD_GROUP(2, 1)" device ref usb2_port3 on probe DB_USB DB_USB3_NO_A end -- To view, visit https://review.coreboot.org/c/coreboot/+/60187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff1302fa758bcde1ce8b03c16f7cc6eac807e5c9 Gerrit-Change-Number: 60187 Gerrit-PatchSet: 2 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/intel/common/rcba_pirq: Use correct size_t length modifier
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60194 ) Change subject: sb/intel/common/rcba_pirq: Use correct size_t length modifier ...................................................................... sb/intel/common/rcba_pirq: Use correct size_t length modifier Building an image for the Lenovo T60 with `x86_64-linux-gnu-gcc-11` fails with the format warning below. CC ramstage/southbridge/intel/common/rcba_pirq.o src/southbridge/intel/common/rcba_pirq.c: In function 'intel_acpi_gen_def_acpi_pirq': src/southbridge/intel/common/rcba_pirq.c:86:69: error: format '%ld' expects argument of type 'long int', but argument 5 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] 86 | printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%ld\n", | ~~^ | | | long int | %d 87 | dev_path(dev), int_pin - PCI_INT_A, 88 | pirq_idx(pin_irq_map[map_count].pic_pirq)); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | size_t {aka unsigned int} The return value of `pirq_idx()` is of type `size_t`, so use the appropriate length modifier `z`. Change-Id: I7af24cee536b81e4825b77942bcac75afeb9f476 Found-by: gcc (Debian 11.2.0-13) 11.2.0 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60194 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/southbridge/intel/common/rcba_pirq.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c index 75dad0d..c9f1518 100644 --- a/src/southbridge/intel/common/rcba_pirq.c +++ b/src/southbridge/intel/common/rcba_pirq.c @@ -83,7 +83,7 @@ pin_irq_map[map_count].pic_pirq = pirq; /* PIRQs are mapped to GSIs starting at 16 */ pin_irq_map[map_count].apic_gsi = 16 + pirq_idx(pirq); - printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%ld\n", + printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%zd\n", dev_path(dev), int_pin - PCI_INT_A, pirq_idx(pin_irq_map[map_count].pic_pirq)); map_count++; -- To view, visit https://review.coreboot.org/c/coreboot/+/60194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7af24cee536b81e4825b77942bcac75afeb9f476 Gerrit-Change-Number: 60194 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/pmc_mux/conn: Change usb{23}_port_number fields to devi...
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60143 ) Change subject: drivers/intel/pmc_mux/conn: Change usb{23}_port_number fields to device pointers ...................................................................... drivers/intel/pmc_mux/conn: Change usb{23}_port_number fields to device pointers Currently, the pmc_mux/conn driver uses integer fields to store the USB-2 and USB-3 port numbers from the SoC's point of view. Specifying these as integers in the devicetree is error-prone, and this information can instead be represented using pointers to the USB-2 and USB-3 devices. The port numbers can then be obtained from the paths of the linked devices, i.e. dev->path.usb.port_id. Modify the driver to store device pointers instead of integer port numbers, and update all devicetrees using the driver. These are the mainboards affected (all are Intel TGL or ADL based): google/brya google/volteer intel/adlrvp intel/shadowmountain intel/tglrvp system76/darp7 system76/galp5 system76/lemp10 Command used to update the devicetrees: git grep -l "usb._port_number" src/mainboard/ | \ xargs sed -i \ -e 's/register "usb2_port_number" = "\(.*\)"/use usb2_port\1 as usb2_port/g' \ -e 's/register "usb3_port_number" = "\(.*\)"/use tcss_usb3_port\1 as usb3_port/g' BUG=b:208502191 TEST=Build test all affected boards. On brya0, boot device and check that the ACPI tables generated with and without the change are the same. Change-Id: I5045b8ea57e8ca6f9ebd7d68a19486736b7e2809 Signed-off-by: Reka Norman <rekanorman(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60143 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/drivers/intel/pmc_mux/conn/chip.h M src/drivers/intel/pmc_mux/conn/conn.c M src/mainboard/google/brya/variants/anahera/overridetree.cb M src/mainboard/google/brya/variants/anahera4es/overridetree.cb M src/mainboard/google/brya/variants/brask/overridetree.cb M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/brya4es/overridetree.cb M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/overridetree.cb M src/mainboard/google/brya/variants/kano/overridetree.cb M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko4es/overridetree.cb M src/mainboard/google/volteer/variants/chronicler/overridetree.cb M src/mainboard/google/volteer/variants/collis/overridetree.cb M src/mainboard/google/volteer/variants/copano/overridetree.cb M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/drobit/overridetree.cb M src/mainboard/google/volteer/variants/eldrid/overridetree.cb M src/mainboard/google/volteer/variants/elemi/overridetree.cb M src/mainboard/google/volteer/variants/lindar/overridetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/todor/overridetree.cb M src/mainboard/google/volteer/variants/voema/overridetree.cb M src/mainboard/google/volteer/variants/volet/overridetree.cb M src/mainboard/google/volteer/variants/volteer/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb M src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb M src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb M src/mainboard/intel/adlrvp/variants/adlrvp_p_mchp/overridetree.cb M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/system76/darp7/devicetree.cb M src/mainboard/system76/galp5/devicetree.cb M src/mainboard/system76/lemp10/devicetree.cb 41 files changed, 173 insertions(+), 168 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Tim Crawford: Looks good to me, but someone else must approve diff --git a/src/drivers/intel/pmc_mux/conn/chip.h b/src/drivers/intel/pmc_mux/conn/chip.h index 96347ae..08a08e1 100644 --- a/src/drivers/intel/pmc_mux/conn/chip.h +++ b/src/drivers/intel/pmc_mux/conn/chip.h @@ -6,10 +6,10 @@ #include <boot/coreboot_tables.h> struct drivers_intel_pmc_mux_conn_config { - /* 1-based port numbers (from SoC point of view) */ - int usb2_port_number; - /* 1-based port numbers (from SoC point of view) */ - int usb3_port_number; + /* A pointer to the SoC's USB-2 device */ + DEVTREE_CONST struct device *usb2_port; + /* A pointer to the SoC's USB-3 device */ + DEVTREE_CONST struct device *usb3_port; /* Orientation of the sideband signals (SBU) */ enum type_c_orientation sbu_orientation; /* Orientation of the High Speed lines */ diff --git a/src/drivers/intel/pmc_mux/conn/conn.c b/src/drivers/intel/pmc_mux/conn/conn.c index caff166..f238397 100644 --- a/src/drivers/intel/pmc_mux/conn/conn.c +++ b/src/drivers/intel/pmc_mux/conn/conn.c @@ -16,6 +16,11 @@ total_conn_count++; } +static unsigned int get_usb_port_number(const struct device *usb_port) +{ + return usb_port->path.usb.port_id + 1; +} + static struct type_c_info *conn_get_cbmem_buffer(void) { struct type_c_info *info; @@ -57,8 +62,8 @@ count = info->port_count; port_info = &info->port_info[count]; - port_info->usb2_port_number = config->usb2_port_number; - port_info->usb3_port_number = config->usb3_port_number; + port_info->usb2_port_number = get_usb_port_number(config->usb2_port); + port_info->usb3_port_number = get_usb_port_number(config->usb3_port); port_info->sbu_orientation = config->sbu_orientation; port_info->data_orientation = config->hsl_orientation; @@ -109,8 +114,8 @@ /* _DSD, Device-Specific Data */ dsd = acpi_dp_new_table("_DSD"); - acpi_dp_add_integer(dsd, "usb2-port-number", config->usb2_port_number); - acpi_dp_add_integer(dsd, "usb3-port-number", config->usb3_port_number); + acpi_dp_add_integer(dsd, "usb2-port-number", get_usb_port_number(config->usb2_port)); + acpi_dp_add_integer(dsd, "usb3-port-number", get_usb_port_number(config->usb3_port)); /* * The kernel assumes that these Type-C signals (SBUs and HSLs) follow the CC lines, @@ -161,8 +166,8 @@ return false; mux_config = conn->chip_info; - *usb2_port = mux_config->usb2_port_number; - *usb3_port = mux_config->usb3_port_number; + *usb2_port = get_usb_port_number(mux_config->usb2_port); + *usb3_port = get_usb_port_number(mux_config->usb3_port); return true; }; diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index 118ce0c..97be625 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -282,13 +282,13 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 1 alias conn1 on end end end diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb index 118ce0c..97be625 100644 --- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb @@ -282,13 +282,13 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 1 alias conn1 on end end end diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index d1931cf..fbb64ff 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -188,18 +188,18 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "2" - register "usb3_port_number" = "2" + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port device generic 1 alias conn1 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 2 alias conn2 on end end end diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 3822a2c..cae2257 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -626,18 +626,18 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "2" - register "usb3_port_number" = "2" + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port device generic 1 alias conn1 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 2 alias conn2 on end end end diff --git a/src/mainboard/google/brya/variants/brya4es/overridetree.cb b/src/mainboard/google/brya/variants/brya4es/overridetree.cb index 3822a2c..cae2257 100644 --- a/src/mainboard/google/brya/variants/brya4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya4es/overridetree.cb @@ -626,18 +626,18 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "2" - register "usb3_port_number" = "2" + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port device generic 1 alias conn1 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 2 alias conn2 on end end end diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index f9301fe..a0643c5 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -309,13 +309,13 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 2 alias conn2 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "2" - register "usb3_port_number" = "2" + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port device generic 1 alias conn1 on end end end diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 3d8f52b..e804635 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -254,13 +254,13 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "2" - register "usb3_port_number" = "3" + use usb2_port2 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 1 alias conn1 on end end end diff --git a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb index d0d54d7..5f8bd0e 100644 --- a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb @@ -217,13 +217,13 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "2" - register "usb3_port_number" = "3" + use usb2_port2 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 1 alias conn1 on end end end diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index a4a5c54..a7e4271 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -487,13 +487,13 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 1 alias conn1 on end end end diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 0ddf2b1..7ef832c 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -310,13 +310,13 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 1 alias conn1 on end end end diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb index fffc1d0..75610b8 100644 --- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb @@ -304,13 +304,13 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 1 alias conn1 on end end end diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 5aa84bdc..9773076 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -436,13 +436,13 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 1 alias conn1 on end end end diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index 9ffc6a0..a31d025 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -440,13 +440,13 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 1 alias conn1 on end end end diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 985745f..b82e9de 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -421,13 +421,13 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 2 alias conn1 on end end end diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb index dbca8ee..5ad69ac 100644 --- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb @@ -421,13 +421,13 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 2 alias conn1 on end end end diff --git a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb index 4b9f095..93ed52b 100644 --- a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb +++ b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb @@ -264,14 +264,14 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU & HSL follow CC device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/collis/overridetree.cb b/src/mainboard/google/volteer/variants/collis/overridetree.cb index 2fe5001..3323bdf 100644 --- a/src/mainboard/google/volteer/variants/collis/overridetree.cb +++ b/src/mainboard/google/volteer/variants/collis/overridetree.cb @@ -205,15 +205,15 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "5" - register "usb3_port_number" = "1" + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "2" + use usb2_port3 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/copano/overridetree.cb b/src/mainboard/google/volteer/variants/copano/overridetree.cb index 6ea6fd58..7ffa7ab 100644 --- a/src/mainboard/google/volteer/variants/copano/overridetree.cb +++ b/src/mainboard/google/volteer/variants/copano/overridetree.cb @@ -230,15 +230,15 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "5" - register "usb3_port_number" = "1" + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "2" + use usb2_port3 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index a36ad1a..378d4e2 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -211,15 +211,15 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb index 14a5ecf..a31017e 100644 --- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -209,15 +209,15 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index f357f0d..9354418 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -211,14 +211,14 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU & HSL follow CC device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 9ce349b..22230ab 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -281,14 +281,14 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU & HSL follow CC device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 9dfd56c..2eb482d 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -289,14 +289,14 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU & HSL follows CC device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 53b0c42..6d29818 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -158,15 +158,15 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "5" - register "usb3_port_number" = "1" + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "2" + use usb2_port3 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb index ece746b..eb61053 100644 --- a/src/mainboard/google/volteer/variants/todor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb @@ -147,15 +147,15 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "5" - register "usb3_port_number" = "1" + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "2" + use usb2_port3 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index 082dfdf..8fdc067 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -115,13 +115,13 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "5" - register "usb3_port_number" = "1" + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "2" + use usb2_port3 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/volet/overridetree.cb b/src/mainboard/google/volteer/variants/volet/overridetree.cb index 1d11063..f4e2255 100644 --- a/src/mainboard/google/volteer/variants/volet/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volet/overridetree.cb @@ -152,13 +152,13 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index f3b7549..9375af3 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -221,14 +221,14 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU & HSL follow CC device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port device generic 1 alias conn1 on end end end diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 7fe38a9..d024835 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -288,14 +288,14 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU & HSL follow CC device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port device generic 1 alias conn1 on end end end diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 2efc3ed..4bca103 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -244,15 +244,15 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb index 133a737..a3860c6 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb @@ -14,15 +14,15 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "2" - register "usb3_port_number" = "2" + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb index e78d00f..de5471c 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb @@ -34,22 +34,22 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "2" - register "usb3_port_number" = "2" + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 2 alias conn2 on end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p_mchp/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p_mchp/overridetree.cb index a23db8c..91073f7 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p_mchp/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p_mchp/overridetree.cb @@ -14,15 +14,15 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "2" - register "usb3_port_number" = "2" + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 6cf83d2..5757392 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -279,15 +279,15 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "6" - register "usb3_port_number" = "1" + use usb2_port6 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 47c4368..201983c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -319,15 +319,15 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "6" - register "usb3_port_number" = "3" + use usb2_port6 as usb2_port + use tcss_usb3_port3 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "7" - register "usb3_port_number" = "4" + use usb2_port7 as usb2_port + use tcss_usb3_port4 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index cd5493b..d76c0f5 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -323,15 +323,15 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "6" - register "usb3_port_number" = "3" + use usb2_port6 as usb2_port + use tcss_usb3_port3 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "5" - register "usb3_port_number" = "2" + use usb2_port5 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb index dc369ad..75b0836 100644 --- a/src/mainboard/system76/darp7/devicetree.cb +++ b/src/mainboard/system76/darp7/devicetree.cb @@ -316,8 +316,8 @@ device generic 0 on chip drivers/intel/pmc_mux/conn # J_TYPEC2 - register "usb2_port_number" = "6" - register "usb3_port_number" = "1" + use usb2_port6 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU & HSL follow CC device generic 0 alias conn0 on end end diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb index 3764d07..880da1e 100644 --- a/src/mainboard/system76/galp5/devicetree.cb +++ b/src/mainboard/system76/galp5/devicetree.cb @@ -320,8 +320,8 @@ device generic 0 on chip drivers/intel/pmc_mux/conn # J_TYPEC2 - register "usb2_port_number" = "6" - register "usb3_port_number" = "1" + use usb2_port6 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU & HSL follow CC device generic 0 alias conn0 on end end diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb index 21928ec..96ee0a1 100644 --- a/src/mainboard/system76/lemp10/devicetree.cb +++ b/src/mainboard/system76/lemp10/devicetree.cb @@ -281,8 +281,8 @@ device generic 0 on chip drivers/intel/pmc_mux/conn # J_TYPEC1 - register "usb2_port_number" = "3" - register "usb3_port_number" = "1" + use usb2_port3 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU & HSL follow CC device generic 0 alias conn0 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/60143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5045b8ea57e8ca6f9ebd7d68a19486736b7e2809 Gerrit-Change-Number: 60143 Gerrit-PatchSet: 5 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: update USB 2.0 Lane Parameter settings...
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60239 ) Change subject: mb/google/guybrush/var/dewatt: update USB 2.0 Lane Parameter settings for USB ports ...................................................................... mb/google/guybrush/var/dewatt: update USB 2.0 Lane Parameter settings for USB ports Tune the USB phy settings to update txpreempamptune to 3 and txvreftune to 6 for passing USB 2.0 SI Eye diagram measurement (port 0/1/4). BUG=b:199468920 TEST= emerge-guybrush coreboot; pass USB 2.0 SI Eye diagram measurement. Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: Ie46c9019186f1893d736fc2806ab74a4f1171be7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60239 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/variants/dewatt/overridetree.cb 1 file changed, 40 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Rob Barnes: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb index 9366ea6..f3fd0e6 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb @@ -18,6 +18,46 @@ register "telemetry_vddcrsocfull_scale_current_mA" = "30314" #mA register "telemetry_vddcrsocoffset" = "560" + #USB 2.0 phy config + register "usb_phy" = "{ + /* Left USB C0 Port */ + .Usb2PhyPort[0] = { + .compdstune = 3, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 3, + .txpreemppulsetune = 0, + .txrisetune = 1, + .txvreftune = 6, + .txhsxvtune = 3, + .txrestune = 1, + }, + /* Left USB A0 Port */ + .Usb2PhyPort[1] = { + .compdstune = 3, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 3, + .txpreemppulsetune = 0, + .txrisetune = 1, + .txvreftune = 6, + .txhsxvtune = 3, + .txrestune = 1, + }, + /* Right USB C1 Port */ + .Usb2PhyPort[4] = { + .compdstune = 3, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 3, + .txpreemppulsetune = 0, + .txrisetune = 1, + .txvreftune = 6, + .txhsxvtune = 3, + .txrestune = 1, + }, + }" + # I2C Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/60239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie46c9019186f1893d736fc2806ab74a4f1171be7 Gerrit-Change-Number: 60239 Gerrit-PatchSet: 3 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/ironlake: Use `NUM_CHANNELS` macro
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60225 ) Change subject: nb/intel/ironlake: Use `NUM_CHANNELS` macro ...................................................................... nb/intel/ironlake: Use `NUM_CHANNELS` macro Change-Id: I3f4dc26699e3618740af5a0ade1a19599d5a2cc7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60225 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 72c3028..9277477 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -792,7 +792,7 @@ info->max_slots_used_in_channel = 2; else info->max_slots_used_in_channel = 1; - for (channel = 0; channel < 2; channel++) + for (channel = 0; channel < NUM_CHANNELS; channel++) mchbar_write32(0x244 + (channel << 10), ((info->revision < 8) ? 1 : 0x200) | ((2 - info->max_slots_used_in_channel) << 17) | -- To view, visit https://review.coreboot.org/c/coreboot/+/60225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f4dc26699e3618740af5a0ade1a19599d5a2cc7 Gerrit-Change-Number: 60225 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/vell: update overridetree for SSD setting
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60099 ) Change subject: mb/google/brya/var/vell: update overridetree for SSD setting ...................................................................... mb/google/brya/var/vell: update overridetree for SSD setting Change CLKSRC#3 to CLKSRC#1 in override devicetree based on schematics BUG=b:208756696 TEST=emerge-brya coreboot Change-Id: I4d452eaa690a91814739cc1b80966fc3a9f1be37 Signed-off-by: = <robert.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60099 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/vell/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 7ffc7e0..7595c6f 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -125,10 +125,10 @@ end end device ref pcie4_0 on - # Enable CPU PCIE RP 1 using CLK 0 + # Enable CPU PCIE RP 1 using CLK 1 register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 1, - .clk_src = 3, + .clk_src = 1, }" end device ref cnvi_wifi on 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d452eaa690a91814739cc1b80966fc3a9f1be37 Gerrit-Change-Number: 60099 Gerrit-PatchSet: 5 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/vell: update overridetree for touchpad
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60098 ) Change subject: mb/google/brya/var/vell: update overridetree for touchpad ...................................................................... mb/google/brya/var/vell: update overridetree for touchpad update override devicetree for touchpad based on schematics BUG=b:209554950 TEST=emerge-brya coreboot Change-Id: I835958349537ed490191db7c8e35847630de64ed Signed-off-by: = <robert.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60098 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/vell/overridetree.cb 1 file changed, 16 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 483dce7..7ffc7e0 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -49,6 +49,15 @@ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Smart Card register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + # I2C Port Config + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" device domain 0 on device ref igpu on chip drivers/gfx/generic @@ -212,12 +221,13 @@ end end device ref i2c5 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" - register "wake" = "GPE0_DW2_14" - register "probed" = "1" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2703"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" device i2c 15 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/60098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I835958349537ed490191db7c8e35847630de64ed Gerrit-Change-Number: 60098 Gerrit-PatchSet: 5 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/magolor: Set core display clock to 172.8 MHz
by Nico Huber (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Henry Sun, Ren Kuo, Paul Menzel, Simon Yang, Kane Chen, Karthik Ramasubramanian. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60301 ) Change subject: mb/google/dedede/var/magolor: Set core display clock to 172.8 MHz ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60301/comment/af73496c_c0deea77 PS6, Line 13: recommendation. (refer to src/soc/intel/jasperlake/chip.h) What frequency is chosen by default? And why is FSP choosing a higher than necessary frequency by default? -- To view, visit https://review.coreboot.org/c/coreboot/+/60301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34 Gerrit-Change-Number: 60301 Gerrit-PatchSet: 6 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 23 Dec 2021 14:15:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config
by Nico Huber (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Jamie Chen, Henry Sun, Tim Wawrzynczak, Paul Menzel, Ren Kuo, Simon Yang, Kane Chen, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 ) Change subject: soc/intel/jasperlake: Add CdClock frequency config ...................................................................... Patch Set 17: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60009/comment/1e2ce87e_53e54743 PS17, Line 14: When is this setting needed? When does FSP apply the CdClock setting? always or only when the GOP blob runs? Please also provide all those details in a comment in `chip.h`. Without such details, people usually fall into the trap to specify random values without knowing why. File src/soc/intel/jasperlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/60009/comment/978d3cc6_6d4838b9 PS17, Line 212: params->CdClock = config->cd_clock ? config->cd_clock - 1 : 0xff; So is the comment in `src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h` wrong? Offset 0x0436 - CdClock Frequency selection 0: (Default) Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180 Mhz, 3: 190 Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz, 8: 648 Mhz, 9: 652.8 Mhz 0: Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180 Mhz, 3: 190 Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz, 8: 648 Mhz, 9: 652.8 Mhz If so, why isn't it fixed? -- To view, visit https://review.coreboot.org/c/coreboot/+/60009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Gerrit-Change-Number: 60009 Gerrit-PatchSet: 17 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 23 Dec 2021 14:10:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Change SD Card and Touch pad GPIO PAD_RST to RSMRST
by EricR Lai (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Meera Ravindranath, Nick Vaccaro. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60320 ) Change subject: mb/google/brya: Change SD Card and Touch pad GPIO PAD_RST to RSMRST ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Meera, we would like to fix all the lock pins at time, b/c Finger printer can't work after reboot as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/60320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I558bab39f935ab31a89541c6498a73af70cbf9ee Gerrit-Change-Number: 60320 Gerrit-PatchSet: 4 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 23 Dec 2021 14:02:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2021