coreboot-gerrit December 2021

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Change in coreboot[master]: mb/intel/adlrvp_n: Add support for ADL-N LP5 RVP
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60193 ) Change subject: mb/intel/adlrvp_n: Add support for ADL-N LP5 RVP ...................................................................... mb/intel/adlrvp_n: Add support for ADL-N LP5 RVP Add support for Alder lake N LP5 RVP with board ID 0x7. Since SPD index 7 is unused earlier, ADL-N will use it. Change-Id: Ib2f53e65f75e23793d8c85ee924827446fd9fea7 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60193 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/intel/adlrvp/include/baseboard/variants.h M src/mainboard/intel/adlrvp/memory.c M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/adlrvp/spd/Makefile.inc A src/mainboard/intel/adlrvp/spd/adlrvp_n_lp5.spd.hex 5 files changed, 100 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Maulik V Vaghela: Looks good to me, but someone else must approve Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index 9ab05f6..143679a 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -24,6 +24,8 @@ /* ADL-M LP4 and LP5 RVPs */ ADL_M_LP4 = 0x1, ADL_M_LP5 = 0x2, + /* ADL-N LP5 RVP */ + ADL_N_LP5 = 0x7, }; /* The next set of functions return the gpio table and fill in the number of diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index f4ae541..b917d98 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -290,6 +290,68 @@ }, }; +static const struct mb_cfg adln_lp5_mem_config = { + .type = MEM_TYPE_LP5X, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr1 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr2 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr3 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + .ddr4 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr5 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr6 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr7 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } + }, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_ULT_ULX, + + .LpDdrDqDqsReTraining = 1, + + .lp5x_config = { + .ccc_config = 0xff, + }, +}; + const struct mb_cfg *variant_memory_params(void) { int board_id = get_board_id(); @@ -311,6 +373,8 @@ return &adlm_lp4_mem_config; case ADL_M_LP5: return &adlm_lp5_mem_config; + case ADL_N_LP5: + return &adln_lp5_mem_config; default: die("unsupported board id : 0x%x\n", board_id); } diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 05d2a17..56bd0cd 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -80,6 +80,7 @@ case ADL_P_LP5_2: case ADL_M_LP4: case ADL_M_LP5: + case ADL_N_LP5: memcfg_init(m_cfg, mem_config, &memory_down_spd_info, half_populated); break; default: diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc index 4cb0f98..96869f4 100644 --- a/src/mainboard/intel/adlrvp/spd/Makefile.inc +++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc @@ -7,4 +7,4 @@ SPD_SOURCES += empty # 0b004 SPD_SOURCES += empty # 0b005 SPD_SOURCES += adlrvp_ddr5_mr # 0b006 -SPD_SOURCES += adlrvp_lp5 # 0b007 +SPD_SOURCES += adlrvp_n_lp5 # 0b007 diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_n_lp5.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_n_lp5.spd.hex new file mode 100644 index 0000000..88a1f1f --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_n_lp5.spd.hex @@ -0,0 +1,32 @@ +23 10 13 0E 15 1A B5 08 00 40 00 00 0A 01 00 00 +48 00 0A FF 92 55 05 00 AA 00 90 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/60193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2f53e65f75e23793d8c85ee924827446fd9fea7 Gerrit-Change-Number: 60193 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anilkumar N <anilkumar.n(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: libpayload/libc/fmap: Implement new FlashMap API
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59494 ) Change subject: libpayload/libc/fmap: Implement new FlashMap API ...................................................................... libpayload/libc/fmap: Implement new FlashMap API This patch introduces new FlashMap API, the fmap_locate_area(). It works on cached FlashMap provided in lib_sysinfo.fmap_cache. Change-Id: Idbf9016ce73aa58e17f3ee19920ab83dc6c25abb Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59494 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- A payloads/libpayload/include/fmap.h D payloads/libpayload/include/fmap_serialized.h M payloads/libpayload/include/libpayload.h M payloads/libpayload/libc/fmap.c A payloads/libpayload/tests/libc/Makefile.inc A payloads/libpayload/tests/libc/fmap_locate_area-test.c 6 files changed, 180 insertions(+), 76 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/payloads/libpayload/include/fmap.h b/payloads/libpayload/include/fmap.h new file mode 100644 index 0000000..53ebe23 --- /dev/null +++ b/payloads/libpayload/include/fmap.h @@ -0,0 +1,12 @@ +/* SPDX_License-Identifier: BSD-3-Clause */ + +#ifndef _FMAP_H +#define _FMAP_H + +#include <commonlib/bsd/cb_err.h> +#include <stddef.h> + +/* Looks for area with |name| in FlashMap. Requires lib_sysinfo.fmap_cache. */ +cb_err_t fmap_locate_area(const char *name, size_t *offset, size_t *size); + +#endif /* _FMAP_H */ diff --git a/payloads/libpayload/include/fmap_serialized.h b/payloads/libpayload/include/fmap_serialized.h deleted file mode 100644 index 53a09af..0000000 --- a/payloads/libpayload/include/fmap_serialized.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright 2010, Google Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Google Inc. nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - */ - -#ifndef FLASHMAP_SERIALIZED_H__ -#define FLASHMAP_SERIALIZED_H__ - -#include <stdint.h> - -#define FMAP_SIGNATURE "__FMAP__" -#define FMAP_VER_MAJOR 1 /* this header's FMAP minor version */ -#define FMAP_VER_MINOR 1 /* this header's FMAP minor version */ -#define FMAP_STRLEN 32 /* maximum length for strings, */ - /* including null-terminator */ - -enum fmap_flags { - FMAP_AREA_STATIC = 1 << 0, - FMAP_AREA_COMPRESSED = 1 << 1, - FMAP_AREA_RO = 1 << 2, - FMAP_AREA_PRESERVE = 1 << 3, -}; - -/* Mapping of volatile and static regions in firmware binary */ -struct fmap_area { - uint32_t offset; /* offset relative to base */ - uint32_t size; /* size in bytes */ - uint8_t name[FMAP_STRLEN]; /* descriptive name */ - uint16_t flags; /* flags for this area */ -} __packed; - -struct fmap { - uint8_t signature[8]; /* "__FMAP__" (0x5F5F464D41505F5F) */ - uint8_t ver_major; /* major version */ - uint8_t ver_minor; /* minor version */ - uint64_t base; /* address of the firmware binary */ - uint32_t size; /* size of firmware binary in bytes */ - uint8_t name[FMAP_STRLEN]; /* name of this firmware binary */ - uint16_t nareas; /* number of areas described by - fmap_areas[] below */ - struct fmap_area areas[]; -} __packed; - -#endif /* FLASHMAP_SERIALIZED_H__ */ diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 3895710..8d8336f 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -45,10 +45,11 @@ #include <stdbool.h> #include <libpayload-config.h> #include <cbgfx.h> +#include <commonlib/bsd/fmap_serialized.h> #include <ctype.h> #include <die.h> #include <endian.h> -#include <fmap_serialized.h> +#include <fmap.h> #include <ipchksum.h> #include <kconfig.h> #include <stddef.h> diff --git a/payloads/libpayload/libc/fmap.c b/payloads/libpayload/libc/fmap.c index b7d6491..2d185a7 100644 --- a/payloads/libpayload/libc/fmap.c +++ b/payloads/libpayload/libc/fmap.c @@ -28,10 +28,60 @@ #include <libpayload-config.h> #include <libpayload.h> +#include <commonlib/bsd/fmap_serialized.h> #include <coreboot_tables.h> #include <cbfs.h> -#include <fmap_serialized.h> +#include <boot_device.h> #include <stdint.h> +#include <arch/virtual.h> + +/* Private fmap cache. */ +static struct fmap *_fmap_cache; + +static cb_err_t fmap_find_area(struct fmap *fmap, const char *name, size_t *offset, + size_t *size) +{ + for (size_t i = 0; i < le32toh(fmap->nareas); ++i) { + if (strncmp((const char *)fmap->areas[i].name, name, FMAP_STRLEN) != 0) + continue; + if (offset) + *offset = le32toh(fmap->areas[i].offset); + if (size) + *size = le32toh(fmap->areas[i].size); + return CB_SUCCESS; + } + + return CB_ERR; +} + +static bool fmap_is_signature_valid(struct fmap *fmap) +{ + return memcmp(fmap->signature, FMAP_SIGNATURE, sizeof(fmap->signature)) == 0; +} + +static bool fmap_setup_cache(void) +{ + /* Use FMAP cache if available */ + if (lib_sysinfo.fmap_cache + && fmap_is_signature_valid((struct fmap *)phys_to_virt(lib_sysinfo.fmap_cache))) { + _fmap_cache = (struct fmap *)phys_to_virt(lib_sysinfo.fmap_cache); + return true; + } + + return false; +} + +cb_err_t fmap_locate_area(const char *name, size_t *offset, size_t *size) +{ + if (!_fmap_cache && !fmap_setup_cache()) + return CB_ERR; + + return fmap_find_area(_fmap_cache, name, offset, size); +} + +/*********************************************************************************************** + * LEGACY CODE * + **********************************************************************************************/ int fmap_region_by_name(const uint32_t fmap_offset, const char * const name, uint32_t * const offset, uint32_t * const size) diff --git a/payloads/libpayload/tests/libc/Makefile.inc b/payloads/libpayload/tests/libc/Makefile.inc new file mode 100644 index 0000000..5f92bdf --- /dev/null +++ b/payloads/libpayload/tests/libc/Makefile.inc @@ -0,0 +1,3 @@ +tests-y += fmap_locate_area-test + +fmap_locate_area-test-srcs += tests/libc/fmap_locate_area-test.c diff --git a/payloads/libpayload/tests/libc/fmap_locate_area-test.c b/payloads/libpayload/tests/libc/fmap_locate_area-test.c new file mode 100644 index 0000000..ce7c36b --- /dev/null +++ b/payloads/libpayload/tests/libc/fmap_locate_area-test.c @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "../libc/fmap.c" + +#include <libpayload.h> +#include <tests/test.h> + + +/* Mocks */ +struct sysinfo_t lib_sysinfo; +unsigned long virtual_offset = 0; + +static void reset_fmap_cache(void) +{ + _fmap_cache = NULL; +} + +static int setup_fmap_test(void **state) +{ + reset_fmap_cache(); + lib_sysinfo.fmap_cache = 0; + return 0; +} + +static void test_fmap_locate_area_no_fmap_available(void **state) +{ + size_t offset = 0; + size_t size = 0; + + assert_int_equal(-1, fmap_locate_area("COREBOOT", &offset, &size)); +} + +static void test_fmap_locate_area_incorrect_signature(void **state) +{ + size_t offset = 0; + size_t size = 0; + struct fmap mock_fmap = { + .signature = "NOT_MAP", + }; + lib_sysinfo.fmap_cache = (uintptr_t)&mock_fmap; + + assert_int_equal(-1, fmap_locate_area("COREBOOT", &offset, &size)); +} + +static void test_fmap_locate_area_success(void **state) +{ + size_t offset = 0; + size_t size = 0; + struct fmap mock_fmap = { + .signature = FMAP_SIGNATURE, + .ver_major = 1, + .ver_minor = 1, + .base = 0xAABB, + .size = 0x10000, + .nareas = 3, + }; + struct fmap_area area_1 = { + .size = 0x1100, + .offset = 0x11, + .name = {'F', 'I', 'R', 'S', 'T', '_', 'A', 'R', 'E', 'A', 0}, + .flags = 0, + }; + struct fmap_area area_2 = { + .size = 0x2200, + .offset = 0x1111, + .name = {'S', 'E', 'C', 'O', 'N', 'D', '_', 'A', 'R', 'E', 'A', 0}, + .flags = 0, + }; + struct fmap_area area_3 = { + .size = 0x100, + .offset = 0x3311, + .name = {'T', 'H', 'I', 'R', 'D', '_', 'A', 'R', 'E', 'A', 0}, + .flags = 0, + }; + u8 fmap_buffer[sizeof(struct fmap) + 3 * sizeof(struct fmap_area)]; + memcpy(fmap_buffer, &mock_fmap, sizeof(mock_fmap)); + memcpy(&fmap_buffer[sizeof(mock_fmap)], &area_1, sizeof(area_1)); + memcpy(&fmap_buffer[sizeof(mock_fmap) + sizeof(area_1)], &area_2, sizeof(area_2)); + memcpy(&fmap_buffer[sizeof(mock_fmap) + sizeof(area_1) + sizeof(area_2)], &area_3, + sizeof(area_3)); + + /* Cache only */ + reset_fmap_cache(); + lib_sysinfo.fmap_cache = (uintptr_t)fmap_buffer; + + assert_int_equal(0, fmap_locate_area("FIRST_AREA", &offset, &size)); + assert_int_equal(area_1.offset, offset); + assert_int_equal(area_1.size, size); + + assert_int_equal(0, fmap_locate_area("THIRD_AREA", &offset, &size)); + assert_int_equal(area_3.offset, offset); + assert_int_equal(area_3.size, size); + + assert_int_equal(0, fmap_locate_area("SECOND_AREA", &offset, &size)); + assert_int_equal(area_2.offset, offset); + assert_int_equal(area_2.size, size); + + reset_fmap_cache(); +} + +#define FMAP_LOCATE_AREA_TEST(fn) cmocka_unit_test_setup(fn, setup_fmap_test) + +int main(void) +{ + const struct CMUnitTest tests[] = { + FMAP_LOCATE_AREA_TEST(test_fmap_locate_area_no_fmap_available), + FMAP_LOCATE_AREA_TEST(test_fmap_locate_area_incorrect_signature), + FMAP_LOCATE_AREA_TEST(test_fmap_locate_area_success), + }; + + return lp_run_group_tests(tests, NULL, NULL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbf9016ce73aa58e17f3ee19920ab83dc6c25abb Gerrit-Change-Number: 59494 Gerrit-PatchSet: 10 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: libpayload: Add commonlib/bsd include path to lpgcc
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60171 ) Change subject: libpayload: Add commonlib/bsd include path to lpgcc ...................................................................... libpayload: Add commonlib/bsd include path to lpgcc coreinfo and nvramcui are using libpayload/bin/lpgcc and libpayload build directory as a base, instead of installing it first. This caused include errors, because commonlib/bsd is not present there. This patch introduces comonlib/bsd include path to lpgcc CFLAGS if it is being built using libpayload build directory as a base. Change-Id: I7d1fe9e5dc3e7c1c1ba825a1bf19972722b42778 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60171 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/bin/lpgcc 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index 3a76f13..a0b736b 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -167,6 +167,8 @@ if [ "$CONFIG_LP_TINYCURSES" = y ]; then _CFLAGS="$_CFLAGS -I$BASE/../curses" fi + + _CFLAGS="$_CFLAGS -I$BASE/../../../src/commonlib/bsd/include" fi # Check for the -fno-stack-protector silliness -- To view, visit https://review.coreboot.org/c/coreboot/+/60171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d1fe9e5dc3e7c1c1ba825a1bf19972722b42778 Gerrit-Change-Number: 60171 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/beadrix: Remove SD controller
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60266 ) Change subject: mb/google/dedede/var/beadrix: Remove SD controller ...................................................................... mb/google/dedede/var/beadrix: Remove SD controller Remove SD controller configurations based on the beadrix's schematic. BUG=b:204882915 BRANCH=None TEST=Built test coreboot image Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Change-Id: Iba6f5cbbe90d9307e5e8080d7063a1881acd7ed9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60266 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/beadrix/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Teddy Shih: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb index 97e77439..c64765b 100644 --- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb +++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb @@ -52,6 +52,7 @@ end end end # USB xHCI + device pci 14.5 off end # SDCard device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""PIXA2635"" -- To view, visit https://review.coreboot.org/c/coreboot/+/60266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba6f5cbbe90d9307e5e8080d7063a1881acd7ed9 Gerrit-Change-Number: 60266 Gerrit-PatchSet: 2 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/beadrix: Add internal USB camera support
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60252 ) Change subject: mb/google/dedede/var/beadrix: Add internal USB camera support ...................................................................... mb/google/dedede/var/beadrix: Add internal USB camera support This change adds internal USB camera into devicetree for beadrix. BUG=b:204882915, b:210772511 BRANCH=None TEST=Built and checked camera device existence with lsusb Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Change-Id: Iddc58c0d27d5da0fa4652f503f15ebb308be18c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60252 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/beadrix/overridetree.cb 1 file changed, 15 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Teddy Shih: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb index e7d940d..97e77439 100644 --- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb +++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb @@ -1,5 +1,8 @@ chip soc/intel/jasperlake + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -37,6 +40,18 @@ }" device domain 0 on + device pci 05.0 off end # IPU - MIPI Camera + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""UFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + end + end + end # USB xHCI device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""PIXA2635"" -- To view, visit https://review.coreboot.org/c/coreboot/+/60252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddc58c0d27d5da0fa4652f503f15ebb308be18c7 Gerrit-Change-Number: 60252 Gerrit-PatchSet: 2 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/beadrix: Enable audio feature
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60250 ) Change subject: mb/google/dedede/var/beadrix: Enable audio feature ...................................................................... mb/google/dedede/var/beadrix: Enable audio feature This change adds ALC5682I audio codec and MAX98360A amplifier for beadrix. BUG=b:204882915, b:210756131 BRANCH=None TEST=Built and heared speaker sound on OS Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Change-Id: I6f12f71ec66acd420471ab9a7612b1821650ad54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60250 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/Kconfig.name M src/mainboard/google/dedede/variants/beadrix/overridetree.cb 2 files changed, 21 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Teddy Shih: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 212f242..b92f137 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -175,3 +175,4 @@ bool "-> Beadrix" select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP + select DRIVERS_GENERIC_MAX98357A diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb index dab4311..e7d940d 100644 --- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb +++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb @@ -48,5 +48,25 @@ device i2c 15 on end end end # I2C 0 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end # I2C 4 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on end + end + end # Intel HDA end end -- To view, visit https://review.coreboot.org/c/coreboot/+/60250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f12f71ec66acd420471ab9a7612b1821650ad54 Gerrit-Change-Number: 60250 Gerrit-PatchSet: 3 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/beadrix: Enable PIXA touchpad
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60246 ) Change subject: mb/google/dedede/var/beadrix: Enable PIXA touchpad ...................................................................... mb/google/dedede/var/beadrix: Enable PIXA touchpad This change adds PIXA touchpad into devicetree for beadrix. BUG=b:204882915, b:203113111 TEST=Built and verified touchpad function Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Change-Id: I0b551554c69d52f0559ace4ad9c1335270dacea9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60246 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/beadrix/overridetree.cb 1 file changed, 11 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved Teddy Shih: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb index 404024b..dab4311 100644 --- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb +++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb @@ -37,6 +37,16 @@ }" device domain 0 on - device pci 15.0 on end + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""PIXA2635"" + register "generic.desc" = ""PIXA Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end # I2C 0 end end -- To view, visit https://review.coreboot.org/c/coreboot/+/60246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b551554c69d52f0559ace4ad9c1335270dacea9 Gerrit-Change-Number: 60246 Gerrit-PatchSet: 2 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/starlabs/labtop: Update VBT
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59727 ) Change subject: mb/starlabs/labtop: Update VBT ...................................................................... mb/starlabs/labtop: Update VBT Using Vbt.bin version 244, with the following changes: * Add 200ms delay to sink (T3) to avoid no response to AUX Channel transaction, which manifests as a repeating, colourful flicker. * Increase maximum supported refresh rate to 120Hz Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ifc03b8f5d45cbbf90fb61d8b08148ed402dd85ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/59727 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Andy Pont <andy.pont(a)sdcsystems.com> --- M src/mainboard/starlabs/labtop/variants/tgl/data.vbt M src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb 2 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Andy Pont: Looks good to me, but someone else must approve diff --git a/src/mainboard/starlabs/labtop/variants/tgl/data.vbt b/src/mainboard/starlabs/labtop/variants/tgl/data.vbt index 67dc497..992a864 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/data.vbt +++ b/src/mainboard/starlabs/labtop/variants/tgl/data.vbt Binary files differ diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb index a3fc715..35c2010 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb @@ -8,10 +8,10 @@ register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Not used but timings left for reference # register "panel_cfg" = "{ - # .up_delay_ms = 0, // T3 + # .up_delay_ms = 2000, // T3 # .backlight_on_delay_ms = 0, // T7 - # .backlight_off_delay_ms = 50, // T9 - # .down_delay_ms = 0, // T10 + # .backlight_off_delay_ms = 2000, // T9 + # .down_delay_ms = 500, // T10 # .cycle_delay_ms = 500, // T12 # .backlight_pwm_hz = 200, // PWM # }" 11 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc03b8f5d45cbbf90fb61d8b08148ed402dd85ec Gerrit-Change-Number: 59727 Gerrit-PatchSet: 13 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/cret: Generate new SPD ID for new memory parts
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58412 ) Change subject: mb/google/dedede/var/cret: Generate new SPD ID for new memory parts ...................................................................... mb/google/dedede/var/cret: Generate new SPD ID for new memory parts Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL 2. Hynix H54G46CYRBX267 BUG=b:203837656 BRANCH=dedede TEST=FW_NAME=cret emerge-dedede coreboot chromeos-bootimage Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I03980858f89e56320ddff3a808110a5f1dd57784 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58412 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/cret/memory/Makefile.inc M src/mainboard/google/dedede/variants/cret/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt 3 files changed, 5 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Shou-Chieh Hsu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/cret/memory/Makefile.inc b/src/mainboard/google/dedede/variants/cret/memory/Makefile.inc index 31d1f7c..5bd1974 100644 --- a/src/mainboard/google/dedede/variants/cret/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/cret/memory/Makefile.inc @@ -4,4 +4,4 @@ # util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/cret/memory src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:F, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:F, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B, K4U6E3S4AB-MGCL, H54G46CYRBX267 diff --git a/src/mainboard/google/dedede/variants/cret/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/cret/memory/dram_id.generated.txt index ae467ec..fc789d3 100644 --- a/src/mainboard/google/dedede/variants/cret/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/cret/memory/dram_id.generated.txt @@ -8,3 +8,5 @@ MT53E512M32D2NP-046 WT:F 0 (0000) K4U6E3S4AA-MGCR 0 (0000) MT53E512M32D1NP-046 WT:B 0 (0000) +K4U6E3S4AB-MGCL 0 (0000) +H54G46CYRBX267 0 (0000) diff --git a/src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt index c1e9e0c..d163884 100644 --- a/src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt @@ -2,3 +2,5 @@ MT53E512M32D2NP-046 WT:F K4U6E3S4AA-MGCR MT53E512M32D1NP-046 WT:B +K4U6E3S4AB-MGCL +H54G46CYRBX267 -- To view, visit https://review.coreboot.org/c/coreboot/+/58412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03980858f89e56320ddff3a808110a5f1dd57784 Gerrit-Change-Number: 58412 Gerrit-PatchSet: 5 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/anahera: Enable SaGv
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60249 ) Change subject: mb/google/brya/var/anahera: Enable SaGv ...................................................................... mb/google/brya/var/anahera: Enable SaGv Enable SaGv support for anahera/anahera4es. BUG=b:211362081 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: I68c916dbc570759dba3a4c32fbb8ebfc6e387be4 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60249 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/anahera/overridetree.cb M src/mainboard/google/brya/variants/anahera4es/overridetree.cb 2 files changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index 97be625..1038798 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -33,6 +33,7 @@ register "gpio_pm[COMM_4]" = "0" register "gpio_pm[COMM_5]" = "0" + register "SaGv" = "SaGv_Enabled" # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb index 97be625..1038798 100644 --- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb @@ -33,6 +33,7 @@ register "gpio_pm[COMM_4]" = "0" register "gpio_pm[COMM_5]" = "0" + register "SaGv" = "SaGv_Enabled" # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/60249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68c916dbc570759dba3a4c32fbb8ebfc6e387be4 Gerrit-Change-Number: 60249 Gerrit-PatchSet: 4 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit December 2021